coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2012-10-26	northbridge/sch: move the \n so it reads a little better	Sebastian Andrzej Siewior
2012-10-26	northbridge/sch: read the size of main memory from the proper register	Sebastian Andrzej Siewior
2012-10-26	northbridge/sch: Read the GPU memory from the correct PCI device	Sebastian Andrzej Siewior
2012-10-26	northbridge/sch: don't overwrite hightables with GPU / TSEG memory	Sebastian Andrzej Siewior
2012-10-07	Remove chip.h files without config structure	Kyösti Mälkki
2012-09-25	HAVE_HIGH_TABLES is gone	Patrick Georgi
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2012-08-08	Cleanup coreboot memory table includes	Kyösti Mälkki
2012-07-27	Intel and GFXUMA: fix MTRR and use uma_resource()	Kyösti Mälkki
2012-07-27	Intel i945 and sch: no memory over 4GB	Kyösti Mälkki
2012-07-20	Intel SCH northbridge: fix resource index	Kyösti Mälkki
2012-07-16	Define global uma_memory variables	Kyösti Mälkki
2012-05-08	Clean up #ifs	Patrick Georgi
2012-04-12	Unify IO APIC address specification	Patrick Georgi
2012-02-17	Avoid ../../.. paths in ASL files	Patrick Georgi
2011-10-15	use acpi.h include instead of manually adding acpi_slp_type.	Stefan Reinauer
2011-10-14	fix compilation of intel/sch northbridge code with gcc 4.6	Stefan Reinauer
2010-12-19	The same mechanisms are used for normal and fallback images.	Stefan Reinauer
2010-12-18	Fix a few whitespace and coding style issues.	Uwe Hermann
2010-12-18	A couple of Poulsbo fixes:	Patrick Georgi
2010-12-18	Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board	Patrick Georgi