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path: root/src/northbridge/intel/sandybridge
AgeCommit message (Expand)Author
2017-06-04Kconfig: Add choice of framebuffer modeNico Huber
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
2017-06-02Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFGNico Huber
2017-05-20nb/intel/sandybridge: Use macros to determine min and max of timAArthur Heymans
2017-05-19nb/intel/sandybridge: Hide additional nb devicesPatrick Rudolph
2017-05-05nb/intel/sandybridge/early_init: Use register namePatrick Rudolph
2017-05-05nb/intel/sandybridge/romstage: Use register namePatrick Rudolph
2017-05-01nb/intel/sandybridge/gma: Set up OpRegion in nb codePatrick Rudolph
2017-04-07nb/intel/sandybridge/raminit: Fix odt stretchPatrick Rudolph
2017-04-07nb/intel/sandybridge/raminit: Always run quick_ram_checkPatrick Rudolph
2017-04-07nb/intel/sandybridge/raminit: Reduce log levelPatrick Rudolph
2017-04-07nb/intel/sandybridge/raminit: Fix normalize_trainingPatrick Rudolph
2017-04-04nb/intel/sandybridge/raminit: Add default valuesPatrick Rudolph
2017-04-04nb/intel/sandybridge/raminit: Add debugging outputPatrick Rudolph
2017-04-04nb/intel/sandybridge/raminit: Add 100MHz refclock supportPatrick Rudolph
2017-04-04nb/intel/sandybridge/raminit: Use Ivy Bridge specific valuesPatrick Rudolph
2017-04-03nb/intel: Deduplicate vbt headerPatrick Rudolph
2017-03-28vboot: Select SoC-specific configuration for all Chrome OS boardsJulius Werner
2017-03-27nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timingsArthur Heymans
2017-01-06nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>Arthur Heymans
2016-12-16nb/intel/sandybridge/raminit: Separate Sandybridge and IvybridgePatrick Rudolph
2016-12-09intel/sandybridge: Use postcar_frame for MTRR setupKyösti Mälkki
2016-12-08nb/intel/sandybridge: Lock PAVPCDennis Wassenberg
2016-12-07MMCONF_SUPPORT: Drop redundant loggingKyösti Mälkki
2016-12-07MMCONF_SUPPORT: Consolidate resource registrationKyösti Mälkki
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
2016-12-06CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
2016-12-05nb/intel/sandybridge/raminit: Split raminit.cPatrick Rudolph
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
2016-11-29nb/intel/nehalem,sandybridge: Hook up libgfxinitNico Huber
2016-11-29nb/intel/sandybridge/raminit: Support CL > 11Patrick Rudolph
2016-11-28nb/intel/sandybridge/raminit: Reset internal state on fallback attemptsPatrick Rudolph
2016-11-22nb/intel/sandybridge/raminit: Do not log inside busy-wait loopKyösti Mälkki
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
2016-11-21nb/intel: Fix some spelling mistakes in comments and stringsMartin Roth
2016-11-20intel sandy/ivy: Improve DIMM replacement detectionKyösti Mälkki
2016-11-20intel sandy/ivy: Skip SPD loading on S3 resume pathKyösti Mälkki
2016-11-20intel sandy/ivy: Move SPD loading after TS_BEFORE_INITRAMKyösti Mälkki
2016-11-20intel sandy/ivy: Change CRC used to detect DIMM replacementKyösti Mälkki
2016-11-20nb/intel/sandybridge/raminit: Fix disable_channelPatrick Rudolph
2016-11-20nb/intel/sandybridge/raminit: Find CMD rate per channelPatrick Rudolph
2016-11-20nb/intel/sandybridge/raminit: Define registersPatrick Rudolph
2016-11-20nb/intel/sandybridge/raminit: Get rid of fallback attemptsPatrick Rudolph
2016-11-20nb/intel/sandybridge/raminit: Fix CAS Write LatencyPatrick Rudolph
2016-11-18intel/sandybridge: Use romstage_handoff for S3Kyösti Mälkki
2016-11-18intel/sandybridge post-car: Redo MTRR settings and stack selectionKyösti Mälkki
2016-11-11intel post-car: Separate files for setup_stack_and_mtrrs()Kyösti Mälkki
2016-11-11intel/sandybridge: Use common ACPI S3 recoveryKyösti Mälkki
2016-10-29nb/intel/sandybridge/gma: Always initialize DP buffer translationNico Huber
2016-10-11nb/intel/*/graphic_init: use sizeof instead of hardcoding edid sizeArthur Heymans
2016-10-11cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZENico Huber
2016-10-04src/northbridge: Remove unnecessary whitespaceElyes HAOUAS
2016-10-04src/northbridge: Remove whitespace after sizeofElyes HAOUAS
2016-09-27northbridge/sandybridge/raminit_mrc.c: fix missing includeMatt DeVillier
2016-09-27nb/intel/*/gma.c: remove spaces at the fake vbt generationArthur Heymans
2016-09-04northbridge/intel/sandybridge: transition away from device_tAntonello Dettori
2016-08-31northbridge/intel: Add required space before opening parenthesis '('Elyes HAOUAS
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
2016-07-31src/northbridge: Capitalize CPU, RAM and ROMElyes HAOUAS
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
2016-07-26intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki
2016-07-07intel/sandybridge: read correct leaf for cpu familyRyan Salsamendi
2016-06-23intel/sandybridge: Fix builds with System Agent blobKyösti Mälkki
2016-06-22intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-20nb/intel/sandybridge/raminit: Use supported CASPatrick Rudolph
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
2016-06-20nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devicesPatrick Rudolph
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
2016-06-12nb/intel/raminit (native): Read PCI mmio size from devicetreePatrick Rudolph
2016-06-12nb/intel: Factor out common MRC codePatrick Rudolph
2016-05-31Fix leaking CONFIG_VGA=yKyösti Mälkki
2016-05-04nb/intel/sandybridge/raminit: support calling dram_freq multiple timesPatrick Rudolph
2016-05-04nb/intel/sandybridge/raminit: add additional fallbacksPatrick Rudolph
2016-04-29nb/intel/sandybridge/raminit: fix regression "always use mrccache"Patrick Rudolph
2016-04-10nb/intel/sandybridge/raminit: always use mrccachePatrick Rudolph
2016-04-05nb/intel/sandybridge/raminit: die in toplevel functionPatrick Rudolph
2016-04-05nb/intel/sandybridge/raminit: prepare raminit for fallbackPatrick Rudolph
2016-03-30nb/intel/sandybridge/raminit: move ram training into seperate functionPatrick Rudolph
2016-03-29nb/intel/sandybridge/raminit: move dimm_info into ramctr_timingPatrick Rudolph
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
2016-03-11nortbridge/sandybridge/mrccache: parse the return code of flash->writeAlexander Couzens
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
2016-03-03nb/intel/sandybridge/raminit: Fill SMBIOS type17 infoPatrick Rudolph
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
2016-03-02nb/intel/sandybridge/raminit: Make discover_timC_write non cyclicPatrick Rudolph
2016-02-28northbridge/intel: add missing #include guardsIru Cai
2016-02-26nb/intel/sandybridge/raminit: Adjust timB to prevent overflowPatrick Rudolph
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
2016-02-20nb/intel/sandybridge/raminit: Add XMP supportPatrick Rudolph
2016-02-19nb/intel/sandybridge/raminit: Improve loggingPatrick Rudolph
2016-02-18nb/intel/sandybridge: Start PEG link trainingPatrick Rudolph
2016-02-18southbridge/intel/bd82x6x: Use common gpio.cPatrick Rudolph
2016-02-16nb/intel/sandybridge/raminit: Add shift offsetPatrick Rudolph
2016-02-13sandybridge: Always include MRC if not using native RAM init.Vladimir Serbinenko
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
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