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2020-11-22nb/intel/sandybridge: Only use write Vref if supportedAngel Pons
Only some Ivy Bridge SKUs support write Vref control. Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Refine power-down mode logicAngel Pons
When memory is running at fast frequencies, power-down modes can lessen system stability. Check tXP and tXPDLL values and use safer power down modes if their values are high. Do not use APD with DLL-off on mobile: vendor firmware does not use it, and it can influence system stability. Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Lower tPRPDEN to 1Angel Pons
This is the default value, and matches what vendor firmware does. Change-Id: Id0c9758a845d711a87c4b06f89fa0926ae658e02 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Increase tRWDRDD with fast RAMAngel Pons
This has been reported to increase stability, and vendor BIOS also does the same. Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename and clean up `discover_edges_write`Angel Pons
This is actually an (incomplete) aggressive read training algorithm. Rename functions and variables accordingly, and tidy up declarations. Tested on Asus P8H61-M PRO, still boots. Change-Id: I8a4900f8e3acffe4e4d75a51a2588ad6b65eb411 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Relocate PREA-ACT-RD sequenceAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie5e243380d940ca89857b230e15091ac01fde928 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Remove spurious writes to IOSAV BW maskAngel Pons
The byte-wise error mask only needs to be set for certain corner cases in read MPR training. Thus, minimize writes to this register. Tested on Asus P8H61-M PRO, still boots. Change-Id: I0bb8d99ad60c4964f896d303878e5982ae1dcdbe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Drop `precharge` functionAngel Pons
This is a copy of `find_predefined_pattern` without any effect. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ieb72066ca25b40b6e60f04e6c4097a0ccc2a56b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Clarify register writeAngel Pons
It is necessary to program this register before doing an I/O reset. Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Encapsulate JEDEC write levelingAngel Pons
Create and rename a few functions to contain the entire JEDEC write leveling algorithm. Not all write training is JEDEC write leveling. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie9c6315340164029e30354723b4103d906633602 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Do not rewrite write leveling sequenceAngel Pons
There's no need to reprogram the exact same sequence over a hundred times. Move it out of the timB loop, and drop the `test_timB` function. Tested on Asus P8H61-M PRO, still boots. Change-Id: I375e325cf8b5369889b9cb059c3675cd00bdbb3f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Make helper for write leveling sequenceAngel Pons
Encapsulate the IOSAV sequence into a helper to help reduce clutter. Tested on Asus P8H61-M PRO, still boots. Change-Id: I58595a5c53fcdc3f29fa55b015a82cbfe85cd6cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Run `read_mpr_training` before write trainingAngel Pons
Reference code does this, so follow suit. Tested on Asus P8H61-M PRO, still boots. Change-Id: I21c5161da55b380dd4b2d574b22a1ef038f55fce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename `read_training` functionAngel Pons
Given that it sets the receive enable mode bit in the GDCRTRAININGMOD register, it's clear that this is about receive enable calibration. Remove a potentially-outdated comment. Proper documentation will be written once code refactoring and various improvements are complete. Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47576 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD registerAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47572 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use bitfield for GDCRCMDPICODINGAngel Pons
This register's layout makes no sense, so use bitfields for clarity. Tested on Asus P8H61-M PRO, still boots. Change-Id: I61efc7349badc2c3297c9b71535dceecaba509d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Move constants out of for-loopAngel Pons
Most per-channel registers are programmed with the same values. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ifddff3043b68113058859cef08625b90012ca424 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Use bitfields to program MCMAIN timingsAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: I9a996de5d596cdb541c8b327f119425243724007 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Clean up TC_OTHP writesAngel Pons
ODT stretch is configured for both slots in `dram_odt_stretch`. Also drop an unjustified OR, which is setting ODT stretch for one slot. Tested on Asus P8H61-M PRO, still boots. Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47490 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use one sequence for write levelingAngel Pons
In order to run a write leveling test, one needs to unset the Qoff bit in MR1, then run the test, and finally set Qoff again. The current IOSAV sequence uses two subsequences to perform the test, while the other two are unused. It is possible to perform the two necessary MR1 updates in the same sequence, which can potentially improve runtime (not measured). Since `write_mrreg` is no longer used, it is necessary to handle address mirroring explicitly. This can be accomplished with the recently-added `ddr3_mirror_mrreg` function, which is also used in `write_mrreg`. Tested on Asus P8H61-M PRO, still boots. Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47614 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21nb/intel/sandybridge: Introduce `disable_refresh_machine` functionAngel Pons
The same IOSAV sequence is used in both loops, so there's no need to reprogram it again in the second loop. Tested on Asus P8H61-M PRO, still boots. Change-Id: If7ee7917b61e4b752b4fc4700715dc9506520c03 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47612 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20nb/intel/sandybridge: Rename loop variableAngel Pons
The `discover_edges_real` function actually tests a range of values for DQS PI and evaluates how the system responds. Rename the loop variable. Change-Id: I67390ba315d618d153f91c0e8a81db04ec8f63e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47606 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20nb/intel/sandybridge: Remove unnecessary per-rank loopsAngel Pons
The IOSAV_By_BW_MASK_ch registers are not per-rank. To preserve original behavior, use a for-populated-channels loop instead of for-all-channels. Tested on Asus P8H61-M PRO, still boots. Change-Id: I6db35c41cd05420ceaeda93255f5ed73598a5bdd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Rename `discover_edges` functionsAngel Pons
These are simply read MPR training, using the MPR pattern mode in MR3. Change-Id: Icdc60572e0ee0b59dcb5dee1e1aceccfda79f029 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Restore nominal Vref for current channelAngel Pons
After aggressive read training, program nominal Vref for the current channel, not only channel 0. This simple mistake can easily degrade memory margins, especially when running at high speed (overclocking). Tested on Asus P8H61-M PRO, still boots. Change-Id: I12630fe33c5c786c8ec131c45c27180c3887d354 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-20nb/intel/sandybridge: Rename `timC_discovery` and relatedAngel Pons
This function simply determines the best delay for the TX DQ PIs. Change-Id: If44c4f661d8c81fe41532ce2bfe3718392b9fe94 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Introduce `ddr3_mirror_mrreg` helperAngel Pons
Write training needs to update mode register 1, but `write_mrreg` will clobber the IOSAV sequence. Reference code uses one four-subsequence to unset Qoff in MR1, run the test, and finally set Qoff again. This will be implemented in future changes, and will use the newly-added helper. Change-Id: I06a06a7bdd43dbde34af4ea2f90e00873eefe599 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Replace and-zero with assignmentAngel Pons
The intent here is to clear the register, so a simple write will work. Change-Id: I547805059e911942ac2cac7bd2165af23d926a2b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Introduce `find_predefined_pattern` functionAngel Pons
Also fuse two per-channel loops together. Tested on Asus P8H61-M PRO, still boots. Change-Id: Iacc66f4364290a66d60d483055abef6e98223d16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Rename receive enable functionsAngel Pons
Give these functions more meaningful names. Change-Id: I6b308120d4185a3bc448213a925d5cee0d4d8bd9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Rework timA minmax codeAngel Pons
There's no need to use `struct timA_minmax`, since most cases only care about the difference between logic delay deltas. The final step does use the minimum logic delay across all lanes, but it's a special case. Tested on Asus P8H61-M PRO, still boots. Change-Id: I1da95520ac915ab003e1a839685cbf5f1970eb6a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Correct some whitespace issuesAngel Pons
Add a missing tab and remove spurious spaces in the IOSAV structs. Change-Id: If588d3f01c8744fd0c83576a56cfdda2fb43a3bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47570 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19nb/intel/sandybridge: Clean up `dram_mr2` functionAngel Pons
Constify variables, and also remove pointless and-masks on mr2reg. Tested on Asus P8H61-M PRO, still boots. Change-Id: I3829012ff7d41f4308ee84d6fbf3b1f2803431af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAMAngel Pons
Reference code never enables SRT for Sandy Bridge, and only enables it for Ivy Bridge when the memory frequency is at most 1066 MHz. Tested on Asus P8H61-M PRO, still boots. Change-Id: I50527f311340584cf8290de2114ec2694cca3a83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Program MR2 shadow registerAngel Pons
This register must be programmed if Self-Refresh Temperature range is enabled in MR2 (bit 7). Because the memory controller needs to reprogram MR2 when entering Self-Refresh, it needs a copy of the MR2 settings. It also needs to know about mirrored ranks to correctly issue MRS commands. Tested on Asus P8H61-M PRO, still boots. Change-Id: I2e459ac7907ead75826c7d2ded42328286eb9377 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Drop unused `rank` parameterAngel Pons
Change-Id: I5476bbe1a99d087bc026dc5646c8440c50dd151e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47518 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19nb/intel/sandybridge: Relocate `get_ODT` functionAngel Pons
This function is only used in two places, so move its definition closer. Change-Id: I21d3e04de45f58cef0603b6b75119cae4b1a7aae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-19nb/intel/sandybridge: Clean up MR0 compositionAngel Pons
There's no need to use and-masks here. Tested on Asus P8H61-M PRO, still boots. Change-Id: If06352daf53ce278dfc64102e023e4f1ea78385c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Rewrite magic numbersAngel Pons
Use bitwise negations for AND-masks and shifts for bitfields. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: Id265728c362a5035ac57f84766e883608f29c398 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47511 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19nb/intel/sandybridge: Remove now-unnecessary sequence macrosAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8H61-M PRO remains identical. Change-Id: I7980daf316cfd524d24df2c10e43b9b15e4e30bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Create sequence helpersAngel Pons
Create some functions to program commonly-used sequences. Tested on Asus P8H61-M PRO, still boots. Change-Id: I1b6474ab208fe5fc2bd7f1b68eff20541fdfce9b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Extract some IOSAV sequences into macrosAngel Pons
This allows deduplicating them while preserving reproducibility. Tested with BUILD_TIMELESS=1, Asus P8H61-M PRO remains identical. Change-Id: Ic7d1a5732296bb678b9954f80508e9f7de7ff319 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Use arrays to program IOSAVAngel Pons
Instead of programming subsequences one-by-one, we might as well take the whole sequence as an array and program all subsequences in one go. Since the number of subsequences is now known in advance, handling of global state can be simplified, which allows reusing the last sequence. Change-Id: Ica1b2b20e04ae368f10aa236ca24d12f69464430 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Move IOSAV functions to separate fileAngel Pons
Change-Id: Icbe01ec98995c3aea97bb0f4f84a938b26896fab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16nb/intel/sandybridge: Clarify some parts of raminitAngel Pons
Put names and expand comments for some parts of the code. Change-Id: If1f83bf113ef08469768a9e4dd13819f76633f18 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-11-16nb/intel/sandybridge: Fix typo in commentAngel Pons
Change-Id: I8271911695f41ef7cac1bb228309af0568e5bb0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16nb/intel/sandybridge: Retype constantAngel Pons
There's no need to use size_t to store a boolean. Change-Id: I0069fa8d75583dc34b402004d753220943406a04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16nb/intel/sandybridge: Drop write_controller_mr() functionAngel Pons
The only reason to write the MR values to the training result registers is for EV (Electrical Validation) usage. The hardware doesn't need it. Tested on Asus P8H61-M PRO, still boots. Change-Id: I808174494729453f4ebcaa13258d735faae68d72 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-16nb/intel/sandybridge: Reduce the scope of get_CWL()Angel Pons
It is only used once, and can thus be moved to the same file. Change-Id: I4ee0621449da7fa1970a475d5a2f6e66546357ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16nb/intel/sandybridge: Clarify IOSAV_DATA_CTL_ch usageAngel Pons
It is usually written to right after programming a pattern, because its lower byte contains the number of cachelines of the programmed pattern. The other cases merely reset the WDB data write and compare pointers. Change-Id: I97196d404bf70542db28499e0d2e24b7cdab07b6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-13mrc_cache: Move code for triggering memory training into mrc_cacheShelley Chen
Currently the decision of whether or not to use mrc_cache in recovery mode is made within the individual platforms' drivers (ie: fsp2.0, fsp1.1, etc.). As this is not platform specific, but uses common vboot infrastructure, the code can be unified and moved into mrc_cache. The conditions are as follows: 1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain switch is true) 2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this means that memory training will occur after verified boot, meaning that mrc_cache will be filled with data from executing RW code. So in this case, we never want to use the training data in the mrc_cache for recovery mode. 3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens before verfied boot, meaning that the mrc_cache data is generated by RO code, so it is safe to use for a recovery boot. 4. Any platform that does not use vboot should be unaffected. Additionally, we have removed the MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the mrc_cache driver takes care of invalidating the mrc_cache data for normal mode. If the platform: 1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data 2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set BUG=b:150502246 BRANCH=None TEST=1. run dut-control power_state:rec_force_mrc twice on lazor ensure that memory retraining happens both times run dut-control power_state:rec twice on lazor ensure that memory retraining happens only first time 2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig boot twice to ensure caching of memory training occurred on each boot. Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23nb/intel/sandybridge: Correct designation of MRC versionAngel Pons
Do not use `System Agent version` to refer to the MRC version, which is what the register being printed contains under normal circumstances. Change-Id: I8679bae37b8ccb76e9e9fc56fc05c399f6030b29 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-13nb/intel/sandybridge: Improve cbmem_top_chipset calculationAngel Pons
Lock bit in TSEGMB register wasn't accounted for in `cbmem_top_chipset`. Align down TSEG base to 1 MiB granularity to avoid surprises. Change-Id: I74882db99502ae77c94d43d850533a4f76da2773 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-21src/northbridge: Drop unneeded empty linesElyes HAOUAS
Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/sandybridge: Check ME status only onceAngel Pons
The pre-RAM CBMEM console is tiny. Do not fill it with largely redundant information, when we could instead store more useful raminit debug logs. Change-Id: I3a93fdeb67b0557e876f78b12241b70933ad324d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21nb/intel/sandybridge: Simplify SPD validity checkAngel Pons
Instead of decoding the entire SPD, just check the memory type directly. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I3afa0ca5aae984895e50fe7b3792192fdd2ee6c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21nb/intel/sandybridge: Drop unnecessary `gma.h`Angel Pons
It only contains prototypes for the long-gone native graphics init. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I9413abb8e49496ada60dcdf801a1f8a03be38d2e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45360 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/sandybridge: Put DMIBAR/EPBAR registers into separate filesAngel Pons
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I836df4675f4886635973c0c75f5981c9ef17d84b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45359 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/sandybridge: Move register headers into a subfolderAngel Pons
Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: Ie525e755f32599db97af7969fc7fbb36a5d826b6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45358 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/sandybridge: Clean up DMIBAR/EPBAR registersAngel Pons
Several registers have been copy-pasted from i945 and do not exist on Sandy Bridge. Moreover, other register definitions were missing. Use the newly-added definitions in existing code, in place of numerical offsets. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I9ad849f57bc68256a2a87ffdc856c4b521e35892 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45357 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/sandybridge: Introduce memmap.hAngel Pons
Move all memory map definitions into a separate header. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I7f2ff2a5cee8bf12e5dca74ff9f0b1a44e26cded Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45356 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/sandybridge: Drop `void *` cast in `MCHBAR32`Angel Pons
This changes the binary for the native raminit code path. Tested on Asus P8Z77-V LX2, still boots with native raminit. Change-Id: Ie8f1205a64e5264cb909d67c1dd402c18a6241ad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45350 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
This allows us to drop some casts to uintptr_t around the tree. The MCHBAR32 macro still needs a cast to preserve reproducibility. Only the native raminit path needs the cast, the MRC path does not. Tested with BUILD_TIMELESS=1, these boards remain identical: - Lenovo ThinkPad X230 - Dell OptiPlex 9010 - Roda RW11 (with MRC raminit) Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macroAngel Pons
RCBA is located in the PCH. Replace all instances with the already-defined `DEFAULT_RCBA` macro, which is equivalent. Change-Id: I4b92737820b126d32da09b69e09675464aa22e31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45348 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`Angel Pons
All boards currently have backlight on either LVDS or eDP. Change-Id: I878bc7f1ff75a2b82b9556e855aff1d4d03e0268 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-31nb/intel/sandybridge: Add ECC error injection register informationAngel Pons
Change-Id: I669a611e804d67bb6e87775d273dc24b03b06691 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44396 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen
Create two new functions to fetch mrc_cache data (replacing mrc_cache_get_current): - mrc_cache_load_current: fetches the mrc_cache data and drops it into the given buffer. This is useful for ARM platforms where the mmap operation is very expensive. - mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a given buffer. This is useful for platforms where the mmap operation is a no-op (like x86 platforms). As the name mentions, we are not freeing the memory that we allocated with the mmap, so it is the caller's responsibility to do so. Additionally, we are replacing mrc_cache_latest with mrc_cache_get_latest_slot_info, which does not check the validity of the data when retrieving the current mrc_cache slot. This allows the caller some flexibility in deciding where they want the mrc_cache data stored (either in an mmaped region or at a given address). BUG=b:150502246 BRANCH=None TEST=Testing on a nami (x86) device: reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12nb/intel/sandybridge: Add comments to `struct iosav_ssq`Angel Pons
Add the ranges of bitfields as comments on the struct. Change-Id: Ib20a233806bfbdc9a81a77f4ef10f67a3cd2dc0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner
2020-08-11nb/intel/sandybridge/raminit: Add commentsPatrick Rudolph
Add comments found when testing ECC scrubbing code. This is a cosmetic change. Change-Id: I7975f6070c2002930eec407a6b101a1295495b25 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40947 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11nb/intel/sandybridge/raminit: Fix ECC scrubPatrick Rudolph
The scrubbing method was never correct nor tested. Fix that by observations made on mrc.bin. Tested on HP Z220 with ECC memory and Xeon E3 CPU: The whole memory is now scrubbed. Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40721 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11nb/intel/sandybridge/raminit: Add ECC debug codePatrick Rudolph
* Add ECC test code when DEBUG_RAM_SETUP is enabled * Move ECC scrubbing after set_scrambling_seed() to be able to observe what has been cleared in the test routine. If clearing happens before set_scrambling_seed the data is XORed with a different PRN. Data read from memory will look random instead of all zeros. * ECC scrubbing must happen after dram_dimm_set_mapping() The ECC logic is set to "normal mode" in dram_dimm_set_mapping(). In normal mode the ECC bits are calculated and stored on write transactions. * Move method out of try_init_dram_ddr3(). This satisfies point 2 and point 3 of the list above. Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-06nb/intel/sandybridge: Drop inexistent device from DMARAngel Pons
There's no `function 1` on the iGPU device for this northbridge. Change-Id: I597446f703165447c3a0d0c1536583b08bc8450c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-06nb/intel/sandybridge: Deduplicate PCIEXBAR decodingAngel Pons
We can use `decode_pcie_bar` instead, as other northbridges do. Change-Id: I35bede573ef2635c54123f9e553003577ecd0ea7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-06nb/intel/sandybridge: Refactor `get_pcie_bar`Angel Pons
Turn it into `decode_pcie_bar`, taken from gm45. Change-Id: Id1c2cfbcac1a798d046beced790930511dc97972 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44121 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDsAngel Pons
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I1f84cae41c6281e0d545669f1e7de5cab0d9f9c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-04nb/intel/sandybridge: Update to ASL 2.0 syntaxAngel Pons
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: Ie3570cd0a75c6b34581b35165c1c6393214ad0bb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-30nb/intel/*: Fill in SMBIOS type 16 on SNB/HSWPatrick Rudolph
Fill in the maximum DRAM capacity and slot count read from CAPID0_A registers on Sandy Bridge and Haswell. While the register isn't part of the Core Series datasheet, it can be found in the corresponding "Intel Open Source Graphics Programmer's Reference" datasheets. Note that the values for DDRSZ (maximum allowed memory size per channel) need to be halved when only one DIMM per channel is supported. On mobile platforms, all but quad-core processors are subject to this restriction. Tested on Lenovo X230: On Linux, verify that `dmidecode -t 16` reports the actual maximum capacity (16 GiB) instead of the currently-installed capacity (4 GiB) or the max capacity assuming two DIMMs per channel is possible (32 GiB). Change-Id: I6e2346de1ffe52e8685276acbdbf25755f4cc162 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26nb/intel/sandybridge: Add missing includesElyes HAOUAS
Change-Id: I9d54d0923a595734a84256ddcafb9dae17615cb0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43348 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24nb/intel/sandybridge: Put host bridge registers into its own fileAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: Ibfaecd6ab94d2caae9804bb827ce8e48a2166d35 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-24nb/intel/sandybridge: Remove unnecessary `struct sys_info`Angel Pons
It was only used in one function, but its value was never read. Drop it. Change-Id: Ib511352d51d4452d666640d0f52810b06c8d61ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-20sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons
Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <types.h>'Elyes HAOUAS
Files found using: diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22nb/intel/sandybridge/gma.c: Remove useless if conditionEvgeny Zinoviev
There's a useless check with both branches doing the same: enabling RC6 and disabling RC6p. In past, this condition would enable RC6p in IVB but not on SNB. Then, at some point, RC6p was considered unstable and was disabled, but the condition remained. It's not needed so let's remove it. Change-Id: I926bb682d1b9d21185048224490b966c33204b6a Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22device/smbus_host: Declare common early SMBus prototypesKyösti Mälkki
Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-09nb/intel/sandybridge: Use MCHBAR bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: If16d8c4aef3dfd1dbeaf48d6855dd4c0ef328168 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-09nb/intel/sandybridge: Use PCI bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-06src: Use pci_dev_ops_pci where applicableAngel Pons
Change-Id: Ie004a94a49fc8f53c370412bee1c3e7eacbf8beb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-03northbridge/intel/sandybridge: Mask lower 20 bits of TOLUD and TOLM in ↵Furquan Shaikh
hostbridge.asl Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: Ib0ffd9a332fa9590de63f8828d30daa710fe50db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-03northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntaxFurquan Shaikh
This change updates hostbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for google/link. Change-Id: I5345ee22df7da92ee48c718f5bd748d7ea6155f2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-02src: Remove unused 'include <bootmode.h>'Elyes HAOUAS
Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41670 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27intel/gma: Only enable bus mastering if we are going to use itNico Huber
Also fix wrong 32-bit writes. Change-Id: Ib038f0cd558223536da08ba2264774db11cd8357 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40727 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27intel/gma: Don't bluntly enable I/ONico Huber
The allocator should take care of this. Change-Id: I4ec88ebe23b4dcab069f764decc8b9b0c6e6a142 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40726 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27drivers/intel/gma: Move IGD OpRegion to CBMEMNico Huber
It never was in GNVS, it never belonged among the ACPI tables. Having it in CBMEM, makes it easy to look the location up on resume, and saves us additional boilerplate. TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and intel_backlight + acpi_video synchronize, both before and after suspend. Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21nb/intel/sandybridge: Use the new IOSAV struct APIAngel Pons
Now that we have created the IOSAV API, we can put it to good use. Drop all the helper macros and replace them with struct constructs. Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged. Change-Id: Ib366e364df11c9bb240cdfbce418540ec715c634 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41003 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21nb/intel/sandybridge: Drop unused parametersAngel Pons
We now use a static variable to handle the sequence length. Tested on Asus P8Z77-V LX2, still boots. Change-Id: Id3115c14336ea128264bd3945a99c52b9796d115 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-21nb/intel/sandybridge: Redefine IOSAV_SUBSEQUENCEAngel Pons
Instead of directly writing values to the IOSAV registers, use a struct and some helper functions to provide a cleaner interface for the IOSAV. Having IOSAV_SUBSEQUENCE refer to a static function is weird, but we will remove this macro in a follow-up that does not change the binary. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I73f13c18a739c5586a7415966f9017c2335fdfd1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-21nb/intel/sandybridge: Truncate IOSAV subseq gapsAngel Pons
We set bit 15 of IOSAV_n_SUBSEQ_CTRL three times, but it is reserved. Since this bitfield is five bits wide, manually truncate the values so that bit 15 does not get set. Tested on Asus P8Z77-V LX2, still boots. Change-Id: Ib61b026b016b0d22e164f8817158ec5093f6bb9e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-21nb/intel/sandybridge: Replace macros with functionsAngel Pons
Turn `iosav_run_queue` and `iosav_run_once` into functions. Inlining them does not have any effect, as the resulting binary is identical. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I7844814eeedad9b1d24f833a77c90902fa926bfe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-20 04:28:54 +0000