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2019-01-13{mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()Elyes HAOUAS
Use hexdump() instead of dump_mem(). Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-09cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans
The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-06usbdebug: Make the EHCI debug console work in the bootblockArthur Heymans
Currently this needlessly initializes the hardware in the both the romstage and the bootblock, but it works. Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the use better, related support files can be built to pre-ram stages regardless of usbdebug being enabled or not. Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK). Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-06usbdebug: Refactor init callsKyösti Mälkki
Expose the function that can unconditionally re-initialise EHCI debug host and gadget. Given the missing header in soc/intel files that prevented building with USBDEBUG_IN_ROMSTAGE=y, it is not actually known if those SOCs work at all for usbdebug. Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-06device: Use pcidev_path_on_root()Kyösti Mälkki
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-19northbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ie221a142ed804988a05269d42904aba3ac79e0be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-13cpuid: Add helper function for cpuid(1) functionsSubrata Banik
This patch introduces 3 helper function for cpuid(1) : 1. cpu_get_cpuid() -> to get processor id (from cpuid.eax) 2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx) 3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx) Above 3 helper functions are targeted to replace majority of cpuid(1) references. Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29302 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-28src/*: normalize Google copyright headersPatrick Georgi
As per internal discussion, there's no "ChromiumOS Authors" that's meaningful outside the Chromium OS project, so change everything to the contemporary "Google LLC." While at it, also ensure consistency in the LLC variants (exactly one trailing period). "Google Inc" does not need to be touched, so leave them alone. Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-25northbridge: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
Change-Id: Ib70eb33fac654a773ea39a5fd4206435dffdabb7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-14nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resumeNico Huber
Change-Id: Icac6e696efa1721933a1963b45d608d9ae735149 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/28589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
2018-08-22nb/intel/*/gma.c: Skip NGI when VGA decode is not enabledArthur Heymans
Writes to VGA MEM and IO by NGI are invalid if the IGD is not decoding them. Change-Id: I4b9329d14105eb563a0d4aea6ef75ff11febf6df Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.cPatrick Rudolph
There's nothing Sandy Bridge specific in this code. Make it available on all platforms to reduce code duplication. Tested on Lenovo T430: SMBIOS entry 17 is still valid. Change-Id: I051c3e07a999d8dad082c24f65b43dce180349fd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20nb/intel/raminit: Remove unused headersPatrick Rudolph
Change-Id: Ic6e7341b53bcabc415089ccfab121d3694ccb071 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-08-20nb/intel/sandybridge/raminit: Fix DIMM type mappingPatrick Rudolph
The DIMM type read from SPD needs to be converted to make sure SMBIOS fills in the correct formfactor. Tested on Lenovo T430: The Form Factor no longer reads as unknown. Change-Id: Ia0211fa133f4ba9d60dfbd5f0dd45a43df68c030 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20nb/intel/sandybridge: Fill in DIMM serial numberPatrick Rudolph
Fill in SMBIOS type 17 DIMM serial number, read from SPD. Fixes FWTS SMBIOS type 17 test. Change-Id: Id6e818bfdf4af0fd34af56dc23df052a3f8c348d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-17sandybridge/raminit_common.c: fix printram statementIru Cai
Change-Id: Iddea8cc71dc1fb33d46b22dd19e39bf1c1257555 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/28117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-03sandybridge/raminit_mrc: remove reference to report_platform_info()Matt DeVillier
Commit ef8c559e537ed10d8054ca6a72ca50e0531fde95 [nb/intel/sandybridge/report_platform: Move remaining code to sb folder] moved reporting code to the southbridge, but missed a reference in the non-default MRC raminit path (so testing missed it). Remove invalid reference to fix compilation error. Test: build google/link with MRC raminit option selected Change-Id: I270a95ac53fbc9f8792f375908cf91585261f6a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining placesFelix Held
Change-Id: I1c81eb7c8ed0b819bb76196208cc1269180aca55 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-01sandybridge/raminit_common: use macro for execute command queue registerFelix Held
This patch doesn't change the hash of a timeless build. Change-Id: I5d329f65be0eee741fd330c0926881ff4f956624 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-01sandybridge/raminit_common: use FOR_ALL_CHANNELS macroFelix Held
Change-Id: I01bd69605760e8a03787dcfa3da9f47576e3144a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
This patch contains the parts that changed the hash of the generated binary; probably due to the compiler optimizing things slightly different. Change-Id: Ide0b3296864e24edb646956e47221bfef8182e3d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27725 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
When using timeless builds and coreboot crossgcc 6.3.0, the checksum of the resulting binary doesn't change with applying this commit. Change-Id: I2b1dc8befa3381f3edac06704e31e7ef50f86fa4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27724 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01northbridge/sandybridge: add MCHBAR32 AND/OR/AND_OR access macrosFelix Held
Change-Id: I5d91674ebd281a595e7c0462671f4715ca09cb5c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27723 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01nb/intel/sandybridge: Don't use PCI operations on the pci_domain deviceArthur Heymans
pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27244 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-29sandybridge/raminit_common: use MCHBAR32 macro everywhereFelix Held
Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29sandybridge/raminit: use MCHBAR32 macro everywhereFelix Held
Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-29sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held
Change-Id: If8b8fd123e0dd15a0fc9dfe178076f8541e29d56 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29nb/intel/sandybridge: Bump MRC_CACHE_VERSIONPatrick Rudolph
Commit 74203de "intel/sandybridge: Don't hardcode platform type" changed the MRC layout. Bump the version to prevent a boot error, if the cache isn't cleared on flashing a new coreboot version. Change-Id: Icd6f31bf0b30a42c66e18ab83d2434f9c3084211 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27712 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph
Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph
Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
* Add a function to return CPU platform ID bits * Add a function to return platform type ** Platform id is 4 on Lenovo T430 (mobile) ** Platform id is 1 on HP8200 (desktop) * Use introduced method to handle platform specific code * Use enum for platform type * Report platform ID Change-Id: Ifbfc64c8cec98782d6efc987a4d4d5aeab1402ba Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-26nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus widthPatrick Rudolph
The bus width has to be encoded where the lower 3 bits are the bus width in multiple of 8 and the following two bits give the error checking bits in multiple of 8. Hardcode to 64 bit as done on haswell. TODO: Make it dynamic once there's ECC support. Change-Id: I3b83a098205455b1c820d0436c6984938f261466 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-26nb/intel/sandybridge/raminit: Fix PDWN_mode on desktopsPatrick Rudolph
On desktop boards the PPD bit of MRS register MR0 is set and thus DLL_Off mode shouldn't be used, as enforced by datasheet 2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.17.1. Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25nb/intel/sandybridge/raminit: Fix non ASCII charPatrick Rudolph
Change-Id: I3f0869dc0b72bef7da8313c69da4fe2a63761ad9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27633 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25nb/intel/sandybridge/raminit: Set REFIx9 according to specPatrick Rudolph
Set tREFIx9 to 8.9*tREFI/1024 as suggested in xeon-e3-1200v3-vol-2-datasheet.pdf chapter 4.2.15 or 2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1. Use the minimum value of REFI*8.9 and tRASmax as suggested by 3rd-gen-core-desktop-vol-2-datasheet.pdf chapter 2.13.9. Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-02src/nb: Fix non-local header treated as localElyes HAOUAS
Change-Id: I8174d7b40008cfe4fba10fde4670682aac0ad078 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-30arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier
Add DMAR RMRR table entry and helper functions, using the existing DRHD functions as a model. As the DRHD device scope (DS) functions aren't DRHD-specific, genericize them to be used with RMRR tables as well. Correct DRHD bar size to match table entry in creator function, as noted in comments from patchset below. Adapted from/supersedes https://review.coreboot.org/25445 Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27269 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-05cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans
Tested on Lenovo Thinkpad X220 with both native raminit and mrc.bin. Change-Id: I5e1a1175d79af4dc079a5a08a464eef08de0bcbf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04nb/intel: Use postcar_frame_add_romcache()Nico Huber
Change-Id: I0729ca4cdad7d2218c1e1feae5cd38dda6d4e11e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-29src/northbridge: Add and update license headersMartin Roth
This change adds and updates headers in all of the northbridge files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all northbridge directories. Change-Id: I8cd7c04ddb8e58946dcdf9c7c125e23698647a73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-24nb/intel/sandybridge: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If36a879fbe7a93a214d74dbfa6fb3ee2d09a044a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30nb/intel/sandybridge: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I585aa48b99f4ef63905cab5d6d1502bfed0e6e42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16nb/intel/sandybridge: support more XMP timingsDan Elkouby
Tested with a pair of GSkill F3-1866C9-8GSR. This makes sure in particular that we honor the CMD rate requested by the XMP profile. This memory kit needs a CMD rate of 2 to be stable at DDR3-1600 and up, even though it passes training at 1. Also respect requested CWL to match vendor firmware and for a potential increase in performance. The tested kit requests a tighter value than the per-frequency table provides and has shown to be stable using that setting. Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/25664 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13nb/intel/sandybridge/peg: Add PEG driver stubPatrick Rudolph
Required for other ACPI generators, like the one used for _ROM. * Add ACPI code for PEG10/PEG11/PEG12/PEG60 and include it on all platforms. * Add PCIe driver for PEG. The driver returns ACPI names for ssdt generators. Needs test on real hardware. Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22337 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11Revert "model_206ax: Use parallel MP init"Arthur Heymans
This reverts commit 5fbe788bae15f0d24d56011e8eb8b48c107b7b05. This commit was submitted without its parent being submitted, resulting in coreboot not building. Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-11model_206ax: Use parallel MP initArthur Heymans
This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves of ~30ms on a 2 core, 4 threads CPU. Change-Id: Iacd7bfedfccbc09057e1b7ca3bd03d44a888871d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23432 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10cpu/intel/sandybridge: Put stage cache into TSEGArthur Heymans
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. The code is mostly copied from src/cpu/intel/haswell. TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used. Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
Many generations of Intel hardware have identical code concerning the RCBA. Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-06nb/intel/sandybridge: Always use the same MMCONF_BASE_ADDRESSArthur Heymans
'Optimizing' MMCONF_BASE_ADDRESS for the native codepath prevents the use of fallback/normal with both the native raminit and the mrc.bin. Using the same MMCONF_BASE_ADDRESS as the mrc.bin codepath means that 128MB less is available to devices using the native raminit. Most devices reserve 2048M for non memory resources below 4G, which in most cases is more than adequate. Devices with only 1024M (and that don't already use the mrc.bin) are: * lenovo/x220 * lenovo/x230 * lenovo/x131e * lenovo/x1_carbon_gen1 Those could fail to allocate PCI resources, but on at least x220 with a somewhat default configuration (USB3 expresscard, Wireless PCIe card) it still boots fine, so one should not expect many problems from this change. Change-Id: I1d0648fe36c88bd9279ac19e5c710055327599fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-02nb/intel/sandybridge: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I6dfef118dc2fecf2a8f2f3401c779a3becfb71a9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-01-31nb/intel/*.h: Remove left-over register definitionsPatrick Rudolph
The code has been moved into drivers folder. Change-Id: I122affffd5108052ed7a95b34d0d66a6d3279d41 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/23487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-26nb/intel/sandybridge: Use common mrc cache functionsArthur Heymans
This uses the functions in include/mrc_cache.h instead of northbidge/intel/common/mrc_cache.h Tested working on Lenovo Thinkpad x220, mrc_cache region gets written and S3 resume still works fine. Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23sb/intel/bd82x6x: Reduce function-disable messNico Huber
Most affected boards set the function disabled (FD) register to an arbitrary state dumped from systems running the vendor BIOS. This makes it impossible to enable the devices in devicetree and a pretty big mess of course because nobody cared to keep the register in sync with the devicetree. To get completely rid of most of the writes to FD, move setting of PCH_DISABLE_ALWAYS into the southbridge code where it belongs. Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-20intel/gma: fix RPNFREQ_VAL bitmaskFelix Held
gma.c of Nehalem was copied from Sandy/Ivy Bridge, so fix it there too. Tested on lenovo/x230. Since both the bit that was masked wrongly and the one that wasn't masked, but sould have been, are 0, the behaviour on lenovo/x230 doesn't change. Change-Id: I5f51c4929df83f948fcb7dc06e07ac3cc4ccf4f2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/22596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-283rdparty/lib{hwbase,gfxinit}: Update to latest masterNico Huber
Simplifies our C interface function gma_gfxinit(), due to the following changes: * *libgfxinit* knows about the underlying PCI device now and can probe MMIO addresses by itself. * The framebuffer mapping is now completely handled inside the library where we validate that we neither overflow - the stolen memory, - the GTT address space, the GTT itself nor - the aperture window (i.e. resource2 of the PCI device) that we use to access the framebuffer. Other changes: * Fixes and a quirk for DP training. * Fix for DP-VGA adapters that report an analog display in EDID. * Fixes for Skylake support with coreboot. * DDI Buffer drive-strength configuration for Haswell, Broadwell and Skylake. * `gfx_test` can now be run from X windows (with glitches). * Compatibility with GCC 7 and SPARK GPL 2017. TEST=Booted lenovo/t420 and verified that everything works as usual. Change-Id: I001ba973d864811503410579fd7ad55ab8612759 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28drivers/intel/gma: Put gma_gfxinit() into its own headerNico Huber
The current header `i915.h` is too invasive to be used everywhere where we want to use *libgfxinit*. Change-Id: Iba57256d536e301e598d98182448d2daa1bf9a89 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19nb/sandybridge: Add a kconfig option to ignore XMP max DIMMsVagiz Trakhanov
XMP profiles can have a restriction on max supported DIMMs per channel, but many configurations work with more DIMMs. This is relevant on mainboards with 2 DIMM slots per channel (usually 4 in total). Populating both slots with DIMMs that support XMP profiles only with 1 DIMM per channel turns off said XMP profiles. TEST=On a system with two DIMM slots per channel populate both slots on one channel and ensure that DIMMs run with XMP profiles enabled. Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3 Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-16sandybridge/acpi: remove unnessary check of PCI IDsVagiz Trakhanov
DRAM Controller is always 00.0. No need to check its PCI ID. Change-Id: I9c5f3e5658905e464491579f8da01aa6a03bd3b7 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-16nb/intel: Add Ivy Bridge Server (Xeon-E3v2) PCI IDsVagiz Trakhanov
Change-Id: I1899dbe9498a0cc83b65b4bc1c6c0a555637fd05 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-12nb/intel/sandybridge/raminit: Fix setting scramble seed for CH1Arthur Heymans
The scramble seed intended for CH1 were written to the regs of CH0. Write the scramble seed for CH1 at the correct offset. TESTED on Lenovo T430, HP 2760P, Asrock B75PRO3-M. Change-Id: I3778947e96b3298c38e6d5b74988e617e1ffea7b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Iru Cai <mytbk920423@gmail.com>
2017-10-03nb/intel/sandybridge: Refactor dram_dimm_mapping()Nico Huber
Remove no-op statements and code-rephrasing comments, apply some cosmetic changes to improve readability. Change-Id: I124a6bc338c2589fab66ca91bf53139b4413d10b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-27nb/intel/sandybridge/raminit: Improve readabilityPatrick Rudolph
Add debug messages for SPD probing. Change-Id: I722102b7981781b88cdc4877f698294eb719ff32 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-14nb/intel/sandybridge/gma: Fix S3 resumePatrick Rudolph
The S3 resume path is broken on current Linux (4.11.3) and maybe on older kernel, too. Don't run the native graphics init when on S3 resume to fix it. Tested on Lenovo T430. Change-Id: Ifad145c86c2e8f019c507f97c889b70b7aa49882 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-11drivers/intel/gma/opregion: migrate from nb/commonMatt DeVillier
Migrate opregion code from northbridge/intel/common to drivers/intel/gma in preparation for consolidation with soc/intel/common opregion code. Rename init_igd_opregion() for clarity and disambiguation with other implementations. Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-08-10nb/intel/sandybridge/raminit: Add Kconfig option for fusesPatrick Rudolph
Add a new Kconfig option to ignore memory fuses that limit the maximum DRAM frequency to be used. The option is disabled by default and should only enabled by experienced users as it might decrease system stability or prevent a successful RAM training. Remove conflicting devicetree settings. Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nicola Corna <nicola@corna.info>
2017-08-07nb/intel/*/gma.c: Use macros for GMBUS numbersArthur Heymans
Change-Id: I885b6bd9f5be6b4e3696a530016123a3e81c4b10 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-06sb/intel/*: Use common SMBus functionsArthur Heymans
All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-30intel/sandybridge: Clean VGA BIOS ids up a littleNico Huber
Sync map_oprom_vendev() and autoport with the list of PCI ids in the `gma.c` driver, remove one obsolete Kconfig default override. Change-Id: I12f24f415b695c516fbb947114e09c873af2e439 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-30intel/sandybridge: Gather MMCONF_BASE_ADDRESS defaultsNico Huber
All affected boards did the same USE_NATIVE_RAMINIT distinction or actually selected USE_NATIVE_RAMINIT. Also update autoport. Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20813 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12nb/intel/sandybridge/gma: Set ASLS on S3 resumePatrick Rudolph
Use new GMA driver method to set ASLS on S3 resume, too. Move gma_enable_swsci to init method as it should always be run. Change-Id: Ic7132cd1848a75043d10f32ac5d0e6b45d2e0fe4 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12drv/intel/gma/opregion: Add interface for GNVS ASLB handlingPatrick Rudolph
Add and use new interface to set and get GNVS' ASLB register. To be used by Intel's gma driver to set ASLB at ACPI table creation and to get ASLB on S3 resume. Change-Id: If30c6b2270069783b0892774802f47406404da5f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-27nb/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-27nb/intel/sandybridge: Fill in acpi_namePatrick Rudolph
Fill in acpi_name to return proper ACPI names. To be used with SSDT generators. The ACPI names have to match those already used in ASL code. By providing the ACPI name it can be retrieved by the acpi_device_name() method and doesn't need to be hardcoded in SSDT generators any more. GFX0 is used in drivers/intel/gma/acpi/pch.asl. MCHC is used in nb/intel/sandybridge/acpi/hostbridge.asl. Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-22nb/intel/sandybridge/raminit: Fix dual DIMM command ratePatrick Rudolph
On boards that are able to take two DIMMs per channel the command rate should be 2T. It is possible to use 1T with load reduced "1T" DIMMs, but it's not clear how to detect those DIMMs. Raminit might fail for those who do not have such DIMMS installed. Hardcode command rate of 2T to make sure raminit works on dual DIMM per channel boards (currently only desktop boards). The command rate of 1T is still tested if only 1 DIMM per channel is present. Will decrease performance on quad slot mainboards, if two DIMMs are installed in one channel and previously 1T have been selected. Tested on ASRock B75 Pro3-M. Change-Id: I029d01092fd0e11390cebcd94ca6f23bf0ee2cab Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-15nb/intel/sandybridge/gma: Use common init_igd_opregion methodPatrick Rudolph
Use common init_igd_opregion method. Change-Id: Ia10a28d05b611a59f787b53f9736b3b76a19ea4a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-12nb/intel/ivybridge: Improve CAS freq selectionArthur Heymans
The previous code seemed weird and tried to check if its selected value is supported three times. This also lower the clock if a selected frequency does not result in a supported CAS number. Change-Id: I1df20a0a723dc515686a766ad1b0567d815f6e89 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-06-12nb/intel/sandybridge: Improve CAS freq selectionArthur Heymans
The previous code seemed weird and tried to check if its selected value is supported three times. This also lower the clock if a selected frequency does not result in a supported CAS number. Change-Id: I97244bc3940813c5a5fcbd770d71cca76d21fcae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-06-09cpu/intel/model_206ax: Use tsc monotonic timerPatrick Rudolph
Switch from lapic to tsc. Allows timestamps to be used in coreboot, as there's a reference clock available to calculate correct time units. Clean Kconfig, remove duplicated lapic code and include tsc dir for LGA1155 boards. Tested on Lenovo T430. Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08device/Kconfig: Put gfx init methods into a `choice`Nico Huber
Provide all gfx init methods as a Kconfig `choice`. This elimates the option to select native gfx init along with running a Video BIOS. It's been only theoretically useful in one corner case: Hybrid graphics where only one controller is supported by native gfx init. Though I suppose in that case it's fair to assume that one would use SeaBIOS to run the VBIOS. For the case that we want the payload to initialize graphics or no pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the choice. If multiple options are available, the default is chosen as follows: * NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS, * VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS, * NATIVE_VGA_INIT, if we don't add a Video BIOS. As a side effect, libgfxinit is now an independent choice. Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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