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path: root/src/northbridge/intel/sandybridge
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2012-07-26CTDP: Only do TDP down/nominal change from TNP0Duncan Laurie
Otherwise there is a flurry of TDP changes with suspend/resume as the kernel powers devices off on suspend and brings them back online in resume. This also adds a mutex around the TDP operations since it is split across two methods and can't just rely on being Serialized. Change-Id: I7757d3ddad34ac985a9c8ce2fc202e2b2dcb2527 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1348 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-26ACPI: Add support for runtime config TDP downDuncan Laurie
The required power MSRs are mirrored in MCHBAR so it is possible to configure TDP at runtime via ASL. This adds the required fields and a set of methods to configure "TDP down" and "TDP nominal". It explicitly does not support "TDP up" at the moment. PSSS: method is added to assist in searching the _PSS table for the appropriate entry that corresponds to the desired max non-turbo ratio. STND: Set TDP Down from Nominal. This will limit CPU to the TDP down configuration by sequencing the required changes in the right order. STDN: Set TDP Nominal from Down. This will set the CPU back to nominal configuration by sequencing the required changes in the correct (reverse) order. This does not introduce any functional changes and must be paired with additional changes to be useful. The current configured TDP can be checked to see that the transition to/from a desired level is successful. > mmio_read8 0xfed15f50 0x00 # TDP-Nominal > mmio_read8 0xfed15f50 0x01 # TDP-Down Change-Id: I31a2f30cc9d134cc5eee980ae9288ae45e71c6e6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1344 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25ELOG: Add support for a monotonic boot counter in CMOSDuncan Laurie
This maintains a 32bit monotonically increasing boot counter that is stored in CMOS and logged on every non-S3 boot when the event log is initialized. In CMOS the count is prefixed with a 16bit signature and appended with a 16bit checksum. This counter is incremented in sandybridge early_init which is called by romstage. It is incremented early in order notice when reboots happen after memory init. The counter is then logged when ELOG is initialized and will store the boot count as part of a 'System boot; event. Reboot a few times and look for 'System boot' events in the event log and check that they are increasing. Also verify that the counter does NOT increase when resuming from S3. 171 | 2012-06-23 16:02:55 | System boot | 285 176 | 2012-06-23 16:26:00 | System boot | 286 182 | 2012-06-23 16:27:04 | System boot | 287 189 | 2012-06-23 16:31:10 | System boot | 288 Change-Id: I23faeafcf155edfd10aa6882598b3883575f8a33 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1315 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25More descriptive error messages in Sandybridge raminit codeStefan Reinauer
MRC returns specific error codes; print the according error message if we know what it means. Change-Id: Iaaf1512b9d577d4291fccfb94d879043ab5b11b5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1289 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24ELOG: Fix boot count increment for non-wake caseDuncan Laurie
The count was only incrementing for a wake from S5 and it was not incrementing in the normal reboot case. Change-Id: I73bc6db6bd02e6c4677f7e44a5c098c6dcb51747 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/1328 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Ivybridge: fix workaround and enable PAIRDuncan Laurie
MCHBAR 0x5f10[7:0] should be set to 0x30 for ivybridge and 0x20 for sandybridge. Move this code to ramstage and set it per-chipset. Power Aware Interrupt Routing is supported in ivybridge, enable it and set fixed priority. Boot on ivybridge device and read MCHBAR 0x5f10: mmio_read8 0xfed15f10 0x30 And verify PAIR is enabled (bit4=1): mmio_read8 0xfed15418 0x24 Change-Id: If017d5ce2bd5ab5092c86f657434f2b645ee6613 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1303 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
Ivybridge B0+ CPUs are capable of supporting multiple TDP levels. This complicates the default case because now the registers that were reporting max non-turbo ratio are reporting that value for the highest possible TDP level. For now this change just forces everything to use the Nominal TDP values instead of the higher (or lower) levels. - When building P-state tables, determine the P[1] (max non turbo) ratio based on the Nominal ratio if available. - Set the turbo activation ratio to the Nominal max ratio. - Mirror the power level settings in new MCHBAR register after they are written, which happens after BIOS_RESET_CPL is set. - Set the current ratio to Nominal ratio at boot. 1) Verify that P-state table is generated properly with P[0]=1801MHz (ratio 0x1C) and P[1]=1800MHz (ratio 0x12) PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00 PSS: 1800MHz power 17000 control 0x1200 status 0x1200 2) Verify power limits in MCHBAR match PKG_POWER_LIMIT: > rdmsr 0 0x610 0x800080aa00dc8088 > mmio_read32 0xfed159a4 0x000080aa > mmio_read32 0xfed159a0 0x00dc8088 3) Verify turbo activation ratio is set to nominal ratio: > rdmsr 0 0x64c 0x0000000000000012 4) Check that proper ratio was set at boot on one core only: > grep 'frequency set to' /sys/firmware/log model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 Change-Id: I592e60a7740f31b140986a8269dca91b4adbb270 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1304 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Make ACPI code detect Sandy/Ivy Bridge dynamicallyStefan Reinauer
On systems with socketed CPUs we want to be able to drop in a Sandy Bridge or Ivy Bridge CPU without recompiling the firmware. Hence, detect the north bridge dynamically. In order for this to work, we need Ivy Bridge MRC and coreboot configured for Ivy Bridge. Change-Id: I635bef2c61d47d36a3fdd87f8ecb6e69097ba969 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24Drop (empty) sandybridge_late_initialization()Stefan Reinauer
The function is empty (a left-over from i945) and should be removed. Change-Id: I91e573b5e37cb9133ea1037aef7e6daf3c292864 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1290 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24Add support for HM70 and NM70 LPC bridgeStefan Reinauer
This lets the SPI driver and the LPC driver know about HM70 and NM70. Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1300 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24Print PCI ID of PCH during boot upStefan Reinauer
Right now, if we have an unknown PCH, coreboot will print something like this: PCH type: Unknown rev id 4 Instead, it should also print the PCI ID of the device, so we can add it to the list of known PCHes. Change-Id: Ib0b96e287c36d2895d1287b1734ca13d75e7985a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1287 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24Drop leading spaces from CPU name stringStefan Reinauer
This is as per Intel's suggestion on how to display their name strings. Change-Id: Ie82341305e58baa8041e50a61a11b395fa7d9582 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1298 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-07-24Fix MRC cache update delaysStefan Reinauer
When no valid MRC cache area is found, the mrc_cache data structure was used without prior initialization. This sometimes caused a long delay when booting because compute_ip_checksum would checksum up to 4GB of memory. Change-Id: I6a0ca1aa618838bbc3d042be425700fc34b427f2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1277 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24SandyBridge: Add another PCI device ID for northbridgeWalter Murphy
Change-Id: I153579561f7eed6d4befd74ff39e1a5e778d0e46 Signed-off-by: Walter Murphy <wmurphy@google.com> Reviewed-on: http://review.coreboot.org/1269 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-07-24Fixes to enable RC6 on IvyBridgeDuncan Laurie
- The unneeded poll on non-MT force-wake bit was timing out and causing the gma_pm_init_pre_vbios() function to exit early so it was not preparing PM registers properly. I changed the gtt_poll() calls to not return on timeout unless it can't proceed so we don't see half-initialized registers. - RC6+ (Deep Render Standby) is not working reliably so we can just enable RC6 in the BIOS and let the kernel decide if it wants to enable RC6+ later. This Kernel message is new in kernel 3.4: [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off Change-Id: I69d005ba56be8c7684a4ea1133a1d761f7c07acc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1268 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-16Define global uma_memory variablesKyösti Mälkki
Use of the uma_memory_base and _size variables is very scattered. Implementation of setup_uma_memory() will appear in each northbridge. It should be possible to do this setup entirely in northbridge code and get rid of the globals in a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29Sandybridge: Remove remnants of FDT support from MRC cache codeStefan Reinauer
Originally, ChromeBooks would get the offset of the MRC cache from an entry in the u-boot device tree. Not everyone wants to use u-boot on Sandybridge systems, however. Since the new code (based on Kconfig) is now fully working, we can drop the u-boot device tree remnants. Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1051 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29Sandybridge: Fix MRC cache calculationStefan Reinauer
The MRC region is described by Kconfig variables, no further math or parsing is required at this point. Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1046 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-11Hook up MRC cache updateStefan Reinauer
Requirements: - must be in ramstage (locking flash while executing code from there might not work) - must be after cbmem is reinitialized (so the mrc cache copy of the current run can be found) Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1002 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
- Separate Sandybridge from ChromeOS a bit The Sandybridge code depends on chromeos features a whole lot. As a first step, provide a code path to look up the MRC cache without depending on u-boot. - Move mrc cache handling to separate file This enables us to handle the MRC cache from ramstage, where we can write the flash safely (eg. to update the cache). Also teach it to lookup the current MRC cache from CBMEM, as the original data block isn't available anymore. After all the preparations, finally write to the SPI as necessary. It's a simple round robin wear levelling that erases the entire MRC cache region when it's full and starts from the beginning. Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1001 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-03Add missing newline to printk in Sandybridge init codeStefan Reinauer
Change-Id: I9217a75ec1a0abb898c45752d990231ce98e5fb2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/991 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-02Strip quotes from Sandybridge MRC blobStefan Reinauer
This fixes my build when specifying an absolute path to the binary. Change-Id: I95fb3960be70f78146c6afeb9cc777dccdca6b5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/987 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-02Sandybridge: Display platform information earlyVadim Bendebury
It is important to have the system configuration reported as early as possible to have a better idea what exact chipset the platform is running with. This change adds code to have an early coreboot module report the CPU and PCH information. CPU info includes the 32 bit feature information word, the symbolic processor brand string, and information about some features support, as obtained through CPUID instructions. The PCH information includes the symbolic device name and PCI device version. Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/975 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-01Update Ivybridge GT power meter tablesDuncan Laurie
- New table for GT1 - Updates to GT2 17W table - New table for GT2 35W SKU - New table for GT2 Other This also includes a workaround to poll on a different register when deasserting force wake. On some SKUs the kernel is hanging when bringing up graphics unless this register is also polled. Change-Id: I2badf62b464e901cfb0eaf4fc196f59111c71564 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/974 Tested-by: build bot (Jenkins)
2012-05-01Update ivybridge graphics initializationDuncan Laurie
- Add config options to set backlight registers - Update powermeter weight tables for IvyBridge GT1 and add a new table for GT2 SKU - Fix a few registers used during GPU PM init sequence Change-Id: I1500bc07e3ba1bc10c77e7856089e716489dc07a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/973 Tested-by: build bot (Jenkins)
2012-05-01Only send ME Dram Init Done message on SandybridgeDuncan Laurie
This is done inside the SystemAgent binary on Ivybridge. Change-Id: I8fb0f593a65a4803e160b284c21b9d5021e2e4a0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/970 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01Modify DMI init for IvyBridgeVincent Palatin
The ASPM setting for the Direct Media Interface should no longer be done on Ivybridge/PantherPoint based systems. Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://review.coreboot.org/969 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01Fix Sandybridge/Ivybridge mainboards according to code reviewStefan Reinauer
This fixes a few cosmetics with the following three boards: - Intel Emerald Lake 2 - Samsung ChromeBook - Samsung ChromeBox The following issues were fixed: - rely on include path in ASL code instead of specifying relative paths - use updated ALIGN_CURRENT in acpi_tables.c - use preprocessor defines instead of hard coded values where possible Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/963 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2012-04-30Sandybridge: Temporarily disable MRC cache finding codeStefan Reinauer
This code is still using libfdt which was denied for inclusion in coreboot, so it won't compile as is. Without MRC cache, waking from suspend won't work, and cold boots are significantly slower (adds around 300-400ms per channel IIRC). A rework of this code is currently in the works, but will take a little bit more time (and should not hold back the mainboards being merged) Change-Id: Ifb9e7d7b86c1f52378803a748810da0d51b58384 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/948 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-28Reverse Vendor ID & Device ID for map_oprom_vendev()Martin Roth
- When calling map_oprom_vendev() the vendor ID and device ID are joined into a 32 bit value. They were reversed from the order that I would have expected - Device ID as the high 16 bits and the Vendor ID as the low 16. This patch reverses them so so that the the dword comparison in map_oprom_vendev() matches what's entered into Kconfig for vendor,device. - Change files calling map_oprom_vendev() Change-Id: I5b84db3cb1a359a7533409fde7d05fbc6ba3fcc4 Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/938 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27SMM: Add udelay on Sandybridge systemsStefan Reinauer
Cougar Point southbridge does udelay in SMM, hence add it on Sandybridge systems. Change-Id: I6e5520ca27e7c6eaae632992fb68612067bc1e30 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/937 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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