coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
	They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15	nb/intel/pineview: Clean up code and comments	Angel Pons
	- Reformat some lines of code - Put names to all MCHBAR registers in a separate file - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) - Align a bunch of things Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected. Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-01	intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL	Kyösti Mälkki
	This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-05-25	nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK	Arthur Heymans
	This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-14	nb/intel/pineview: Move the boilerplate mainboard_romstage_entry	Arthur Heymans
	The mainboard_romstage_entry function is mostly boilerplate, so move it to a common location and provide mainboard specific callbacks. Change-Id: I33cf1d6a60d272f490f41205ec725dee8b00242b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14	nb/intel/{i945,pineview}: Remove unused function	Arthur Heymans
	Change-Id: I6ca83bde61f231b9f79c90af1d6c1cfa1a027768 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-06-07	nb/intel/pineview: Enable and allocate 8M for TSEG	Arthur Heymans
	TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25593 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2016-11-21	nb/intel: Fix some spelling mistakes in comments and strings	Martin Roth
	Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17478 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-28	nb/intel/pineview: Native VGA init (CRT)	Damien Zammit
	VGA grub console works but display wobbles left/right drm/i915 driver reports one error: - [drm:i915_irq_handler] ERROR pipe A underrun - Monitor does not display 1920x1080 after modeset - Other resolutions look out of sync Cause: suspect single bug in raminit (chipset init) Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12921 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02	northbridge/intel/pineview: Add remaining boilerplate code for northbridge	Damien Zammit
	This patch does not include native raminit Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12430 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-11-24	northbridge/intel/pineview: Add minimal Pineview northbridge	Damien Zammit
	Based on i945. Tested on Intel D510MO mainboard, board boots to UART console with this code. Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/10073 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>