coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-03-06	Remove DEFAULT_PCIEXBAR alias	Kyösti Mälkki
	The other DEFAULT_ entries are just immediate constants. Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-29	sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables	Arthur Heymans
	Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. TESTED on Intel DG43GT: show correct PIRQ ACPI entries in /sys/firmware/acpi/tables/SSDT. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-26	nb/intel/pineview: Increase MMCONF decoding to 256 busses	Damien Zammit
	Linux kernel detects 256 busses but previously only 64 were allocated. Removes warning in OS. Change-Id: Id83c85e60025a04acbe6a53dfea6878222d8791f Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13033 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-02	northbridge/intel/pineview: Add remaining boilerplate code for northbridge	Damien Zammit
	This patch does not include native raminit Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12430 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)