coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-08-07	northbridge/intel: Rename ram_calc.c to memmap.c	Kyösti Mälkki
	Use a name consistent with the more recent soc/intel. Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-03	intel/i945,gm45,pineview,x4x: Move stage cache support function	Kyösti Mälkki
	Let garbage-collection take care of stage_cache_external_region() when it is not needed and move implementation to a suitable file already building for needed stages. Change-Id: Ic32adcc62c7ee21bf38e2e4e5ece00524871b091 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-25	nb/intel/pineview: Use MTRR as a proxy for proper reset	Arthur Heymans
	On reset this platform can sometimes hang. This also fixes pineview mainboards not building due to the symbol 'check_mtrr' lacking. Change-Id: I61fe77113004ea664522bda549240a33e3742a98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-25	nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK	Arthur Heymans
	This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24	nb/intel/pineview: Put stage cache in TSEG	Arthur Heymans
	TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Tested on Foxconn D41S. Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25605 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14	nb/intel/pineview: Move the boilerplate mainboard_romstage_entry	Arthur Heymans
	The mainboard_romstage_entry function is mostly boilerplate, so move it to a common location and provide mainboard specific callbacks. Change-Id: I33cf1d6a60d272f490f41205ec725dee8b00242b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05	nb/intel/pineview: Switch to POSTCAR_STAGE	Arthur Heymans
	Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-01-28	nb/intel/pineview: Native VGA init (CRT)	Damien Zammit
	VGA grub console works but display wobbles left/right drm/i915 driver reports one error: - [drm:i915_irq_handler] ERROR pipe A underrun - Monitor does not display 1920x1080 after modeset - Other resolutions look out of sync Cause: suspect single bug in raminit (chipset init) Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12921 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02	northbridge/intel/pineview: Add native raminit	Damien Zammit
	Does native ram init for Intel Atom D5xx 8086:a000 northbridge Tested on Intel D510MO mainboard, board boots linux kernel - Works fully with both dimms populated (2x2GB), memtest passes 100% - Almost boots with only one dimm in one of the slots (suspect bad memory map with one dimm?) - Reads garbage with only one dimm in other slot Change-Id: Ibd22be2a959045e0a83aae2a3a0e877013f80711 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-02	northbridge/intel/pineview: Add remaining boilerplate code for northbridge	Damien Zammit
	This patch does not include native raminit Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12430 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-11-24	northbridge/intel/pineview: Add minimal Pineview northbridge	Damien Zammit
	Based on i945. Tested on Intel D510MO mainboard, board boots to UART console with this code. Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/10073 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>