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path: root/src/northbridge/intel/i945/i945.h
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2021-01-30nb/intel/i945: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: I5c75409fd3b7b018e402c471cbd856eca20278b7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49757 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07nb/intel/i945: Introduce memmap.hPatrick Georgi
Inspired by Idca25b2e4bf65abcb and Ib275f9ad8ca9ff move all memory map definitions into a header with a common name. Change-Id: I32a99f70f4d2eb52367c9edfc0aa6d5da2fec03f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-21src/northbridge: Drop unneeded empty linesElyes HAOUAS
Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04nb/intel/i945: Deduplicate PCIEXBAR decodingAngel Pons
We can use `decode_pcie_bar` instead, if we make it non-static. Change-Id: Ic39f3df0293b4d44f031515b1f868e0bb9f750c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-22nb/intel/i945: Put names to northbridge PCI devicesAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I0d51f48f0c1e37c41322a0eda49806925d9d194d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42285 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id2cb642baa764fd69543460ba869cd822ab5acad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15nb/intel/i945: Initialize console in bootblockArthur Heymans
Change-Id: Ic6ea158714998195614a63ee46a057f405de5616 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-15nb/intel/i945: Move boilerplate romstage to a common locationArthur Heymans
This adds callbacks for mainboard specific init. Change-Id: Ib67bc492a7b7f02f9b57a52fd6730e16501b436e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36787 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01nb/intel: Remove unused 'barrier()'Elyes HAOUAS
Change-Id: I0c33a1f3f9c33c15a901fe90258ed989e9641701 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-05intel/i945,i82801gx: Refactor early PCI bridge resetKyösti Mälkki
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-01intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki
This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-24nb/intel/i945: Use DEBUG_RAM_SETUPKyösti Mälkki
Avoid preprocessor here, also we never set loglevel to value of >8 so the call would not be made. The calls to ram_check() were removed, for a long time that function has not tested start..stop region. Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-06Remove DEFAULT_PCIEXBAR aliasKyösti Mälkki
The other DEFAULT_ entries are just immediate constants. Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-14nb/intel/{i945,pineview}: Remove unused functionArthur Heymans
Change-Id: I6ca83bde61f231b9f79c90af1d6c1cfa1a027768 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-13{mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()Elyes HAOUAS
Use hexdump() instead of dump_mem(). Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-11-25nb/intel/i945: Add and use defines for registers of device 0:01.0Elyes HAOUAS
Some registers are not documented in "Mobile Intel 945 Express Chipset Family" datasheet but they are in "Intel 945G/945GZ/ 945GC/945P/945PL Express Chipset Family" datasheet. Change-Id: I81f68a5b16e195626d4d271f8c7036032611bea3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans
This adds a common function to decode the TSEG size from the ESMRAM register. This will come in handy when SMM in TSEG is implemented. This function is used both in romstage and in ramstage. Change-Id: I4e163598752fb6cd036aec229fce439ebad74def Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23448 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23nb/intel/i945: Use ESMRAMC instead of 0x9eElyes HAOUAS
Macro renamed to be in accordance with the name used in the datasheet. Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-03-22nb/intel/i945: Fix errors found by checkpatch.plArthur Heymans
Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18704 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13i945.h: fix #include pathAntonello Dettori
Fix the #include path. Change-Id: Ifefb2faef6e4fc87152acb21c37dd87e7c14645c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16294 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31i945: Enable changing VRAM sizeArthur Heymans
On i945 the vram size is the default 8mb. It is also possible to set it 1mb or 0mb hardcoding the GGC register in early_init.c The intel documentation on i945, "Mobile Intel® 945 Express Chipset Family datasheet june 2008" only documents those three options. They are set using 3 bits. The documententation also makes mention of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. The other non documented (straight forward) bit combinations allow to change the VRAM size to those other states. What this patch does is: - add those undocumented registers with their respective vram size to the i945 NB code; - make this a cmos option on targets that have this northbridge. TEST: build, flash to target, set cmos as desired and boot linux. On Debian it can be found using "dmesg | grep stolen". NOTE: dmesg message about reserved vram are quite different depending on linux version Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2014-11-28i945: make PCIe link wait sensiblePatrick Georgi
Waiting for (a & 4) == 3 to become true proves futile unless you're searching for defective hardware or neutrino impact. While I'm not 100% sure that this is the actual intent (no data-sheets at hand, and the public ones are unhelpful as usual), it's the likely correct version and it's also boot-tested on intel/d945gclf. While at it, replace register number with the name found in the public datasheet. Change-Id: I4b87001967a2013e0089806e8cd606d5ee81b0d9 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6575 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09i945: consolidate sb & nb early initsVladimir Serbinenko
Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7062 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-06-03northbridge/intel/i945/gma.c: Add and use defines for `GMADR` and `GTTADR`Paul Menzel
Change-Id: I0f39b35fbf8e053ba21454a2847d6bb3ac5d2e1c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5923 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03northbridge/intel/i945/i945.h: Move define `BSM` to section D2F0Paul Menzel
The Base of Stolen Memory (BSM) register belongs to device 2, function 0. Change-Id: I2381f87ffaccb2f8034c160fc30c1d92f8b19402 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5922 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01northbridge/intel/i945/i945.h: Trivial, fixup header guardsEdward O'Callaghan
Change-Id: Iff15ab436e5b7b4e189c7341e7c508faaef07a3a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5896 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-31northbridge/intel/i945: Add define for register `BSM` and use itPaul Menzel
Add a define for the register Base of Stolen Memory (BSM) and use it. Change-Id: I5b1df4e088d88344fac8cd8d218e76b08a885f58 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5884 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-06-07i945: Add Display defines for int15h handler.Denis 'GNUtoo' Carikli
Change-Id: I7bc99761c7047e64b4e29c307ad779cec49c17c8 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3306 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2010-12-07Get rid of some unneeded function prototypes in romstage.c files.Uwe Hermann
Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05Remove lib/ramtest.c-include from all CAR boards.Patrick Georgi
Remove many more .c-includes from i945 based boards. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14i945:Stefan Reinauer
* fix some potential compiler issues with newer gccs * add some more comments * make 32bit accesses for feature test functions * make some objects drivers because they contain a pci_driver struct. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26Kontron 986LCD-M updateStefan Reinauer
- run ACPI code through preprocessor so we get the same values as the C code - fix PCIe x16 slot - fix ICH7 Azalia/HDA driver - SMI/GNVS update security fix (only allow struct pointer update once) - ACPI updates - IDE driver fixes - add cmos options for disabling onboard ethernet and controlling system fan Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12drop extra whitespace at end of line for i945 + ICH7 (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21* drop ich7 includeStefan Reinauer
* detect more i945 variants * raminit fixes * ACPI + PCIe updates Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-10Merge some parts of the i945 review (trivial):Stefan Reinauer
* fix \r\n occurence in i945 code * drop early TOLUD write * fix 16bit BCTRL1 access Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-09i945.h: Add some more comments, align data for better readability (trivial).Uwe Hermann
Also, add missing C1DRA2 #define (as per public datasheet). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for the Intel 945 northbridge.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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