coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2008-12-09	Add (parts of the) support for multiple DIMMs on the Intel 440BX chipset.	Uwe Hermann
2008-11-27	Remove the unnecessary memctrl[] indirection, 440BX only has one	Uwe Hermann
2008-10-01	The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of	Carl-Daniel Hailfinger
2008-09-30	A duplicate register address is incremented in table register_values.	Mats Erik Andersson
2008-01-18	Please bear with me - another rename checkin. This qualifies as trivial, no	Stefan Reinauer
2007-10-27	Drop duplicated and unneeded #defines from some northbridges (trivial).	Uwe Hermann
2007-10-24	Ever wondered where those "setting incorrect section attributes for	Stefan Reinauer
2007-06-07	Minor tweaks in the 440BX RAM init code (trivial).	Uwe Hermann
2007-05-28	Lower the RAM init delays we use on the Intel 440BX.	Uwe Hermann
2007-05-27	Various 440BX and Tyan S1846 related minor changes and fixes (trivial):	Uwe Hermann
2007-05-10	Fixup the 440BX northbridge.c (self-ack as this wasn't working anyway).	Uwe Hermann
2007-05-10	Fixed a bug within the 440BX RAM size calculation. Since the DRB values	Ceri Coburn
2007-05-04	Cosmetics (trivial).	Uwe Hermann
2007-04-30	Fix typo: s/PRINT_DEBUG_/PRINT_DEBUG/ (trivial).	Uwe Hermann
2007-04-01	Initial Intel 440BX RAM initialization framework.	Uwe Hermann
2006-11-30	Add convenience macros PAM0..PAM6 (trivial).	Uwe Hermann
2006-11-11	Add missing bracket in comment, and fix whitespace (trivial).	Uwe Hermann
2006-11-10	Add an include file which contains the register definitions for the	Uwe Hermann
2006-11-05	Use the canonical name of the vendors/devices and the	Uwe Hermann
2006-07-29	- Add support _framework_ for the Asus p2b.	Richard Smith
2006-07-24	add framework for i440bx chipset	Richard Smith