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2017-01-06nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>Arthur Heymans
Nothing from that header is used or even declared since CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not selected on Intel hardware. Change-Id: I9101eb6ffa6664a2ab45bc0b247279c916266537 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18044 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2016-12-07MMCONF_SUPPORT: Drop redundant loggingKyösti Mälkki
Resource is actually stored even before read_resources, but that's where we currently log this resource. For Intel, use PCI config register offset as the resource index, while AMD side uses MSR address. Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17696 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Consolidate resource registrationKyösti Mälkki
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-21nb/intel: Fix some spelling mistakes in comments and stringsMartin Roth
Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17478 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-20northbridge/intel/i3100: Add space around operatorsElyes HAOUAS
Change-Id: I5ff894f23dc2a2c59bc5e5d1de4287a6b9c9922c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/intel: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I53208ce5db06d2c65f954e6d59222924ab87722e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16304 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/northbridge: Capitalize CPU, RAM and ROMElyes HAOUAS
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-16cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin
The Intel i3100 northbridge code is the only user of cache_ramstage(). Therefore, place it next to the sole consumer. Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14097 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-13northbridge/intel/i3100: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i3100 boards in the chipset. Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13786 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-28northbridge/intel: add missing #include guardsIru Cai
I first found the missing of #include guards when I tried to include both sandybridge/gma.h and sandybridge/sandybridge.h, but sandybridge.h includes gma.h in it and gives a compile error. Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/13775 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-06-05lib: Unify log2() and related functionsJulius Werner
This patch adds a few bit counting functions that are commonly needed for certain register calculations. We previously had a log2() implementation already, but it was awkwardly split between some C code that's only available in ramstage and an optimized x86-specific implementation in pre-RAM that prevented other archs from pulling it into earlier stages. Using __builtin_clz() as the baseline allows GCC to inline optimized assembly for most archs (including CLZ on ARM/ARM64 and BSR on x86), and to perform constant-folding if possible. What was previously named log2f on pre-RAM x86 is now ffs, since that's the standard name for that operation and I honestly don't have the slightest idea how it could've ever ended up being called log2f (which in POSIX is 'binary(2) LOGarithm with Float result, whereas the Find First Set operation has no direct correlation to logarithms that I know of). Make ffs result 0-based instead of the POSIX standard's 1-based since that is consistent with clz, log2 and the former log2f, and generally closer to what you want for most applications (a value that can directly be used as a shift to reach the found bit). Call it __ffs() instead of ffs() to avoid problems when importing code, since that's what Linux uses for the 0-based operation. CQ-DEPEND=CL:273023 BRANCH=None BUG=None TEST=Built on Big, Falco, Jerry, Oak and Urara. Compared old and new log2() and __ffs() results on Falco for a bunch of test values. Change-Id: I599209b342059e17b3130621edb6b6bbeae26876 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3701a16ae944ecff9c54fa9a50d28015690fcb2f Original-Change-Id: I60f7cf893792508188fa04d088401a8bca4b4af6 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/273008 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-04devicetree: Change scan_bus() prototype in device opsKyösti Mälkki
The input/output value max is no longer used for tracking the bus enumeration sequence, everything is handled in the context of devicetree bus objects. Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8541 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-29kbuild: automatically include northbridgesStefan Reinauer
This change switches all northbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in northbridge/Makefile.inc or in northbridge/<vendor>/Makefile.inc. This means, vendor and northbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I8468154dbfaaaffcba9fda27ba2d7b9049ad5c19 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9800 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01devicetree: Drop redundant scan_bus() opsKyösti Mälkki
Change-Id: If96e0843f507b9f1db9977b5d0c47f5ed1c59999 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8533 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Tag chipsets with LATE_CBMEM_INITKyösti Mälkki
In preparation to remove the static CBMEM allocator, tag the chipsets that still do not implement get_top_of_ram() for romstage. LATE_CBMEM_INIT also implies BROKEN_CAR_MIGRATE. Change-Id: Iad359db2e65ac15c54ff6e9635429628e4db6fde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7850 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-06northbridge: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the northbridge code to use printk() on all non-ROMCC boards. Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7856 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-18intel/truxton: Un-romcc-ify boardStefan Reinauer
Change-Id: Iaf1756321960041f6a152d5dd4c9108291f51300 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7852 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-11-01northbridge/intel: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: I9aeed70f72d4df260312df6e53379f1741415b65 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7287 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-10-18i3100: Convert to per-device ACPIVladimir Serbinenko
Change-Id: Id90db4f6ce1a5fb506c81bc3a6010d85b0aa8c43 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6940 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-07-29Uniformly spell frequency unit symbol as HzElyes HAOUAS
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6384 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-11src: Make use of 'CEIL_DIV(a, b)' macro across treeEdward O'Callaghan
The objective here is to tighten coreboot up a bit by not repeating common helpers. This makes the code base more consistent and unified/tight. Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-08northbridge: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I9515778e97cc5ae0e366b888da90a651ae5994fe Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6210 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25northbridge/intel/i3100/raminit.c: Uninitialized variableEdward O'Callaghan
Spotted by Clang Change-Id: If524a5cd984602a332c4ca28a8167a3597206b94 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5844 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-13lib: Make log2() available in romstage on ARM, not just x86Alexandru Gagniuc
On x86, log2() is defined as an inline function in arch/io.h. This is a remnant of ROMCC, and forced us to not include clog2.c in romstage. As a result, romstage on ARM has no log2(). Use the inline log2 only with ROMCC, but otherwise, use the one in clog2.c. Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4681 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-11CBMEM northbridges: Remove references to global high_tables_baseKyösti Mälkki
Use the new helper function set_top_of_ram() to remove remaining uses of high_tables_base and _size under northbridge/. Change-Id: I6b0d9615002ed2aff578c5811d7bd43dd2594453 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3561 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-11Set PCI bus operations at buildtime for ramstageKyösti Mälkki
PCI bus operations are static through the ramstage, and should be initialized from the very beginning. For all the replaced instances, there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for the northbridge, so these continue to use PCI IO config access. Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-04Move select MMCONF_SUPPORT under northbridge (fix)Kyösti Mälkki
I missed the board with gm45 when I moved MMCONF_SUPPORT lines. Also, the intel/i3100 does not have MMCONF_SUPPORT implemented even though it was previously selected for intel/eagleheights board. Change-Id: I9c7f6b0a150b4d54288a1e015277b9d98467fca4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3598 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03Move select MMCONF_SUPPORT under northbridgeKyösti Mälkki
Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as that feature originates from northbridge and cannot be disabled for a single mainboard. Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3589 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10Get rid of a number of __GNUC__ checksStefan Reinauer
In the process of streamlining coreboot code and getting rid of unneeded ifdefs, drop a number of unneeded checks for the GNU C compiler. This also cleans up x86emu/types.h significantly by dropping all the duplicate types in there. Change-Id: I0bf289e149ed02e5170751c101adc335b849a410 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3226 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-10Drop prototype guarding for romccStefan Reinauer
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-28Drop CONFIG_WRITE_HIGH_TABLESStefan Reinauer
It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1928 Tested-by: build bot (Jenkins)
2012-11-27Get rid of drivers classPatrick Georgi
The use of ramstage.a required the build system to handle some object files in a special way, which were put in the drivers class. These object files didn't provide any symbols that were used directly (but only via linker magic), and so the linker never considered them for inclusion. With ramstage.a gone, we can drop this special class, too. Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-22Auto-declare chip_operationsKyösti Mälkki
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
... and don't require it to specify a cache type. This function is only used on romcc boards, and should go away (because all boards should be switched to CAR) Change-Id: Ic32ca3be1afffc773c72c140e88b338d48a0c8ca Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1288 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-03-07Move C labels to start-of-linePatrick Georgi
Also mark the corresponding lint test stable. Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09Replace while with do; while to avoid repetitionNoe Rubinstein
Cosmetic only; replaces some 'while' loops with 'do; while' loops to avoid repetition. Replacement performed by the Ruby expression: t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/, "\\1do \\2\n\\1\\3;") Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/183 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2010-12-13We hardcode highmemory size in every northbridge! This is bad, and ↵Rudolf Marek
especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic. Abuild tested. Please check all changes if I did not make any wrong while converting this to bytes. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Move DIMM_MAP_LOGICAL to Kconfig.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-15Move RCBA defines to northbridge (instead of mainboard)Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26Convert some comments to proper Doxygen syntax.Uwe Hermann
Also, make them all fit in 80chars/column, fix some whitespace issues and also some typos I noticed. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11Factor out a few commonly duplicated functions from northbridge.c.Uwe Hermann
The following functions are moved to devices/device_util.c: - ram_resource() - tolm_test() - find_pci_tolm() There are only two tolm_test() / find_pci_tolm() which differ from the defaults, one of them can easily be eliminated in a follow-up patch, maybe even both, but for now keep it simple and only eliminate the majority. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30Rename build system variables to be more intuitive, andPatrick Georgi
at the same time let the user specify sources instead of object files: - objs becomes ramstage-srcs - initobjs becomes romstage-srcs - driver becomes driver-srcs - smmobj becomes smm-srcs The user servicable parts are named accordingly: ramstage-y, romstage-y, driver-y, smm-y Also, the object file names are properly renamed now, using .ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently. Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't easily fit in the build system and aren't useful anyway. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coreystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30We call this cache as ram everywhere, so let's call it the same in KconfigStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-27drop three unneeded config variables:Jens Rottmann
- HAVE_HIGH_TABLES - HAVE_LOW_TABLES - FALLBACK_SIZE Jens Rottmann sent an almost identical patch at the same time, so Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-08Fix all warnings in the tree Stefan Reinauer
(does not fix the cmos.layout race yet) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-17Always enable parent resources before child resources.Myles Watson
Always initialize parents before children. Move s2881 code into a driver. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-09Same conversion as with resources from static arrays to lists, exceptMyles Watson
there is no free list. Converting resource arrays to lists reduced the size of each device struct from 1092 to 228 bytes. Converting link arrays to lists reduced the size of each device struct from 228 to 68 bytes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-21Use lists instead of arrays for resources in devices to reduce memory usage.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-30fix compilation of mtarvonStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-30Get rid of a few more warnings.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27Since some people disapprove of white space cleanups mixed in regular commitsStefan Reinauer
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-16fix romcc compiled i3100 boards.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-16zero warnings days: unify mp tables. fix warnings.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-14drop quite a lot of dead code that did nothing but produce warnings and makeStefan Reinauer
the rest of the code unreadable. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-31Drop \r\n and \n\r as both print_XXX and printk now do this internally.Stefan Reinauer
Only some assembler files still have \r\n ... Can we move that part to C completely? Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22Fix all the format string warnings.Myles Watson
Some other random warnings. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22printk_foo -> printk(BIOS_FOO, ...)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16pci drivers should be const.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-11Replace clear_memory with memset.Myles Watson
Replace set_init_ram_access with the call to set_var_mtrr. Remove unused #include statments. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22This is a general cleanup patchStefan Reinauer
- drop include/part and move files to include/ - get rid lots of warnings - make resource allocator happy with w83627thg - trivial cbmem resume fix - fix payload and log level settings in abuild - fix kontron mptable for virtual wire mode - drop some dead includes and dead code. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-15Various license header consistency fixes (trivial).Uwe Hermann
- Consistently use the same wording and formatting for all license headers. - Remove useless whitespace, add missing whitespace, fix indentation. - Add missing "This file is part of the coreboot project." where needed. - Change "(C) Copyright John Doe" to "Copyright (C) John Doe" for consistency. - Add some missing "(C)" strings and copyright years where needed. - Move random comments and file descriptions out of the license header. - Drop incorrect file descriptions completely (e.g. lpc47m10x/Makefile.inc). There should be no changes in _content_ of the license headers, if you spot such changes that's a bug, please report! Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07newconfig is no more.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15Add CONFIG_GENERATE_* for tables so that the user can select which tables notMyles Watson
to build, but by default all the tables that are available are built. Make PIRQ table build for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09Remove default n statements to simplify .config and ldoptions files.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29Make CONFIG_HAVE_HIGH_TABLES consistent in where and how it is set.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25some progress on kconfig:Patrick Georgi
- northbridges are done - southbridges are done - Intel CPUs are done, with a design that the board only has to specify the socket it has, and the CPUs are pulled in automatically. There is some more cleanup possible in that area, but I'll do that later - a couple more mainboards compile: - intel/eagleheights - intel/jarrell - intel/mtarvon - intel/truxton - intel/xe7501devkit - sunw/ultra40 - supermicro/h8dme - tyan/s2850 - tyan/s2875 - via/epia - via/epia-cn - via/epia-m - via/epia-m700 - via/epia-n - via/pc2500e (PPC not considered, probably overlooked something) All of them only _build_, but some options are probably completely wrong. To be fixed later Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28This patch adds VGA and PS/2 Keyboard/mouse support to the already existing ↵Arnaud Maye
intel truxton (ep80579) dev board. This patch tries to improve the pcie portA configuration. The Matrox G550e PCIe gfx card shipped along with the dev board is supported. Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-02Move the v3 resource allocator to v2.Myles Watson
Major changes: 1. Separate resource allocation into: A. Read Resources B. Avoid fixed resources (constrain limits) C. Allocate resources D. Set resources Usage notes: Resources which have IORESOURCE_FIXED set in the flags constrain the placement of other resources. All fixed resources will end up outside (above or below) the allocated resources. Domains usually start with base = 0 and limit = 2^address_bits - 1. I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is still there for resources. Some platforms may want to change that, but I didn't want to break anyone's board. Resources are allocated in a single block for memory and another for I/O. Currently the resource allocator doesn't support holes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01Add support for the Intel Eagle Heights development board.Thomas Jourdan
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30This patch unifies the use of config options in v2 to all start with CONFIG_Stefan Reinauer
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30Add high tables support to all northbridges.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots ofCarl-Daniel Hailfinger
code to use it. That makes the code more readable and also less error-prone. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-24Support for the memory controller and PCIe interface of the IntelEd Swierk
EP80579 Integrated Processor (codename "Tolapai"). The memory controller code supports only 64-bit-wide DIMMs with x8 devices and ECC. It has been tested on a development board using a single Micron MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other DIMMs. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28Eric Biederman believes that he and Tom Zimmerman of the defunctEd Swierk
LinuxNetworx own the copyright for the Intel e7520, e7525 and 3100 raminit code. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,Ed Swierk
and renames some existing macros for clarity. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16This patch implements support for the Intel 3100 integrated ↵Ed Swierk
northbridge and RAM controller. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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