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path: root/src/northbridge/intel/haswell
AgeCommit message (Expand)Author
2021-01-24cpu/intel/haswell: Set C9/C10 vccminAngel Pons
2021-01-10cpu/intel/haswell/haswell.h: Align with BroadwellAngel Pons
2021-01-05nb/intel/haswell/memmap.h: Clean upAngel Pons
2021-01-01nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settingsMichael Niewöhner
2021-01-01soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representationMichael Niewöhner
2020-12-30drivers/intel/gma: Include gfx.asl by default for all platforms...Matt DeVillier
2020-12-29soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delayMichael Niewöhner
2020-12-03cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()Julius Werner
2020-11-13mrc_cache: Move code for triggering memory training into mrc_cacheShelley Chen
2020-11-13nb/intel/haswell/acpi: Do not add PEG devices for LPAngel Pons
2020-11-13nb/intel/haswell/acpi: Move PEG and CTDP includes downwardsAngel Pons
2020-11-13nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`Angel Pons
2020-11-13nb/intel/haswell/acpi/hostbridge.asl: Drop unused registersAngel Pons
2020-11-13nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVENAngel Pons
2020-11-13haswell/lynxpoint: Drop remaining uses of `ISLP` methodAngel Pons
2020-11-04haswell: Add Intel TXT support in romstageAngel Pons
2020-11-04nb/intel/haswell: Place CTDP ASL code in a separate scopeAngel Pons
2020-11-04nb/intel/haswell/acpi: Align with BroadwellAngel Pons
2020-10-31{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffixAngel Pons
2020-10-25nb/intel/haswell/gma.c: Drop unused ChromeOS includeAngel Pons
2020-10-25nb/intel/haswell/gma.c: Drop unused `set_translation_table` functionAngel Pons
2020-10-24nb/intel/haswell/gma.c: Drop space after unary `!`Angel Pons
2020-10-24nb/intel/haswell/gma.c: Move log message to the right placeAngel Pons
2020-10-24nb/intel/haswell/gma.c: Use `config_of` in `gma_setup_panel`Angel Pons
2020-10-24nb/intel/haswell/early_init.c: Remove invalid register writesAngel Pons
2020-10-24nb/intel/haswell/finalize.c: Align with BroadwellAngel Pons
2020-10-24nb/intel/haswell/finalize.c: Align MC locking with BroadwellAngel Pons
2020-10-24nb/intel/haswell/finalize.c: Lock down MC ARB registerAngel Pons
2020-10-24nb/intel/haswell/finalize.c: Lock PCU DDR PTMAngel Pons
2020-10-24nb/intel/haswell/finalize.c: Drop obsolete SA PM lockAngel Pons
2020-10-24nb/intel/haswell/finalize.c: Use PCI register namesAngel Pons
2020-10-24nb/intel/haswell: Generalise northbridge chip nameAngel Pons
2020-10-24nb/intel/haswell: Set up Root Complex topologyAngel Pons
2020-10-23nb/intel/haswell/raminit.c: Clean up local variablesAngel Pons
2020-10-23nb/intel/haswell: Correct designation of MRC versionAngel Pons
2020-10-23nb/intel/haswell: Drop ASM to call into MRCAngel Pons
2020-10-23nb/intel/haswell: Constify pointers to stringsAngel Pons
2020-10-23nb/intel/haswell: Make MAD_DIMM_* registers indexedAngel Pons
2020-10-23nb/intel/haswell: Drop unnecessary register readAngel Pons
2020-10-22nb/intel/haswell: Add HASWELL_HIDE_PEG_FROM_MRC optionAngel Pons
2020-10-17intel/txt: Add `txt_get_chipset_dpr` functionAngel Pons
2020-10-15nb/intel/haswell: Account for DPR region in memory mapAngel Pons
2020-09-21src/northbridge: Drop unneeded empty linesElyes HAOUAS
2020-09-17nb/intel/haswell: Put DMIBAR/EPBAR registers into separate filesAngel Pons
2020-09-17nb/intel/haswell: Move register headers into a subfolderAngel Pons
2020-09-17nb/intel/haswell: Clean up register definitionsAngel Pons
2020-09-17nb/intel/haswell: Guard DMIBAR/EPBAR macro parametersAngel Pons
2020-09-17nb/intel/haswell: Introduce memmap.hAngel Pons
2020-09-08nb/intel/haswell: Drop `gpu_panel_port_select`Angel Pons
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
2020-09-02{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS
2020-08-24mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen
2020-08-05{nb,soc}/intel: Use get_current_microcode_rev() for ucode versionSubrata Banik
2020-08-04nb/intel/haswell: Use ASL 2.0 syntaxAngel Pons
2020-08-04nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-03nb/intel/haswell: Add Crystal Well PCI IDsIru Cai
2020-07-31nb/intel/haswell: Configure VCs on Egress PortAngel Pons
2020-07-30nb/intel/*: Fill in SMBIOS type 16 on SNB/HSWPatrick Rudolph
2020-07-28nb/intel/haswell: Enable DMI ASPMAngel Pons
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
2020-07-26nb/intel/haswell: Use macro for dimm->bus_widthElyes HAOUAS
2020-07-25nb/intel/haswell/hostbridge_regs.h: Clean up registersAngel Pons
2020-07-24nb/intel/haswell: Put host bridge registers into its own fileAngel Pons
2020-07-20sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons
2020-07-12nb/intel/haswell/romstage.c: Align pei_data initializersAngel Pons
2020-07-12haswell: Move some MRC settings to devicetreeAngel Pons
2020-07-12haswell: Automatically check if Intel GbE is to be enabledAngel Pons
2020-07-12haswell: Add function to retrieve SPD addressesAngel Pons
2020-07-12haswell: Automatically determine system typeAngel Pons
2020-07-12haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig optionAngel Pons
2020-07-12haswell: Factor out `max_ddr3_freq`Angel Pons
2020-07-12haswell: Compute disabled channel masks at runtimeAngel Pons
2020-07-12mb/asrock/b85m_pro4: Factor out common MRC settingsAngel Pons
2020-07-12haswell: Relocate `mainboard_romstage_entry` to northbridgeAngel Pons
2020-07-12haswell: Drop `struct romstage_params` typeAngel Pons
2020-07-12haswell: Make `copy_spd` a weak functionAngel Pons
2020-07-11nb/intel/haswell: Add `mb_late_romstage_setup` functionAngel Pons
2020-07-09haswell: Drop GPIO indirection layersAngel Pons
2020-07-09haswell: Turn RCBA configuration into a functionAngel Pons
2020-07-08haswell: relocate `romstage_common` to northbridgeAngel Pons
2020-07-08haswell: drop unused function parameterAngel Pons
2020-07-08nb/intel/haswell/acpi: Update to ASL 2.0 syntaxAngel Pons
2020-07-08nb/intel/haswell/acpi: Fix host bridge registersAngel Pons
2020-06-22nb/intel/haswell: Use 16-bit ops on PCI COMMANDAngel Pons
2020-06-09nb/intel/haswell: Use PCI bitwise opsAngel Pons
2020-06-06src: Use pci_dev_ops_pci where applicableAngel Pons
2020-06-06src: Remove unused '#include <cpu/x86/smm.h>'Elyes HAOUAS
2020-06-03northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge...Furquan Shaikh
2020-06-03northbridge/intel/haswell: Update hostbridge.asl to ASL2.0Furquan Shaikh
2020-05-27intel/gma: Only enable bus mastering if we are going to use itNico Huber
2020-05-27intel/gma: Don't bluntly enable I/ONico Huber
2020-05-27drivers/intel/gma: Move IGD OpRegion to CBMEMNico Huber
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
2020-05-12device/pci_device: Extract pci_domain_set_resources from SOCRaul E Rangel
2020-05-11treewide: Replace BSD-3-Clause and ISC headers with SPDX headersPatrick Georgi
2020-05-11treewide: split off license text, remove extra copyright noticesPatrick Georgi
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
2020-05-09vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled()Julius Werner
2020-05-08nb/intel/haswell/northbridge.c: Fix typoAngel Pons
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