coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-01-24	cpu/intel/haswell: Set C9/C10 vccmin	Angel Pons
	Backport commit ab7586fa26 (broadwell: Set C9/C10 vccmin) to Haswell. Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46922 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10	cpu/intel/haswell/haswell.h: Align with Broadwell	Angel Pons
	Sort MSR definitions, move MCHBAR registers to northbridge and relocate C-state latency macros into the header. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46914 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24	nb/intel/haswell/finalize.c: Lock down MC ARB register	Angel Pons
	The Haswell System Agent BIOS Spec revision 0.6.0 indicates this register needs to be locked, and Broadwell already locks it. Tested on Asrock B85M Pro4, still boots and register is locked. Change-Id: Icdeb39e2fdde1403b6ab83faed214addca863f4b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46680 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24	nb/intel/haswell/finalize.c: Lock PCU DDR PTM	Angel Pons
	This register has a lock bit. The Haswell System Agent BIOS Spec revision 0.6.0 indicates it needs to be set, thus set it. Note that Broadwell already locks this register. Tested on Asrock B85M Pro4, still boots and register is locked. Change-Id: Ie23b825e708edbfc04ec0d7783f868e8632eb608 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46679 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23	nb/intel/haswell/raminit.c: Clean up local variables	Angel Pons
	Remove unnecessary arrays, use unsigned types for non-negative values and constify where possible. Also define NUM_CHANNELS and NUM_SLOTS. Change-Id: Ie4eb79d9c48194538c0ee41dca48ea32798ad8c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46363 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23	nb/intel/haswell: Make MAD_DIMM_* registers indexed	Angel Pons
	This allows using the macro in a loop, for instance. Change-Id: Ice43e5db9b4244946afb7f3e55e0c646ac1feffb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-17	nb/intel/haswell: Move register headers into a subfolder	Angel Pons
	Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I143b3c829be44a39e14902255cd4bb13bf02f0c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45354 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>