aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/intel/haswell/northbridge.c
AgeCommit message (Expand)Author
2014-09-22haswell: Move to per-device ACPIVladimir Serbinenko
2014-02-16haswell: backup the default SMM region on resumeAaron Durbin
2014-01-15CBMEM intel: Define get_top_of_ram() once per chipsetKyösti Mälkki
2013-12-12haswell: Export functions for CPU family+model and steppingDuncan Laurie
2013-12-07haswell: Misc power management setup and fixesDuncan Laurie
2013-10-15CBMEM: Define cbmem_top() just once for x86Kyösti Mälkki
2013-07-10Fix MMCONF_SUPPORT_DEFAULT for ramstageKyösti Mälkki
2013-06-03haswell: fix overflow handling TOUUDAaron Durbin
2013-05-01boot: remove cbmem_post_handling()Aaron Durbin
2013-03-23resources: introduce reserved_ram_resource()Aaron Durbin
2013-03-22haswell: use dynamic cbmemAaron Durbin
2013-03-22coreboot: dynamic cbmem requirementAaron Durbin
2013-03-21haswell: use s3_resume field in romstage_handoffAaron Durbin
2013-03-21haswell: cbmem_get_table_location() implementationAaron Durbin
2013-03-18haswell: fix ACPI MCFG tableAaron Durbin
2013-03-18haswell: enable caching before SMM initializationAaron Durbin
2013-03-17haswell: include TSEG region in cacheable memoryAaron Durbin
2013-03-16haswell: don't add a 0-sized memory range resourceAaron Durbin
2013-03-15haswell: Fix BDSM and BGSM indicies in memory mapAaron Durbin
2013-03-15haswell: reserve default SMRAM spaceAaron Durbin
2013-03-15haswell: resource allocationAaron Durbin
2013-03-14haswell: Add ULT device IDsDuncan Laurie
2013-03-14haswell: add PCI id supportAaron Durbin
2013-03-14haswell: Add initial support for Haswell platformsAaron Durbin
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 06:01:05 +0000