coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-02-01	nb/intel/haswell: Calculate TSEG limit from registers	Angel Pons
2020-10-17	intel/txt: Add `txt_get_chipset_dpr` function	Angel Pons
2020-10-15	nb/intel/haswell: Account for DPR region in memory map	Angel Pons
2020-09-02	{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-05	src/northbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2020-03-15	nb/intel/haswell: Tidy up code and comments	Angel Pons
2019-11-01	lib/cbmem_top: Add a common cbmem_top implementation	Arthur Heymans
2019-10-21	src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'	Elyes HAOUAS
2019-08-28	intel/haswell: Use smm_subregion()	Kyösti Mälkki
2019-08-26	soc/intel: Use common romstage code	Kyösti Mälkki
2019-08-22	arch/x86: Add <arch/romstage.h>	Kyösti Mälkki
2019-08-15	arch/x86: Add postcar_frame_common_mtrrs()	Kyösti Mälkki
2019-08-15	cpu/intel: Refactor platform_enter_postcar()	Kyösti Mälkki
2019-08-11	intel/haswell: Move platform_enter_postcar()	Kyösti Mälkki
2019-08-07	northbridge/intel: Rename ram_calc.c to memmap.c	Kyösti Mälkki