coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2015-02-15	x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer	Kevin Paul Herbert
	On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2013-05-22	intel/gm45: Add more debug output to read/write training	Nico Huber
	Add debug output for the timing values of the edges found during read and write training. Now, output for one DIMM of DDR3-1066 in a roda/rk9 looks like: [...] Lower bound for byte lane 0 on channel 0: 0.0 Upper bound for byte lane 0 on channel 0: 8.4 Final timings for byte lane 0 on channel 0: 4.2 Lower bound for byte lane 1 on channel 0: 0.0 Upper bound for byte lane 1 on channel 0: 10.2 Final timings for byte lane 1 on channel 0: 5.1 Lower bound for byte lane 2 on channel 0: 0.0 Upper bound for byte lane 2 on channel 0: 7.5 Final timings for byte lane 2 on channel 0: 3.6 Lower bound for byte lane 3 on channel 0: 0.0 Upper bound for byte lane 3 on channel 0: 11.4 Final timings for byte lane 3 on channel 0: 5.6 Lower bound for byte lane 4 on channel 0: 0.0 Upper bound for byte lane 4 on channel 0: 9.4 Final timings for byte lane 4 on channel 0: 4.6 Lower bound for byte lane 5 on channel 0: 0.0 Upper bound for byte lane 5 on channel 0: 11.2 Final timings for byte lane 5 on channel 0: 5.5 Lower bound for byte lane 6 on channel 0: 0.0 Upper bound for byte lane 6 on channel 0: 8.4 Final timings for byte lane 6 on channel 0: 4.2 Lower bound for byte lane 7 on channel 0: 0.0 Upper bound for byte lane 7 on channel 0: 10.4 Final timings for byte lane 7 on channel 0: 5.2 Lower bound for group 0 on channel 0: 1.7.5 Upper bound for group 0 on channel 0: 2.2.2 Final timings for group 0 on channel 0: 1.10.7 Lower bound for group 1 on channel 0: 1.6.1 Upper bound for group 1 on channel 0: 2.0.2 Final timings for group 1 on channel 0: 1.9.1 Lower bound for group 2 on channel 0: 2.0.7 Upper bound for group 2 on channel 0: 2.8.1 Final timings for group 2 on channel 0: 2.4.4 Lower bound for group 3 on channel 0: 2.4.7 Upper bound for group 3 on channel 0: 3.0.0 Final timings for group 3 on channel 0: 2.8.3 [...] Final timings are always the average of the two bounds. The last dots separate eights (not decimals) and the middles are elenvenths or twelfths depending on the clock speed (twelfths in this case). Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3257 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22	intel/gm45: Handle overflows during DDR3 write training	Nico Huber
	We halted the machine on any overflow during the write training. However, overflows during the search for a good to bad edge are non-fatal, and should be ignored. Change-Id: I45ccbabc214e208974039246d806b0d2ca2fdc03 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3256 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22	intel/gm45: Refactor DDR3 write training	Nico Huber
	Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3255 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22	intel/gm45: Handle overflows during DDR3 read training	Nico Huber
	We halted the machine on any overflow during the read training. However, overflows during the search for a good to bad edge are non-fatal, and should be ignored. Change-Id: I77085840ade25bce955480689c84603334113d1f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3254 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22	intel/gm45: Refactor DDR3 read training	Nico Huber
	Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Ied551a011eaf22f6f8f6db0044de3634134f0b37 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3253 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
	In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' \| xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-27	intel/gm45: new northbridge	Patrick Georgi
	The code supports DDR3 boards only. RAM init for DDR2 is sufficiently different that it requires separate code, and we have no boards to test that. Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>