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2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-14nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xceElyes HAOUAS
Change-Id: Ifb8aa43b6545482bc7fc136a90c4bbaa18d46089 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22957 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30nb/intel/fsp_rangeley: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I0b969a5109276d108e6140bad338c74786b967f3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-27nb/intel/fsp_rangeley/port_access.c: Add brackets around macroElyes HAOUAS
Code checked manually Change-Id: Idf86546ddda4fa2b4b96f0b703c03af9931c757d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-25lib: provide clearer devicetree semanticsAaron Durbin
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-18intel/fsp_rangeley: Fix use of __SIMPLE_DEVICE__Kyösti Mälkki
Required fix to have rules.h as default include. Change-Id: I6ce2d4e13de5139a84c709b5836ecd41c0abc836 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17747 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-07MMCONF_SUPPORT: Consolidate resource registrationKyösti Mälkki
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel/fsp_rangeley: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Boards with this chipset do not have any reference of MMCONF_BASE_ADDRESS being written to chipset registers. Either board support is already broken or FSP takes care of this early and Kconfig lacks the notice that this parameter must match with the chosen FSP binary. CPU bootblock associated with this chipset uses exclusive PCI IO access already. Untested. Change-Id: I07d20d81266ff6aaa6384d20a806d52fd4568e08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17547 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30intel/fsp_rangeley: Fix regression on MMCONF_SUPPORTKyösti Mälkki
Following commit did not move this selection to northbridge: bac0fad Remove explicit select MMCONF_SUPPORT Change-Id: I5f3c429dfd160eb439f396db2baf0ecf280022fd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17653 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-20northbridge/intel/fsp_rangeley: Add space around operatorsElyes HAOUAS
Change-Id: Ia60729db83333c1159862cf604de321e3af8dcb1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-09northbridge/intel/fsp_rangeley: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/fsp_rangeley. Change-Id: I4c1e6af64fe70211db2fafdba9f39182dfea66fc Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16470 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/intel: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I53208ce5db06d2c65f954e6d59222924ab87722e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16304 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
This just updates existing guard name comments on the header files to match the actual #define name. As a side effect, if there was no newline at the end of these files, one was added. Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-23Intel: Move MCRS ResourceTemplate outside of _CRS methodMartin Roth
On Broadwell, this reduces the number of 'remarks' in the IASL build from 222 to 3. Fixes these remarks: Object is not referenced (Name is within method [_CRS]) The ACPI compiler is trying to be helpful in letting us know that we're not using various fields in the MCRS ResourceTemplate when we define it inside of the _CRS method. Since we're not intending to use those objects in the method, it shouldn't be an issue, but the warning is annoying and can mask real issues. Moving the creation of the MCRS object to outside of the CRS method and referencing it from there solves this problem. This change was made for fsp_baytrail in commit 2eaa0d49 fsp_baytrail: Fix ACPI 'Object is not referenced' warnings Change-Id: I67a1faf963d1868f4133c7747a43a511cd28a44b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11268 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
This chip is still being used and should not have been deleted. It's a current intel chip, and doesn't even require an ME binary. This reverts commit 959478a763c16688d43752adbae2c76e7764da45. Change-Id: I78594871f87af6e882a245077b59727e15f8021a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11860 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
mohonpeak is the reference board for Rangeley. I doubt anyone uses it or cares about it. We jokingly refer to it as "Moron Peak". It's code with no known users, so we shouldn't be hauling it around for the eventuality that someone might use it in the future. Change-Id: Id3c9fc39e1b98707d96a95f2a914de6bbb31c615 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11790 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-07-13x86: flatten hierarchyStefan Reinauer
It never made sense to have bootblock_* in init, but pirq_routing.c in boot, and some ld scripts on the main level while others live in subdirectories. This patch flattens the directory hierarchy and makes x86 more similar to the other architectures. Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10901 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-06-05device_ops: add device_t argument to acpi_fill_ssdt_generatorAlexander Couzens
`device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-26acpi: Remove monolithic ACPIVladimir Serbinenko
All boards now use per-device ACPI. This patch finishes migration by removing transitional kludges. Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7372 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-20acpi: make fill_slit and fill_srat into arguments.Vladimir Serbinenko
SLIT and SRAT are created this way only on amdk8 and amdfam10. This saves the need of having a lot of dummies. Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7052 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-01northbridge/intel/fsp_rangeley: Correct MMIO size settingDave Frodin
The Rangeley chipset has the MMIO PCI config space feature enabled at 0xe0000000-0xefffffff. This is a 256MB space which covers all of config space. The ACPI table for this space only defines it as being 64MB. This change fixes that setting. Change-Id: I8205a9b89ea6633ac6c4b0d5a282cd2745595b2e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/10047 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-05-01intel: Correct MMIO related ACPI table settingsDave Frodin
Several of the intel platforms define the region reserved for PCI memory resources in a location where it overlaps with the MMIO (MCFG) region. Using the memory map from mohon_peak as an example: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007fbcffff: RAM 4. 000000007fbd0000-000000007fbfffff: CONFIGURATION TABLES 5. 000000007fc00000-000000007fdfffff: RESERVED 6. 00000000e0000000-00000000efffffff: RESERVED 7. 00000000fee00000-00000000fee00fff: RESERVED 8. 0000000100000000-000000017fffffff: RAM The ACPI table describing the space set aside for PCI memory (not to be confused with the MMIO config space) is defined as the region from BMBOUND (the top of DRAM below 4GB) to a hardcoded value of 0xfebfffff. That region would overlap the MMIO region at 0xe0000000-0xefffffff. For rangeley the upper bound of the PCI memory space should be set to 0xe0000000 - 1. The MCFG regions for several of the affected chipsets are: rangeley 0xe0000000-0xefffffff baytrail 0xe0000000-0xefffffff haswell 0xf0000000-0xf3ffffff sandybridge 0xf8000000-0xfbffffff TEST = intel/mohonpeak and intel/bayleybay. Change-Id: Ic188a4f575494f04930dea4d0aaaeaad95df9f90 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/9972 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-04-29kbuild: automatically include northbridgesStefan Reinauer
This change switches all northbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in northbridge/Makefile.inc or in northbridge/<vendor>/Makefile.inc. This means, vendor and northbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I8468154dbfaaaffcba9fda27ba2d7b9049ad5c19 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9800 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28fsp platforms: consolidate FspNotify callsMartin Roth
Consolidate the FspNotify calls into the FSP driver directory, using BOOT_STATE_INIT_ENTRY to set up the call times. Change-Id: I184ab234ebb9dcdeb8eece1537c12d03f227c25e Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/9780 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-24fsp: Move fsp to fsp1_0Marc Jones
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific directory. See follow-on patches for sharing of common code. Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-02-13Fix source code permissionsStefan Reinauer
Two source files were accidently marked executable. Switch them back to mode 644 (rw-r---r--) Change-Id: Ic96f6e5e9a05cbffb65cdfb627023d04d3866dc9 Signed-off-by: Stefan Reinauer <stepan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8426 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-06intel/fsp_rangeley: Indent '#define' consistentlyYork Yang
The indentations of #define are not consistent in chip.h. Update to make all #define indentations being aligned and put them after the variable declaration. Change-Id: I37550acac18bac3efddb580ef6b956be0e2b357a Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/8333 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
2015-02-06FSP & CBMEM: Fix broken cbmem CAR transition.Martin Roth
1) Save the pointer to the FSP HOB list to low memory at address 0x614. This is the same location as CBMEM_RESUME_BACKUP - the two aren't used in the same platform, so overlapping should be OK. I didn't see any documentation that actually said that this location was free to use, and didn't need to be restored after use in S3 resume, but it looks like the DOS boot vector gets loaded juat above this location, so it SHOULD be ok. The alternative is to copy the memory out and store it in cbmem until we're ready to restore it. 2) When a request for the pointer to a CAR variable comes in, pass back the location inside the FSP hob structure. 3) Skip the memcopy of the CAR Data. The CAR variables do not get transitioned back into cbmem, but used out of the HOB structure. 4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform. Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8196 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSPYork Yang
Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. When needed, it can be customized by BCT tool for tracking BCT configurations. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/8107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7888 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-06northbridge/intel: Do not define include guard as 1Edward O'Callaghan
As `#ifndef` and not `#if` is used in the check for include guards, setting it to 1 is not needed. Change-Id: Iaa6c0f807b9e99ad3c9551abe4ab1627e5505d67 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8103 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-12-05drivers/intel/fsp: add upd macros and #definesMartin Roth
Add macros and #defines for working with the UPD data. This makes the code look much cleaner. Remove the UPD_ENABLE / UPD_DISABLE from fsp_rangeley/chip.h and include the fsp_values header instead. This fixes a conflict. Change-Id: I72c9556065e5c7461432a4593b75da2c8a220a12 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7487 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-20Replace includes of build.h with version.hKyösti Mälkki
As build.h is an auto-generated file it was necessary to add it as an explicit prerequisite in the Makefiles. When this was forgotten abuild would sometimes fail with following error: fatal error: build.h: No such file or directory Fix this error by compiling version.c into all stages. Change-Id: I342f341077cc7496aed279b00baaa957aa2af0db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7510 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-08fsp_rangeley: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7046 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-01northbridge/intel: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: I9aeed70f72d4df260312df6e53379f1741415b65 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7287 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
Placement of romstage stack in RAM was vulnerable for getting corrupted by decompressed ramstage. Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7096 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-16ACPI: Remove CONFIG_GENERATE_ACPI_TABLESVladimir Serbinenko
As currently many systems would be barely functional without ACPI, always generate ACPI tables if supported. Change-Id: I372dbd03101030c904dab153552a1291f3b63518 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4609 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-07-30northbridge/intel: Add fsp_rangeley northbridge supportMartin Roth
This adds the northbridge initialization pieces for Intel's Atom C2000 processor (Formerly Rangeley). It is intended to be used with the Intel Atom C2000 FSP and does not contain all of the pieces that would otherwise be required for initialization. Not currently supported: S3 suspend/resume CAR memory Migration (No early cbmem console) SMM Change-Id: I7665212c892d9a08ecf35d7be70d0afe5fd2c77b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/6369 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-07 22:36:37 +0000