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2021-05-03nb/intel/common: Replace `_bar_clrsetbits_impl` macroAngel Pons
This macro contains a cast on the and-mask, which can suppress actual type overflow issues. Replace it with wrapper functions around the existing macros in device/mmio.h which still contain a type cast, but it is a non-issue because the wrapper functions now allow compilers to check for overflows. Change-Id: I975bf8152fc961767f0292bff4a03aecd8c65f56 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51886 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03nb/intel/common: Drop deprecated fixed BAR accessorsAngel Pons
Now that all code has been switched to make use of the new accessors, the old ones can be dropped. Follow-ups will clean up bitwise accessors. Change-Id: Ib4cb24ca71f3c3717ea50d147ddca74aaf0288fa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-02nb/intel/common: Turn `*bar_{read,write}*` macros into functionsAngel Pons
These accessors were defined as macros in order to allow verifying the patches that replaced the accessors using BUILD_TIMELESS=1. Now that all replacement is done, turn the new accessors into static functions to let the compiler perform overflow checks on the arguments. Change-Id: Iaa2ba208fba11c4a00f2b8a05eb1129a32c6c092 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52816 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/common/fixed_bars.h: Add new read/write accessorsAngel Pons
The {MCH,DMI,EP}BAR macros can be used for both reading and writing. While this can sometimes be useful, compile-time overflow checking is limited. Moreover, and-masks need to be bit-wise negated, which is easy to forget and may result in spurious overflow warnings, and silencing them with a cast also suppresses true integer overflow issues. To address these limitations and for consistency with the existing MMIO API (arch/mmio.h and device/mmio.h), these macros will be replaced with prefixed wrappers around MMIO API functions. However, existing platform code needs to be refactored, and the risk of introducing regressions is substantial. To minimize the risk of breakage, the bulk of the platform code changes will be verified using reproducible builds. This patch introduces the new accessors, to be put to use in follow-ups. These accessors are implemented as macros so that subsequent commits can be verified using reproducible builds. They will be replaced with actual functions after refactoring all platforms. Change-Id: I85376a9e2f6cd042b41036f90de7f9edc7ad4508 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51864 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel: Factor out remaining MCHBAR macrosAngel Pons
Except for some formatting differences, the macros are equivalent. Change-Id: I5dc4f115b0873fb96683263ecd152d3d1504647d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51863 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12nb/intel/common/fixed_bars.h: Add casts to `uintptr_t`Angel Pons
64-bit builds need this, as the Kconfig values fit in a 32-bit integer. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I570374f92394f839a97e28fabc8fa07a7e673e83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-07nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessorsAngel Pons
These accessors can be reused for several other northbridges. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18nb/common/intel: Remove the mrc cache codeArthur Heymans
This is now unused, since all intel northbridges now use the equivalent in drivers/mrc_cache. Change-Id: I3e4b4afa53acc0a82b4ba961f13f816b04931fea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23485 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-05nb/intel/common: Write MRC cache at exit of BS_DEV_INITNico Huber
We set the SPI lockdown in BS_POST_DEVICE (dev_finalize()) on many plat- forms now. The SPI controller is initialized at start of BS_DEV_INIT (dev_initialize()). The SPI lockdown usually shouldn't be a problem but the SPI driver imple- mentation lacks full support for the locked interface. Also, some options exist to lock all flash regions read-only until the next reboot. Change-Id: Ifda826ae2bb28adcce8dda8e2bb16dc38fe0fe9e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bill XIE <persmule@gmail.com>
2017-08-11drivers/intel/gma/opregion: migrate from nb/commonMatt DeVillier
Migrate opregion code from northbridge/intel/common to drivers/intel/gma in preparation for consolidation with soc/intel/common opregion code. Rename init_igd_opregion() for clarity and disambiguation with other implementations. Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12nb/intel/common/gma_opregion: Use new method to update ASLSPatrick Rudolph
Use new GMA driver method to set ASLS. Change-Id: I872ff86a778497df76ad7f9b1b6910c4e7c5941f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09nb/intel/common: Create a common init_igd_opregion methodPatrick Rudolph
Copy Haswell's init_igd_opregion to common folder. Remove platform specific code. Will replace all Intel NB implementations. Change-Id: I14dfb5986df264ffd71183a159f98b79e8e3230e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-05-19drivers/spi/spi_flash: Pass in flash structure to fill in probeFurquan Shaikh
Instead of making all SPI drivers allocate space for a spi_flash structure and fill it in, udpate the API to allow callers to pass in a spi_flash structure that can be filled by the flash drivers as required. This also cleans up the interface so that the callers can maintain and free the space for spi_flash structure as required. BUG=b:38330715 Change-Id: If6f1b403731466525c4690777d9b32ce778eb563 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12nb/intel: Factor out common MRC codePatrick Rudolph
Remove code duplication and use the common function store_current_mrc_cache instead. No functionality is changed. Tested on Sandybridge Lenovo T520. Change-Id: I4aa5463f1b1d5e1afbe44b4bfc659524d86204db Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15074 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
The sourcecode is 99% the same. Only two lines differ, but not in functionality. Also rename mrccache.c -> mrc_cache.c Tested-on: boot + suspend/resume on x220 Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
The mrc_cache definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/13998 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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