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2014-05-22northbridge/amd/amdmct/mct: Initialize variables at the eolEdward O'Callaghan
Spotted by Clang Change-Id: Idada98b7863ef986021943cf3ddb92d2f035e3e1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5816 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-05AGESA: Implement EmptyHeap()Kyösti Mälkki
Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear the fields individually. Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5659 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam14: Use common calloutsKyösti Mälkki
Backported from fam15tn and fam16kb. This also implements GetHeapBase() to satisfy some requirements of HAVE_ACPI_RESUME for the following boards: amd/inagua amd/south_station amd/union_station asrock/e350m1 Change-Id: I488d063d4eabf4bf45bcbabd1e8f13b88b2ef401 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5658 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam14: Add fam14_callouts headerKyösti Mälkki
Backported from fam15tn and fam16kb. Change-Id: I868352b32ff56a8386c615ab1a9f59e7e875292e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5657 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Add GetHeapBase()Kyösti Mälkki
While fam15 boards do not select HAVE_ACPI_RESUME, backport this from fam14. Implementation of this function is common across different families. Change-Id: I222b418a0a79bbdf5f5cce6c876243ecb4912256 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5655 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam12: Add GetHeapBase()Kyösti Mälkki
While amd/torpedo does not select HAVE_ACPI_RESUME, backport this from fam14. Implementation of this function is common across different families. Change-Id: I0e5099a0991a2655ec2b6990929196900e842fc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5654 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15tn: Use common GetHeapBase()Kyösti Mälkki
Implementation of this function is common for all boards in family, and also across different families. Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam16kb: Use common GetHeapBase()Kyösti Mälkki
Implementation of this function is common for all boards in family, and also across different families. Change-Id: I6aab710e76af9a361f0c0006922019a52feb3f6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Use common calloutsKyösti Mälkki
Backport from fam15tn and fam16kb. Change-Id: I6d8f9a88f0dc43c36efb168c0111a6e2bcdda5fd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Add fam15_callouts headerKyösti Mälkki
Backported from fam15tn and fam16kb. Change-Id: I13ca70d141a46220a5d8ea7bb3898bc7d7258424 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam12: Move dimmSpdKyösti Mälkki
Implemented under northbridge/ on other families. Change-Id: I4d21af9d6c0f61eb1597e8e7095c08dd87ae2a84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam12: Add fam12_calloutsKyösti Mälkki
Although amd/torpedo is only fam12 board at the moment, backported this from fam15tn and fam16kb. Change-Id: I72a856e2eb455a8428a886f0c4217ff80e60eb78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03AMD: Drop redundant test for CONFIG_RAMTOPKyösti Mälkki
Same test is already done in x86/mtrr.h. Change-Id: Ib0785d047567374294b9ee7afc4f4244f9ced926 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5620 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26Rename coreboot_ram stage to ramstageFurquan Shaikh
Rename coreboot_ram stage to ramstage. This is done in order to provide consistency with other stage names (bootblock, romstage) and to allow any Makefile rule generalization, required for patches to be submitted later. Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-16AMD AGESA fam15tn/fam16kb: Remove unused source filesKyösti Mälkki
Change-Id: I45084ffe84fef4dd43acea843d7c93a81c255472 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5523 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-02-13Eliminate some ASL warningsOskar Enoksson
The ASL compiler warned about "Control Method should be made Serialized (due to creation of named objects within)". This commit eliminates the warnings by changing those NonSerialized into Serialized. Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5189 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-28x86: add common definitions for control registersAaron Durbin
The access to control registers were scattered about. Provide a single header file to provide the correct access function and definitions. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted using this infrastructure. Also objdump'd the assembly to ensure consistency (objdump -d -r -S | grep xmm). Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172641 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4873 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-13lib: Make log2() available in romstage on ARM, not just x86Alexandru Gagniuc
On x86, log2() is defined as an inline function in arch/io.h. This is a remnant of ROMCC, and forced us to not include clog2.c in romstage. As a result, romstage on ARM has no log2(). Use the inline log2 only with ROMCC, but otherwise, use the one in clog2.c. Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4681 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-12lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4659 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-10Replace all occurences of sprintf with snprintfVladimir Serbinenko
THis reduces risks of bufer overflows. Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4279 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-30AMD K8 (rev F): Move rev F0/F1 workaround to headerKyösti Mälkki
Place this in header so it works also when raminit_f.c and raminit_f_dqs.c are not #included in romstage.c build. The workaround remains to be disabled for all boards. Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4568 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridgeKyösti Mälkki
Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all K8 rev F boards do the same things here. Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORTKyösti Mälkki
Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4558 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29AMD K8 (rev-F): Always have RAMINIT_SYSINFOKyösti Mälkki
K8 Rev F raminit code cannot be built without RAMINIT_SYSINFO, so have the option enabled together with K8_REV_F_SUPPORT. Also move the option under AMD K8. Change-Id: I91fa0b4ae7e3e54fbcb4a4f91eb043956cd0fb60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29AMD K8: Socket implies K8_REV_F_SUPPORTKyösti Mälkki
K8_REV_F_SUPPORT is already set by all affected sockets, (AM2, F, S1G1). Change-Id: If42a4178263d90a4e195fae0c78943ac9eda1ad6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4557 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26AMD fam10: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4555 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4523 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-23Coding style: punctuation cleanup [1/2].Idwer Vollering
Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4562 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-02global: Fix usage of get_option() to make use of CB_CMOS_ codesAlexandru Gagniuc
Do not directly check the return value of get_option, but instead compare the returned value against a CB_CMOS_ error code, or against CB_SUCCESS. Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4266 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-26AMD Northbridge LX: simplify get_top_of_ram()Christian Gmeiner
Get rid of not needed dependency to gliu0table. This change is needed to move get_top_of_ram() to raminit.c - as needed for EARLY_CBMEM_INIT. Boot tested on a Bachmann OT200. Change-Id: I0bfe40c366a3537775d5c1ff8e0b1f5ac94320b7 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3380 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-10-13northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in ↵Paul Menzel
`setup_mtrr_dqs()` Change-Id: I7fc7819c329c058472031e82237be5c170b277f4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3965 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-13Rename cpu/x86/car.h to arch/early_variables.hStefan Reinauer
and add an ARMv7 version. Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156 Signed-off-by: Stefan Reinauer <reinauer@google.com> [km: rebased fa004acf8 from chromium git] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3939 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-09-24southbridge/cimx/sb900: Rename headers to match sb700 & sb800Corey Osgood
Northbridge code includes these headers, so they all need to have the same name to allow different combinations of northbridge and southbridge. This changes the sb900 names to match sb700 & sb800, and points agesa/family12 and amd/torpedo to the new file names. Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Reviewed-on: http://review.coreboot.org/3825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-11CBMEM: Unify get_top_of_ram()Kyösti Mälkki
Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3904 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM northbridges: Remove references to global high_tables_baseKyösti Mälkki
Use the new helper function set_top_of_ram() to remove remaining uses of high_tables_base and _size under northbridge/. Change-Id: I6b0d9615002ed2aff578c5811d7bd43dd2594453 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3561 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM AMD: Fix calls to set_top_of_ram_once()Kyösti Mälkki
We can postpone the call to set_top_of_ram_once() outside the loops and make just one call instead. As set_top_of_ram() is now only called once, it is no longer necessary to check if high_tables_base was already set. Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-11CBMEM AMD: Remove references to global high_tables_baseKyösti Mälkki
Prepare for removal of globals high_tables_base and _size by replacing the references with a helper function. Added set_top_of_ram_once() may be called several times, but only the first call (with non-zero argument) takes effect. Change-Id: I5b5f71630f03b6a01e9c8ff96cb78e9da03e5cc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-15AMD Richland: Add new graphics device IDs to Family 15, Models 10-1FBruce Griffith
Change-Id: Ic7fdedc0a22e7664f14b105f2f7cecd8f55980be Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3857 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-15AMD Kabini: Split DSDT into common sectionsMike Loptien
Split the Family16 (Kabini) DSDT file into logical regions. Olive Hill is the only mainboard and Kabini is the only NB/CPU currently using Family16 AGESA code. Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3821 Tested-by: build bot (Jenkins)
2013-08-08ASUS F2A85-M: Split DSDT into common sections (as per Parmer)Kimarie Hoot
Rearranged the F2A85-M DSDT file to match the functionality found on Parmer. As with the Parmer implementation, the F2A85-M dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. As with Parmer, some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for F2A85-M. Change-Id: Ic72cb6004538ca9d9f79826b9b3c8d6aeb25017c Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/3805 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-05AMD Kabini: Add map_oprom() function for Vendor/Device IDsBruce Griffith
Change-Id: I14285f0677003fbf8b9b112207af202658807894 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3806 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Kabini: Add northbridge AGESA wrapper (new AMD processor)Siyuan Wang
src/arch/x86/boot/tables.c and src/include/device/pci_ids.h are also changed because these two files depend on F16kb northbridge macros Change-Id: Iedc842f0b230826675703fc78ed8001a978319c5 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-07-16AMD Fam15tn: Split DSDT into common sectionsSteve Goodrich
Split the Parmer, Family 15tn, and Hudson DSDT into groups. This splits the DSDT table into includable ASL files which carry details specific to the Family 15tn APU, the Parmer platform, and the Hudson FCH. The dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. Initially, this split was done by moving each piece of functionality into its own file (e.g. IRQ routing and mapping, processor tree, sleep states and sleep methods, etc.) and those pieces were #included in dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d) with the extant version of the table. Once the new tables were found to exactly match the existing tables, the pieces were rearranged into reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.). Some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl, sata.asl, etc.). Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710 Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-on: http://review.coreboot.org/3629 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-11Set PCI bus operations at buildtime for ramstageKyösti Mälkki
PCI bus operations are static through the ramstage, and should be initialized from the very beginning. For all the replaced instances, there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for the northbridge, so these continue to use PCI IO config access. Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Fix MMCONF_SUPPORT_DEFAULT for ramstageKyösti Mälkki
Define at one place whether to use IO 0xcf8/0xcfc or MMIO via MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage. The implementation of pci_default_config() always returned with pci_cf8_conf1. This means any PCI configuration access that did not target bus 0 used PCI IO config operations, if PCI MMIO config was not explicitly requested. Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3606 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-28amd/cimx/rd890/amd.h: Eliminate redefinition of NULLBruce Griffith
This change replaces a redefinition of NULL with the standard definition from <stddef.h> to eliminate a compiler redefinition warning. Change-Id: I441fa569f545c0efb00284b5ee58aa27cb6617ba Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3540 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28amd/agesa/family15/northbridge.c: Delete unused variableBruce Griffith
This change eliminates an unused variable that causes a build warning. Change-Id: I02487c7dd80d458f562d7afe1827eefcc0fb678b Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3526 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-24AMD: Drop empty root_complexKyösti Mälkki
There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-24AMD Fam15tn: Add support for AGESA runtime allocation in CBMEMRudolf Marek
The IOMMU AGESA needs a reserved scratch space and it wants to allocate the stuff for runtime. So provide a simple allocator for 4 KB CBMEM page. Change-Id: I53bdfcd2cd69f84fbfbc6edea53a051f516c05cc Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/3315 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24AMD Fam15tn: Add IOMMU BAR allocation to northbridgeRudolf Marek
For IOMMU we need to allocate a 512 KB BAR in a non-standard location. Use the standard allocator for that and limit the BAR to 32-bits to be compatible with older systems. Change-Id: I44414ce6b264b7f1c086a9b1c7ea275a0830205e Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3314 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-13AMD: Kconfig cleanupKyösti Mälkki
Change-Id: I21182eae1d389790c330f27e6a830d91c3ee4eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3433 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-04AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"Christian Gmeiner
Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: convert spd_read_byte() to non-static versionChristian Gmeiner
Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3369 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: rename get_systop() to get_top_of_ram()Christian Gmeiner
Change-Id: I6126d575b8289f76b38858304836e3037200bcdb Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3367 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: include northbridge.h in raminit.cChristian Gmeiner
Change-Id: Ic2f50ae184678637c611757d3391826c1d2719a1 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3365 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-staticChristian Gmeiner
Change-Id: Id914be1ae4dac96c51f2640f056af4ce58a248eb Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3364 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: add some missing includesChristian Gmeiner
This commit fixes problems if we build raminit.c for romstage. Change-Id: Ic1380f3635ac28b939fa2a8ce614814012455c44 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3363 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: make sdram_* function prototypes non-staticChristian Gmeiner
In order to get rid of the bad #include "northbridge/amd/lx/raminit.c" line we need to do some prepartion steps. This commit is one of them. Change-Id: I33173660bbda8894e7672e41e1b994d254d7ae8a Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3362 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Fam 15tn: Use all memory on systems with more than 4 GBSiyuan Wang
Take a Parmer board with 4G memory as an example. Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'. Parmer uses 512M as video memory when it has 4G. 3327540+512*1024 = 3851828(kB), so some memory is lost. When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is 0x00000001. But in e820 table or coreboot table, the last item is 6: 0000000100000000 - 0000000118000000 = 1 RAM This is not correct, it should be 6: 0000000100000000 - 000000011f000000 = 1 RAM This patch changes the memory layout when TOM2 is set. Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3366 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03northbridge/amd/amdmct: Use `static const` instead of `const static`Paul Menzel
From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. The following command was used to make the change. $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/' As asked by Bruce Griffith, the changes in `src/vendorcode` were reverted as that is what AMD prefers. The same change was done already for AMD Persimmon in the following commit. commit 824e192809e021b3cdee947a44b3a18d276bdb35 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 Persimmon: platform_cfg.h: Declare codec arrays as `static const` Reviewed-on: http://review.coreboot.org/2474 Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3197 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-05-10Get rid of a number of __GNUC__ checksStefan Reinauer
In the process of streamlining coreboot code and getting rid of unneeded ifdefs, drop a number of unneeded checks for the GNU C compiler. This also cleans up x86emu/types.h significantly by dropping all the duplicate types in there. Change-Id: I0bf289e149ed02e5170751c101adc335b849a410 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3226 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-08Drop CONFIG_AP_CODE_IN_CARStefan Reinauer
This option has not been enabled on any board and was considered obsolete last time it was touched. If we need the functionality, let's fix this in a generic way instead of a K8 specific way. This was mostly a speedup hack back in the day. Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3211 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-12Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"Nico Huber
This reverts commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5: commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5 Author: Patrick Georgi <patrick.georgi@secunet.com> Date: Tue Apr 9 15:41:23 2013 +0200 siemens/sitemp_g1p1: Make ACPI report the right mmconf region ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> It sneaked in without it's dependencies and, therefore, broke the build for all amdk8 targets. Paul Menzel already commented on the issue in [1]. It also doesn't look like the dependencies would be pulled soon [2]. [1] http://review.coreboot.org/#/c/3047/ [2] http://review.coreboot.org/#/c/2662/ Change-Id: Ica89563aae4af3f0f35cacfe37fb608782329523 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3063 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-04-11Persimmon/Fam14/SB800 DSDT: Split into common areasMike Loptien
Split the Persimmon DSDT into common code areas. For example, split the Southbridge specific code into the Southbridge directory and CPU specific code into the CPU directory. Also adding the superio.asl file to the Persimmon DSDT tree. This file is empty for the moment but will be necessary in the future. I have also emptied the thermal.asl file in the mainboard directory because it does not seem to perform as intended (fan control does not change when it is brought back into the code base) and it has been inside a '#if 0' statement for a long time. Removing it until it is decided that it is actually necessary. This change was verified in three different ways: 1. Visual comparison of the compiled DSDT pulled from the Persimmon after booting into Linux using the ACPI tools acpidump, acpixtract, and iasl. The comparison was done between the DSDT before and after doing the split work. This test is somewhat difficult considering the expanse of the changes. Blocks of code have been moved, and others changed. 2. Linux logs were dumped before and after the DSDT split. Logs dumped and compared include dmesg and lspci -tv. Neither log changed significantly between the two compare points. 3. The test suite FWTS was run on the Coreboot build both before and after doing the DSDT split with the command 'sudo fwts -b -P -u'. The flag -b specifies all batch jobs, -P specifies all power tests, and -u specifies utilities. Interactive jobs were not run as most of them consist of laptop checks. Again, there were no significant changes between the two endpoints. These tests lead me to believe that there was no change in the functionality of the ACPI tables apart from what is known and expected. This patch is the first of a series of patches to split the DSDT. The ASRock patch was merged before this one and breaks the ASROCK E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/). Please be aware of this dependency when pulling these patches. Other patches that depend on this patch are 'AMD Fam14: Split out the AMD Fam14 DSDT' (http://review.coreboot.org/#/c/3051/) and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC' (http://review.coreboot.org/#/c/3052/) Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-10siemens/sitemp_g1p1: Make ACPI report the right mmconf regionPatrick Georgi
ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-04AMD GX1: Remove useless copied header file `northbridge.h`Paul Menzel
This was there since the beginning commit d24d6993b6d7bcf7977d74d081e718e1b076d1b0 Author: arch import user (historical) <svn@openbios.org> Date: Wed Jul 6 17:06:46 2005 +0000 Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26 Creator: Hamish Guthrie <hamish@prodigi.ch> Added AMD GX1 northbridge and cs5530 Southbridge but blindly copied from Intel 440 BX and is not used anywhere. Thanks to Idwer Vollering for spotting this. Change-Id: I38b3d3feb25966c3aa382994d323e59c3f3c9e6c Reported-by: Idwer Vollering Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3020 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19AMD Fam15: Add SPD read functions to wrapper codeKimarie Hoot
Change: This is the initial step for moving the AMD F15 & HUDSON1,2,3 SPD-read callout out of the mainboard directories and into the wrapper. The next step is to update the platforms to use this routine in BiosCallouts.c and to delete the code from the mainboard directories. The DIMM addresses should be moved into devicetree.cb. If there are significant differences or reasons that the mainboard needs to override this code, it's perfectly reasonable to keep using the version in the mainboard, but this allows us to remove duplicated code and simplify the mainboard directories. Notes: This started by duplicating what was in Dinar, and was changed to use the devicetree.cb structures. Significant cleanup and magic number reduction was done as well. It is intended that this file will not be included in ramstage as the DIMM init is all done in romstage. This is similar to what was done for Parmer/Thatcher in commit 7fb692bd - http://review.coreboot.org/#/c/2190/ Fam15tn: Move SPD read from mainboards into wrapper Yes, it would make sense to split this into two separate files and move the SMBus initialization and access into the southbridge wrapper. Maybe that can come next. Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2777 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07AMD Fam14: Add SPD read functions to wrapper codeMartin Roth
Change: This is the initial step for moving the AMD F14 & HUDSON1,2,3 SPD-read callout out of the mainboard directories and into the wrapper. The next step is to update the platforms to use this routine in BiosCallouts.c and to delete the code from the mainboard directories. The DIMM addresses should be moved into devicetree.cb. If there are significant differences or reasons that the mainboard needs to override this code, it's perfectly reasonable to keep using the version in the mainboard, but this allows us to remove duplicated code and simplify the mainboard directories. Notes: This started by duplicating what was in Persimmon, and was changed to use the devicetree.cb structures. The ASF setup was also removed from the persimmon copy (PMIO writes to 0x28 & 0x29) as that's not needed for the SPD access and doesn't make sense to initialize here. Significant cleanup and magic number reduction was done as well. It is intended that this file will not be included in ramstage as the DIMM init is all done in romstage. This is similar to what was done for Parmer/Thatcher in commit 7fb692bd - http://review.coreboot.org/#/c/2190/ Fam15tn: Move SPD read from mainboards into wrapper Yes, it would make sense to split this into two separate files and move the SMBUS initialization and access into the southbridge wrapper. Maybe that can come next. Change-Id: I1e106d3912c160b0015bf02158d9faba4f578ee3 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2497 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-28Drop CONFIG_WRITE_HIGH_TABLESStefan Reinauer
It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-20Whitespace: Replace tab character in license text with two spacesPaul Menzel
For whatever reason tabs got inserted in the license header text. Remove one occurrence of that with the following command [1]. $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,' [1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2460 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-18AMD Family12h: Fix warningsMartin Roth
Add needed prototypes to .h files. Remove unused variables and fix types in printk statements. Add #IFNDEFs around #DEFINEs to keep them from being defined twice. Fix a whole bunch of casts. Fix undefined pre-increment behaviour in a couple of macros. These now match the macros in the F14 tree. Change a value of 0xFF that was getting truncated when being assigned to a 4-bit bitfield to a value of 0x0f. This was tested with the torpedo build. This fixes roughly 132 of the 561 warnings in the coreboot build so I'm not going to list them all. Here is a sample of the warnings fixed: In file included from src/cpu/amd/agesa/family12/model_12_init.c:35:0: src/include/cpu/amd/amdfam12.h:52:5: warning: redundant redeclaration of 'get_initial_apicid' [-Wredundant-decls] In file included from src/cpu/amd/agesa/family12/model_12_init.c:34:0: src/include/cpu/amd/multicore.h:48:5: note: previous declaration of 'get_initial_apicid' was here src/northbridge/amd/agesa/family12/northbridge.c:50:10: warning: no previous prototype for 'get_node_pci' [-Wmissing-prototypes] src/northbridge/amd/agesa/family12/northbridge.c: In function 'get_hw_mem_hole_info': src/northbridge/amd/agesa/family12/northbridge.c:302:13: warning: unused variable 'i' [-Wunused-variable] src/northbridge/amd/agesa/family12/northbridge.c: In function 'domain_set_resources': src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat] src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat] src/northbridge/amd/agesa/family12/northbridge.c:716:1: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat] In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0, from src/northbridge/amd/agesa/family12/northbridge.c:38: src/vendorcode/amd/agesa/f12/AGESA.h:1282:0: warning: "TOP_MEM" redefined [enabled by default] In file included from src/northbridge/amd/agesa/family12/northbridge.c:34:0: src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0, from src/northbridge/amd/agesa/family12/northbridge.c:38: src/vendorcode/amd/agesa/f12/AGESA.h:1283:0: warning: "TOP_MEM2" redefined [enabled by default] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetNumberOfComplexes': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:99:19: warning: operation on 'ComplexList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfPcieEnginesList': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:126:20: warning: operation on 'PciePortList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfDdiEnginesList': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:153:19: warning: operation on 'DdiLinkList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetComplexDescriptorOfSocket': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:225:17: warning: operation on 'ComplexList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c:246:1: warning: no previous prototype for 'PcieFmForceDccRecalibrationCallback' [-Wmissing-prototypes] In file included from src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c:58:0: src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h:120:5: warning: large integer implicitly truncated to unsigned type [-Woverflow] And fixed a boatload of these types of warning: src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress': src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:687:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:694:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:702:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:705:23: warning: assignment makes integer from pointer without a cast [enabled by default] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:709:21: warning: assignment makes integer from pointer without a cast [enabled by default] Change-Id: I97fa0b8edb453eb582e4402c66482ae9f0a8f764 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2348 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-04Add MMCONF resource to AMD fam15 PCI_DOMAINSteven Sherk
This is a port of the following: commit d5c998be99709c92f200b3b08aed2ca3fee2d519 The coreboot resource allocator doesn't respect resources claimed in the APIC_CLUSTER. Move the MMCONF resource to the PCI_DOMAIN to prevent overlap with PCI devices. original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9 Signed-off-by: Marc Jones <marc.jones@se-eng.com> URL - http://review.coreboot.org/#/c/2167/ Change-Id: I6e585d5cf0d46bd58337a6801fb0690ab2dd000c Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/2248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Family 12: Update for string portabilityMike Loptien
Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: I3368a831770df1b8449eb0c97ae4bb24f6678efd Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2250 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Family 15tn: Update for string portabilityMike Loptien
Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: Ib8ab97666340a9481f3ab71f0f347382e964994f Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2251 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Family 10: Update for string portabilityMike Loptien
Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: Idf479980e427bbf0399bdbc15045d80f402f6dbe Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2249 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Family 15: Update for string portabilityMike Loptien
Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: Ie71fec39df5e7703d35d6505dc7d5b55179e2c7e Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2234 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Add MMCONF resource to AMD fam15tn PCI_DOMAINSteven Sherk
In the process of verifying change it was discovered the MMCONF default base address 0xA0000000 was set below mem_top 0xE0000000 and bus number 256 wasn't a relistic number. The Kconfig defaults were changed to mirror fam15 defaults base address 0xF8000000 and bus number 64. Verified changes with boot to OS. This is a port of the following: commit d5c998be99709c92f200b3b08aed2ca3fee2d519 The coreboot resource allocator doesn't respect resources claimed in the APIC_CLUSTER. Move the MMCONF resource to the PCI_DOMAIN to prevent overlap with PCI devices. original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9 Signed-off-by: Marc Jones <marc.jones@se-eng.com URL - http://review.coreboot.org/#/c/2167/ Change-Id: I47660061538f8889f528b9b880a82645074886a7 Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/2260 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-01Fam15tn: Move SPD read from mainboards into wrapperMartin Roth
Continuing with the mainboard cleanup for F15tn, move the functions to read the SPD from the mainboards for Thatcher and Parmer into the wrapper for the northbridge/amd/agesa/family15tn. Move the SPD address customization for the mainboard into the devicetree.cb file. Unrelated side note - Porting.h has an un-closed #pragma pack(1) that can cause confusing side-effects. AGESA's structures all use this, but coreboot's don't. Be sure to include the coreboot .h files BEFORE Porting.h is included, not after. This fix has been tested. Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2190 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
2013-01-30Extend CBFS to support arbitrary ROM source media.Hung-Te Lin
Summary: Isolate CBFS underlying I/O to board/arch-specific implementations as "media stream", to allow loading and booting romstage on non-x86. CBFS functions now all take a new "media source" parameter; use CBFS_DEFAULT_MEDIA if you simply want to load from main firmware. API Changes: cbfs_find => cbfs_get_file. cbfs_find_file => cbfs_get_file_content. cbfs_get_file => cbfs_get_file_content with correct type. CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM, the ROM may come from USB, UART, or SPI -- any serial devices and not available for memory mapping. To support these devices (and allowing CBFS to read from multiple source at the same time), CBFS operations are now virtual-ized into "cbfs_media". To simplify porting existing code, every media source must support both "reading into pre-allocated memory (read)" and "read and return an allocated buffer (map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*" provides simple memory mapping simulation. Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA is defined for CBFS functions to automatically initialize a per-board default media (CBFS will internally calls init_default_cbfs_media). Also revised CBFS function names relying on memory mapped backend (ex, "cbfs_find" => actually loads files). Now we only have two getters: struct cbfs_file *entry = cbfs_get_file(media, name); void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type); Test results: - Verified to work on x86/qemu. - Compiles on ARM, and follow up commit will provide working SPI driver. Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30Rename family15 pci northbridgeops functions.Steven Sherk
This is a port of the following commit 8a49ac7f808f76821e7d63070420cfd98f707c7c Rename fam14 pci northbridge ops functions. Clarify the northbridge ops function names. original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id7889bf02e2696220081251acdf695327267c796 Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/2225 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30Rename family15tn pci northbridgeops functions.Steven Sherk
This is a port of the following commit 8a49ac7f808f76821e7d63070420cfd98f707c7c Rename fam14 pci northbridge ops functions. Clarify the northbridge ops function names. original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icda3ec58219baa177af3b1dce729c6ad1f744be8 Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/2226 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30Family 14: Update for string portability.Mike Loptien
Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: I6327c9769c2544bbc56155a2f89afd767487faf6 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2227 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-22Add MMCONF resource to AMD fam14 PCI_DOMAIN.Marc Jones
The coreboot resource allocator doesn't respect resources claimed in the APIC_CLUSTER. Move the MMCONF resource to the PCI_DOMAIN to prevent overlap with PCI devices. Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/2167 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com>
2013-01-22Rename fam14 pci northbridge ops functions.Marc Jones
Clarify the northbridge ops function names. Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/2166 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-01-22F15tn: Fix all warnings, enable warnings as errorsMartin Roth
Enable 'all warnings being treated as errors' in thatcher and parmer. Fixed the following warnings on parmer / thatcher: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c: In function 'GetGlobalCpuFeatureListAddress': src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c: In function 'SaveDeviceContext': src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c: In function 'GetPstateGatherDataAddressAtPost': src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c: In function 'MemNInitNBDataTN': src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32: warning: assignment from incompatible pointer type [enabled by default] src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23: warning: assignment from incompatible pointer type [enabled by default] src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c: In function 'GetGlobalCpuFeatureListAddress': src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c: In function 'SaveDeviceContext': src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0: src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0: warning: "TOP_MEM" redefined [enabled by default] src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0: warning: "TOP_MEM2" redefined [enabled by default] src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0: src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0: warning: "LOCAL_APIC_ADDR" redefined [enabled by default] src/include/cpu/x86/lapic_def.h:9:0: note: this is the location of the previous definition In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0, from src/mainboard/amd/parmer/mainboard.c:28: src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0: warning: "TOP_MEM" redefined [enabled by default] src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0: warning: "TOP_MEM2" redefined [enabled by default] src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2171 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-21AGESA F15tn: Move callouts into northbridge wrapperMartin Roth
There are currently too many things in the mainboard directories that are really more suited to being in the northbridge / southbridge wrappers. This is a start at moving some of those functions down into the wrappers. Move the bios callback functions into the northbridge/amd/agesa/family15tn directory from the mainboard directories. These can still be overridden by any mainboard just by updating the pointer in the callback table to point to a customized version of the function. Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2169 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21F15tn: Modify devicetree to fix S3 resumeMartin Roth
The way that devicetree.cb was configured for the family 15tn boards was doing... interesting things to the video device initialization. This was causing S3 resume to fail. There is a disconnect between how the devicetree should be configured if there are multiple HT links on the CPU and how it's configured if there's only one HT link. These platforms were set up as if they had multiple HT links, which was causing duplicate instances of devices in the device list. The scan for the IO Hub was removed from the northbridge code which isn't a problem for F15tn devices. Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2160 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-04rd890: clear IO-APIC before setupAladyshev Konstantin
Add function "clear_ioapic" before "setup_ioapic" for RD890 northbridge like it is done for SB700 and SB800 chipsets ("amd/cimx/sb{7,8}00"). No functionality change is noticed. Change-Id: I1fd87692d8bf35c166141c9b7a6a1e748c19a636 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2045 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-07Add function to map vendor/device to generic VBIOS IDsDave Frodin
Change-Id: I4d7c4ec2b91c97eacf96770c150c2b9a61309053 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1982 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1928 Tested-by: build bot (Jenkins)
2012-11-28amdk8/amdfam10: Use CAR_GLOBAL for sysinfoPatrick Georgi
This gets rid of the somewhat unstructured placement of AMD's sysinfo structure in CAR. We used to carve out some CAR space using a Kconfig variable, and then put sysinfo there manually (by "virtue" of pointer magic). Now it's a variable with the CAR_GLOBAL qualifier, and build system magic. For this, the following steps were done (but must happen together since the intermediates won't build): - Add new CAR_GLOBAL sysinfo_car - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR - remove DCACHE_RAM_GLOBAL_VAR_SIZE - from CAR setup (no need to reserve the space) - commented out code (that was commented out for years) - only copy sizeof(sysinfo) into RAM after ram init, where before it copied the whole GLOBAL_VAR area. - from Kconfig Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Get rid of drivers classPatrick Georgi
The use of ramstage.a required the build system to handle some object files in a special way, which were put in the drivers class. These object files didn't provide any symbols that were used directly (but only via linker magic), and so the linker never considered them for inclusion. With ramstage.a gone, we can drop this special class, too. Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-17Drop no-op bootblock.cKyösti Mälkki
Deletes unused file: src/northbridge/amd/agesa/family15tn/bootblock.c Change-Id: Ic29553e008839407755d25bf125d599fa1f6131c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-07AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPUSiyuan Wang
Each G34 socket has two node. Previous lapic algorithm is written for the CPU which has one node per socket. I test the code on h8qgi with 4 family 15 CPUs(8 cores per CPU). The topology is: socket 0 --> Node 0, Node 1 socket 2 --> Node 2, Node 3 socket 1 --> Node 4, Node 5 socket 3 --> Node 6, Node 7 Each node has 4 cores. I change the code according to this topology. Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1659 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07AMD rd890 late.c: Don't enable PCIe ports after PCIe init.Siyuan Wang
PCIE devices are detected and initialized by the AMD PCIe init functions, which is in cimx rd890. The parameters are read from devicetree.cb before PCIe init. Now, all bridges and devices are trained on the device 0.0 enable. After PCIe init, the PCIe ports with devices are on and the PCIe ports without devices are off. so resources may be allocated correctly during the rest of the PCI scan. But if the devicetree was being used to enable/disable devices after initialization, the problems would arise. Take a look at the serial log: do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:04.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 PCI bridge 02.0, 03.0 and 04.0 are not inserted devices, but these bridges are still scanned. This is not correct. Change-Id: I87dac5f062c6926081970ed0c5f26a7e3f447395 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1640 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
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