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Its used for Name and Scope and Processor now. As bonus, it allows to
create a multi name paths too. Like Scope(\ALL.YOUR.BASE).
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Compared to posted patch, there are whitespace fixes
(request by Uwe), and a guard to run the erratum only
on AMD_RB_C2 (request by Marc).
Signed-off-by: Marco Schmidt <mashpb@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Change all printk_raminit to printk_spew.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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them a bit more verbose and hopefully more understandable.
Old messages for my machine with 5 GB:
RAM: 0x00400000 kB
Ram3
[...]
Initializing memory: done
RAM: 0x00500000 kB
New messages:
RAM end at 0x00400000 kB
Adjusting lower RAM end
Lower RAM end at 0x003f0000 kB
Ram3
[...]
Initializing memory: done
Handling memory hole at 0x00300000 (default)
RAM end at 0x00500000 kB
Handling memory mapped above 4 GB
Upper RAM end at 0x00500000 kB
Correcting memory amount mapped below 4 GB
Adjusting lower RAM end
Lower RAM end at 0x00300000 kB
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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code, specifically the difference between pre_f and f code.
The only functional changes are in printk statements. The rest is white space.
1. Remove some #if 0 and #if 1 blocks
2. Remove #if USE_DCACHE_RAM blocks. All K8 boards use CAR.
2. Correct typos (canidate -> candidate)
3. Try to minimize the differences between amdk8_f.h and amdk8_pre_f.h
4. Try to minimize the differences between raminit.c and raminit_f.c
5. Make boards that have rev_f processors include the correct raminit code
There is much more that could be done, but it's a start.
Abuild tested and boot tested on s2892 and serengeti_cheetah.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.
Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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To ease some of my debugging pain on the unichrome, i decided i needed to
move FB size selection into cmos, so i could test a size and then reset it
to the default after loading this value so that the next reboot uses the
(working) default again. This meant implementing set_option in parallel to
get_option.
get_option was then found to have inversed argument ordering (like outb) and
passing char * and then depending on the cmos layout length, which made me
feel quite uncomfortable. Since we either have reserved space (which we
shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go. So all users of
get_option now have their arguments inversed and switched from using ints
to unsigned ints now.
The way get_cmos_value was implemented forced us to not overlap byte and to
have multibyte values be byte aligned. This logic is now adapted to do a
full uint32_t read (when needed) at any offset and any length up to 32, and
the shifting all happens inside an uint32_t as well. set_cmos_value was
implemented similarly. Both routines have been extensively tested in a
quick separate little program as it is not easy to get this stuff right.
build_opt_tbl.c was altered to function correctly within these new
parameters. The enum value retrieval has been changed strol(..., NULL, 10)
to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
now but so that we also interprete hex values correctly. The 32bit limit
gets imposed on all entries not marked reserved, an unused "user_data" field
that appeared in a lot of cmos.layouts has been changed to reserved as well.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Replace $(PWD) with $(CURDIR) in Makefiles. I don't know why
the Solaris version behaves differently, but CURDIR is a safe
choice on gnu make (and we require gnu make already)
- Use tail -1 instead of tail -n1 in a file that already relies on
tail -1 support in another place
- Use tail -1 as alternative to tail -n1 in another place
- Use #define for ulong_t in romcc, as that name is used on Solaris
- Avoid fprinting a null pointer. The standard doesn't mandate that
this is a special case, and Solaris doesn't implement it that way.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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register setting for all FAM10 processors.
This does not include new errata for FAM10 C2.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Vincent Lim (vincent.lim@amd.com)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I didn't try to remove "defined but not used" warnings because there are too
many ifdefs to be sure I wouldn't break something.
For shadowed variable declarations I renamed the inner-most variable.
The one in src/pc80/keyboard.c might need help. I didn't change the
functionality but it looks like a bug.
I boot tested it on s2892 and abuild tested it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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support for it.
The related mainboards don't need to activate it
themselves anymore.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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QRANK_DIMM_SUPPORT in line 2208, which caused the protected code fragment never to be included for compilation.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CPUs. It handles both type of erratas on those CPUs.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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in line with the K10 code.
I was trying to use DDR2 800 (CL6) memory on an m57sli, but booting failed.
Marc Jones found this bug (thanks!), which fixes booting with this specific
memory. For the record, it was Crucial CT2KIT25664AA800.
I put the machine through a few days of use. It also succesfully passed a run
of http://people.redhat.com/dledford/memtest.shtml:
$ ./memtest
TEST_DIR: /tmp
SOURCE_FILE: linux-2.6.29.1.tar.bz2
NR_PASSES: 20
MEGS_PER_COPY: 270
NR_COPIES: 45
PARALLEL: no
COMPRESS_RATIO: 5
COMPRESS_FLAG: j
COMPRESS_PROG: /bin/bzip2
EXTRACT: yes
Creating comparison source...done.
Starting test pass #1: unpacking, comparing, removing, done.
Starting test pass #2: unpacking, comparing, removing, done.
Starting test pass #3: unpacking, comparing, removing, done.
Starting test pass #4: unpacking, comparing, removing, done.
Starting test pass #5: unpacking, comparing, removing, done.
Starting test pass #6: unpacking, comparing, removing, done.
Starting test pass #7: unpacking, comparing, removing, done.
Starting test pass #8: unpacking, comparing, removing, done.
Starting test pass #9: unpacking, comparing, removing, done.
Starting test pass #10: unpacking, comparing, removing, done.
Starting test pass #11: unpacking, comparing, removing, done.
Starting test pass #12: unpacking, comparing, removing, done.
Starting test pass #13: unpacking, comparing, removing, done.
Starting test pass #14: unpacking, comparing, removing, done.
Starting test pass #15: unpacking, comparing, removing, done.
Starting test pass #16: unpacking, comparing, removing, done.
Starting test pass #17: unpacking, comparing, removing, done.
Starting test pass #18: unpacking, comparing, removing, done.
Starting test pass #19: unpacking, comparing, removing, done.
Starting test pass #20: unpacking, comparing, removing, done.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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be used unconditionally, and the names don't hurt.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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memory must be clear with 0s because otherwise the resources of K8 will be
totally messed up.
res = probe_resource(dev, 0x100 + (reg | link));
This is called with dev = NULL and this is no good for probe_resource at all.
The attached patch fixes the potential problems and of course the problem
itself. On one particular place was missing test if the device really exists.
This was copied to fam10 and perhaps the same issue is in v3 (DID NOT check).
The rest of the patch is just very paranoid and do all checkings.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>
--This line, and those below, will be igno
red--
M src/devices/pci_ops.c
M src/northbridge/amd/amdk8/northbridge.c
M src/northbridge/amd/amdfam10/northbridge.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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as "driver" instead of "object" in order to get the init code actually
executed.
This patch fixes up all northbridges that did not do this before.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few
include files and missing prototypes. Also, fix up the Config-abuild.lb files
to properly work for cross compiling.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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changes by file:
src/northbridge/amd/amdk8/northbridge.c:
Add high tables code ala Stefan's code for the i945.
src/southbridge/nvidia/ck804/ck804_lpc.c:
Enable High Precision Event Timers.
Add pm_base for ACPI.
src/southbridge/nvidia/ck804/ck804_fadt.c:
Since fadt is only dependent on the Southbridge, add it here.
src/southbridge/nvidia/ck804/Config.lb:
Compile in ck804_fadt.c
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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whitespace differences between this file and the amdk8_util.asl from
asus/m2v_mxe.
It also enables SLIT filling if you have one, zeroes the unused fields in the
srat_lapic structure, and adds some declarations in acpi.h.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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horribly broken and thus never used by any platform. This needs to get
straightened out so current chipsets drivers can use the full feature set.
Create wrapper functions similar to the io pci config space ones.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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triggered by the AMD 690/SB600 targets.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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table to read. Otherwise you never know what you'll get from the factory BIOS. There are probably more, but these are the ones compiled into the s2895.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Add TOM2 to the K8 DSDT.
Thanks to Rudolf Marek for testing and fixing this patch.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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new AML code generator. Compile-tested on all changed targets. I think it should
work because it works for Asus M2V-MX SE.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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generate run-time ACPI ASL code.
Moreover it demonstrates its use on Asus M2V-MX SE where the SSDT table is
generated by new function k8acpi_write_vars (technically similar to
update_ssdt). But lot of nicer.
x
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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functional changes, only a little bit of (mostly formatting) cleanup to
make merging easier.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Do not allow non-identical DIMMs yet, but prepare the code.
Calculate tCL related settings per DIMM in a dual channel setup. The
check for compatibility will come in a later patch, but since DIMMs
still have to be identical, this does not hurt.
Factor out tRC calculation to prepare for per-DIMM calculation.
Add diagnostic messages to tRC code.
Test booted to FILO, behaviour is identical if you ignore the added
debug messages (which are switched off by default).
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This will allow usage of compatible DIMMS in a dual channel setup
instead of requiring the DIMMS to be identical.
Code impact is minimal because a large chunk of code has been moved into
a separate function with almost no changes.
Tested, yields identical results and identical logs.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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print_* in K8 RAM init does not make sense anymore. Convert almost all
print_* to printk_*. This improves readability a lot and makes the code
shorter.
Reorder the SPD equality checks in the dual channel DIMM compatibility
checking code. This is to make sure that we know if any other mismatches
are present in the DIMM. The new order eases debugging with the old
code.
Add a comment about false negatives in that code. This needs to be
implemented correctly, but that is hard to do in an efficient way.
Check if the DIMMS in a dual channel setup have any compatible CAS
latencies.
Add better comments to explain why wrong-at-first-glance SPD CL walking
code is actually correct.
Fix a few typos.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Trying to read the FIDVID register when the processor does not support FIDVID
control causes a GP Fault. This patch reads the startup FID from a different
MSR. I have verified this patch to work on the dbm690t platform.
Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initialization.
This patch has helped immensely to track down a bug in 690G ncHT init.
It depends on my earlier patch which enables CONFIG_USE_PRINTK_IN_CAR
for all boards using HT. Of course that means ROMCC is not an option
anymore for those boards, but I don't think that's a big problem.
Another way to solve this would be #defining printk_spew to nothing.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Marc says:
ROMCC doesn't make sense for k8 boards.
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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except get_nodes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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due to integer rounding errors. Previously, the formula was:
speed = 2 * (10000/spd_value)
For spd_value=60 this means speed = 2 * 166 = 332, which is less than
333 and coreboot died saying RAM was incompatible. The new formula is:
speed = 20000 / spd_value
For spd_value=60, speed=333, which is fine.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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code to use it. That makes the code more readable and also less
error-prone.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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ChannelB slot. Previously a DIMM could only be populated in ChannelB
if there was a DIMM already in ChannelA. This patch doesn't allow unmatched
DIMMs to be populate in ChannelA and ChannelB. In an A & B configuration
the DIMM must still be matched.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Michael Xie Michael.Xie@amd.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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in a number of places.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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fixes the non-coherent(sb) link running at default speed.
Fix HT event notify to output useful information.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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cleaner, avoid compiler warnings, and matches the AMD example code more closely.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This doesn't save any space for me but it is the right thing to allow GCC to
optimize.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initialize them.
Supports single and split plane systems. Set P0 on all cores for best performance.
All APs will be in hlt(C1).
The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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recomendations.
Changes include the following:
fix > 4GB dqs tests
fix channel interleaving
ecc memory scrub updates
MC tristating updates
debug print changes
fix memory hoisting across nodes -
The DRAM Hole Address Register is set via devx in each node, but the Node
number <-> DRAM Base mapping and the Node number <-> DstNode mapping is
set in Node 0. The memmap is setup on node0 and copied to the other nodes
later. so dev, not devx. The bug was the hole was always being set on the
first node.
Signed-off-by: Marc Jones (marc.jones@amd.com)
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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following mainboard files had identical Geode LX specific print_conf()
implementations:
mainboard/amd/db800/mainboard.c
mainboard/amd/norwich/mainboard.c
mainboard/digitallogic/msm800sev/mainboard.c
mainboard/pcengines/alix1c/mainboard.c
Move print_conf() to northbridge/amd/lx/northbridge.c where it belongs.
Add a copyright notice to mainboard/digitallogic/msm800sev/mainboard.c.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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coherent_ht.c (save one empty line removed) so there's no use
to keep it around.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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iasl now defaults to put created files into the input file's path, not into the
current directory.
This (trivial) patch fixes the behavior for the northbridge specific ASL code.
Further checkins to be expected.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Fix IRQ tables (Thanks to Marc Jones)
Fix IRQ SLOT #
Comment out ram test in early startup.
make the debug print in lx/raminit.c a debug print, not emerg print
Set the default console log level to 3, but leave in the possibility of
running with more info (leave maximum at 11)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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also changes the rdpreamble parameter, which will cause that more then one DIMM will work for 939 motherboard.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is the common style in both Linux as well as in LinuxBIOS.
Self-ack as this is pretty trivial and a similar patch was already acked.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Ethernet yet. The fixes are a board-specific fake spd_read_byte, cleaning up
comments, and just in general customizing for the 1c.
The lxraminit
change fixes a bug (&& used instead of ||), adds some debug prints which were
VERY useful debugging the alix1c, changes fatal error messages from print_debug
to print_emerg, and adds two functions:
banner, which just prints out a string with a banner, and
hcf, which print an emergency message and then pushes null bytes
into the uart forever, just to make sure that no bytes get lost
for any reason.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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rodata.pci_driver" warnings are coming from? We were packing those
structures into a read-only segment, but forgot to mark them const.
Despite its size, this is a fairly trivial patch created by a simple
search/replace
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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days on a function named pll_reset that, on exit, says "Done
cpuRegInit", and which, in turn, made me think it was a lot farther
along that it was.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Without this bugfix, the resource for the PCI/ISA video memory at
0xa0000 - 0xbffff is too big, i.e. it goes up to 0xcffff instead of
just 0xbffff as it should.
Here's the diff from two runs of the tool from
http://www.linuxbios.org/pipermail/linuxbios/2007-June/022449.html
on the MSI MS-7260 (K9N Neo), with and without the bugfix. After applying,
the resource size is correct again.
--- dumpres_lb_pci_vgacard_without_resfix.txt
+++ dumpres_lb_pci_vgacard_with_resfix.txt
@@ -11,7 +11,7 @@
MMIO map: #2 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
MMIO map: #3 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
MMIO map: #4 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
-MMIO map: #5 0x00000a0000 - 0x00000cffff Access: R/W Dstnode:0 DstLink 0
+MMIO map: #5 0x00000a0000 - 0x00000bffff Access: R/W Dstnode:0 DstLink 0
MMIO map: #6 0x00fc000000 - 0x00fd1fffff Access: R/W Dstnode:0 DstLink 0
MMIO map: #7 0x00fd200000 - 0x00fd1fffff Access: R/W Dstnode:0 DstLink 0
MMIO map: #0 0x000000 - 0x003fff Access: R/W ISA VGA Dstnode:0 DstLink 0
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This makes sense on systems with small memories when the VGA feature is
not used (CONFIG_VIDEO_MB = 0 in this case).
On Geode GX1 based systems the following amount of memory should be reserved
when VGA support is enabled:
- 1MiB for VGA and SVGA resolutions
- 2MiB for XGA resolution
- 4MiB for SXGA resolution
Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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For example: in C51/MCP55 or C51/MCP51
Will allow
1. C51 at 0x10 to 0x14, and MCP at 0 to 4
2. C51 at 1 to 4, and MCP at 7 to 0x0a
The reason is c51/mcp51/mcp55 reported unitid is 0x0f (far beyond it
needed), and will prevent us from putting them on bus 0.
Typical values for c51/mcp55 or c51/mcp51:
HT_CHAIN_UNITID_BASE = 0x10 # for C51
HT_CHAIN_END_UNITID_BASE = 0 # for mcp
If only have mcp with c51,
HT_CHAIN_UNITID_BASE = 0 # for MCP
#HT_CHAIN_END_UNITID_BASE = 0 # default value 0x20
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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(trivial)
Please fix this if you can.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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should only shift the mask one bit, not two.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
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romcc code but no longer needed in cache as ram code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
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Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Geode changes.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Geode LX platform, including memory and graphics. (rediffed for whitespace)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Comment out code which currently doesn't compile. Needs fixing later.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
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hypertransport specific updates
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
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Drop a lot of debugging code from northbridge.c
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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dead code and adding a few fixmes.
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* Drop empty file (0 bytes) northbridge/amd/amdk8/cpu_rev.c
and references to it.
* move config option decision to preprocessor instead of code
since config options can not change during runtime
* slightly more verbose output in built_opt_tbl.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
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Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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pmtools packages of upcoming SUSE 10.2, too, so the problem will
go away. (new package installed on linuxbios.org, too)
See also
http://www.linuxbios.org/pipermail/linuxbios/2006-September/015968.html
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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serengeti_cheeatah
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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