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2021-10-22AGESA binaryPI: Use common acpi_fill_madt()Kyösti Mälkki
Change-Id: I01ee0ba99eca6ad4c01848ab133166f8c922684d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-07cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-27nb/amd/pi/00630F01: Remove unused directory and codeAngel Pons
No board uses AMD PI 00630F01, so drop it. And drop a single reference to the now-removed `NORTHBRIDGE_AMD_PI_00630F01` Kconfig option inside the `drivers/amd/agesa/acpi_tables.c` file. Change-Id: Ibc45a4a6041220ed22273c1d41f9b796e1acb901 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54897 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13nb/amd/pi/00730F01: enable RESOURCE_ALLOCATOR_V4Michał Żygowski
TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no-ECC Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0387071748262fdeaa5f4d9a71bb87d4d83241b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52761 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13nb/amd/pi/00730F01/northbridge.c: Report missing resourcesMichał Żygowski
Not all resources were being reported, add them. TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no ECC Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia57ab026218f4aae0a98c2081412c4a9ebb7f57a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52927 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13nb/amd/pi/00730F01: Use generic allocation functions for PCI domainMichał Żygowski
Move the DRAM reporting to read_resoures function before the resources are being set. Use generic PCI domain resource allocation functions to read and set domain resources. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9605f7fad30eb093bddf9bc34e31dea9f5f846ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/53955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-12nb/amd/pi/00730F01: Use generic allocation functions for northbridgeMichał Żygowski
Remove obsolete resource assigning functions. IO and MMIO address registers are currently set by amd_initcpuio to cover whole PCI hole under 4G to MMIO and IO 0x0000-0xFFFF is configured to be routed to southbridge already. Use generic PCI and resource allocation functions wherever possible to set northbridge resources. TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no ECC Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8dd5e40bce513c5ba7f1d42a06e7ab0846666942 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-06nb/amd/{agesa,pi}: Avoid overflows during DRAM calculationMichał Żygowski
Do not use get_dram_base_mask to calculate system DRAM limits. Shift operation around values operating on base and mask were causing overflows and thus incorrect system DRAM limit. Another function returning base and limit in KiB has been developed to avoid data loss. Keep DRAM high base and limit in calculations only for Trinity where the physical CPU address bits is 48. Although it is almost impossible to have a non-zero value there, the platform would have to support nearly 256GB of RAM. TEST=boot PC Engines apu1 2GB, apu2 4GB and apu3 2GB and boot Debian with Linux 4.14 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once. Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27sb,soc/amd: Rename PMOD to PICM in ASLKyösti Mälkki
Use the same variable name as soc/intel to implement a common _PIC method at top-level ASL. Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-28kconfig: remove non-existent sourceJack Rosenthal
src/northbridge/amd/pi/00660F01/Kconfig does not exist. Remove the source statement. Also, no kconfig files under src/soc/intel/common/basecode/. Clean that up. Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-25nb/amd: Deduplicate nb_common.hAngel Pons
Save for the IO_APIC2_ADDR definition, they are equivalent. Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47408 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25device: Drop unused HyperTransport codeAngel Pons
Only two definitions are actually used somewhere, the rest is unused. Change-Id: Iec52d0d47fce6a1ec5455b670824b995a7a34a4c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47407 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/amd/pi: Remove 00660F01 directory & filesMartin Roth
These files are not used by any platform, so remove them. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I75651d2cc53fc5a3cb3233686ad66881d129312d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-21src/northbridge: Drop unneeded empty linesElyes HAOUAS
Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26nb/amd/pi/00730F01/northbridge.c: Add include <types.h>Elyes HAOUAS
BIT(x) needs <types.h>. Change-Id: I20526f20d9528dd1fce20bcae933e04aea3d24f9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-11arch/x86: Drop CBMEM_TOP_BACKUPKyösti Mälkki
Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06src: Use pci_dev_ops_pci where applicableAngel Pons
Change-Id: Ie004a94a49fc8f53c370412bee1c3e7eacbf8beb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-26northbridge/amd: Keep using old resource allocatorFurquan Shaikh
This change selects the old resource allocator RESOURCE_ALLOCATOR_V3 for northbridge/amd chipsets. This is required until the chipsets can be fixed to report the resource requirements correctly before resource allocator runs. Issues identified in the chipset code are captured in the mailing list thread here: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/QWLUXO3V5IR5AS6ARRI722BFVAPOD5TS Change-Id: Iaf873ee76a67482483e410aede653dd8f662e468 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08northbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: Ief2fdedbdba3b7d1708adb2519eb01242e9b52ab Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-07nb/amd/pi/00730F01/northbridge.c: refactor IVRS generationMichał Żygowski
Use defined structures to assemble IVRS and IVHD entries. Additionally assemble IVHD type 11h which supersedes IVHD type 10h. In order to utilize all IOMMU features firmware should also expose IVHD type 11h. The new type is already supported and parsed since Xen 1.13. IVHD type 10h should still be present for backwards compatibility. TEST=boot PC Engines apu2 and disassemble IVRS using newest IASL, boot Xen 1.13 or newer with debug enabled and see IVRS IVHD 11h parsed in xl dmesg Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9a2c24b67adfa8ebd718caeb5eec88687dcbcc9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-05src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id2cb642baa764fd69543460ba869cd822ab5acad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-05Drop explicit NULL initializations from `device_operations`Elyes HAOUAS
Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside that, the struct has grown over the years. There are too many optional fields to list them all. Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25amd/common/acpi: move thermal zone to common locationMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I048d1906bc474be4d5a4e44b9c7ae28f53b49d5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25acpi: correct the processor devices scopeMichał Żygowski
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here. Additionally add processor scope patching for P-State SSDT created by AGESA, becasue AGESA creates the tables with processors in \_PR scope. TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are no errors, decompile ACPI tables with acpica to check whether the processor scope is correct and if IASL does not complain on wrong checksum, run FWTS Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/amd/pi/00730F01/state_machine.c: unhardcode IOAPIC2 addressMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I95964ac6b5939f66c40bd56939bdf532a72d75ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/39701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-23nb/amd/pi/00730F01: initialize GNB IOAPICMichał Żygowski
Northbridge IOAPIC was not being initialized which caused its APIC ID to be set to 0 (the same APIC ID as BSP). TEST=boot Debian Linux on PC Engines apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id06ad4c22a56eb3559e1d584fd0fcac1f95f13e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-23nb/amd/{agesa,pi}/acpi: include thermal zoneMichał Żygowski
According to BKDGs these northbridges should support the K10 compatible temperature sensors. TEST=boot FreeBSD on PC Engines apu2 and check the thermal zone temperature using sysctl Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Icbdf44508085964452d74e084b133f1baa39e1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-23src: capitalize 'APIC'Elyes HAOUAS
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17nb/amd/pi/00730F01: enable ACS and AER for PCIe portsMichał Żygowski
Enable Access Control Services and Advanced Error Reporting for PCI Express bridges in order to have PCIe devices in separate IOMMU groups for correct passthrough. TEST=run dmesg on Debian Buster on PC Engines apu2 and check whether PCIe devices have separate groups Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I10a8eff0ba37196692f9db6519e498fe535ecd15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-30amd/pi/00660F01: Add missing domain_acpi_name functionJorge Fernandez
It's symmetric to the code found in 00730F01 northbridge. Change-Id: I1ee439213ff128b534f5bf130661d0ae2b9558ab Signed-off-by: Jorge Fernandez <jorgefm@cirsa.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37547 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09nb/amd/pi/00730F01/state_machine: Add lost optionsMichał Żygowski
Add back options that were lost on postcar migration. Some of them seem to be required for IOMMU initialization. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie9cc772d7fcbefded8bab88f9960fef663dc7217 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37999 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09amd/agesa/state_machine: Add BeforeInitLate hooksMichał Żygowski
Add missing BeforeInitLate hooks in order to bring back certain options that were lost on postcar migration. This will also allow to disable CDIT again that caused AmdInitLate error on 00730F01. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1226e9c0c8a92920f2569ec0f85d0be0adcc9e30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-08nb/amd/pi: Fix typosElyes HAOUAS
Change-Id: I79ec3a346edde0a63cf344352e58dfb78556dfd8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38244 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02amd/acpi: Drop empty PCSD device nodesNico Huber
These devices were just added in 727ac0d263 (AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID), but they don't provide any information and are not referenced anywhere. Change-Id: I862a3c43eb610e488eb7d9246feb94a6d1333ca0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31nb/amd: Fix typoElyes HAOUAS
Change-Id: I7d27981dd7af53f0e8484d267a9a40fd3d269212 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-20AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HIDMichał Żygowski
PCI devices starting from 18 are processor configuration devices for each node and are not a bus itself. According to ACPI specification 6.3 section 6.1.5: "... _HID object must be used to describe any device that will be enumerated by OSPM. OSPM only enumerates a device when no bus enumerator can detect the device ID. ... Use the _ADR object to describe devices enumerated by bus enumerators other than OSPM." PCI device 18 with its functions has a standard enumerator, which is PCI enumerator so it needs a _ADR. Create a separate ACPI device for the processor configuration space. This fixes the ACPI compliance problem from CB:36318. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37835 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src/northbridge: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I7a214196b05d3af06c8cd742a6154b0627a0d82f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33685 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-14Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID"Nico Huber
This reverts commit 01787608670adec26fcea48173e18395e51c790e. AMD: Dropping the _HID of PCI root bus doesn't work well and people started to notice the breakage. Intel: These platforms have a devicetree switch to choose between PCI and ACPI modes. In the former case we need _ADR, but in the latter _HID as the PCI devices are hidden. The conflicting use of _ADR and _HID still needs to be fixed before we can bump our IASL version. Change-Id: If7b52b9e8f2f53574849aa3fddfccfa016288179 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04amdblocks/acpimmio: Unify BIOSRAM usageMichał Żygowski
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size. Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30AGESA,binaryPI: Flag boards with ROMCC_BOOTBLOCKKyösti Mälkki
Allows boards to be transformed to C env bootblock one at a time. Change-Id: I1cc1910a8bfb6b3495593979cbf7194b0d82c8e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37345 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29{northbridge,soc,southbridge}: Don't use both of _ADR and _HIDElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: Ifb777c09aeef09a6a4cbee254b081519f5b6c457 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-27binaryPI: Drop BINARYPI_LEGACY_WRAPPER supportKyösti Mälkki
Drop all the sources that were guarded with this. Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-26amd/pi/00730F01: Add support without BINARYPI_LEGACY_WRAPPERKrystian Hebel
A stripped down version (without S3) of ../agesa/family*/state_machine.c is used to provide platform-specific hooks. TEST=boot PC Engines apu2 with POSTCAR_STAGE patch Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32421 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25binaryPI: Use Kconfig to define the number of IOAPICsMichał Żygowski
Define the number of IOAPICs in a Kconfig to get rid of AmdGetValue calls being not conformant to AGESA API. Change-Id: I532597dd326093455358a23aef3b3ea0d0a14f75 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-27src/[northbridge,security]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If6b5930f78c3da6dcefaa7b6202cd0424a24525b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-15northbridge: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: Ib60305948ac1d3464586fe69501bd28eecb761ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33529 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20nb/amd/pi,sb/amd/sr5650: Remove unnecessary allocationJacob Garber
add_ivrs_device_entries() is a recursive function, and each recursive call is passed a pointer to a root_level variable declared outside the function. In an attempt to make the function self-contained, the initial call is made with the root_level pointer set to NULL, and then the function attempts to detect this and allocate a root_level variable for the rest of the calls. This makes memory management very tricky - for example, the pi code incorrectly attempts to free the root_level variable at the end of *each* recursive call, which only avoids being a double-free because free() in coreboot is currently a no-op. Let's keep life simple and declare root_level as a local variable outside the first function call instead. Change-Id: Ifd63ee368fb89345b9b42ccb86cebcca64f32ac8 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1362811 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34387 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20AGESA,binaryPI: Replace use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-06-28device,nb/amd: Deduplicate add_more_links()Jacob Garber
This function is duplicated in many AMD northbridge files, and all the definitions have started to diverge somewhat. This moves a single copy into device utils and deletes the rest. The function definition from nb/amd/amdfam10 was chosen to be kept, since it contains several fixes from commit 59d609217b (AMD fam10: Fix add_more_links) that the others don't have. For the ease of diffing, the checkpatch lints and other small cleanups will be done in a follow-up patch. Change-Id: I5ea73126092449db3f18e19ac0660439313072de Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33237 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03nb/amd/pi/00630F01/northbridge.c: Remove variable set but not usedElyes HAOUAS
Change-Id: Id5e762880ddfcb65872a50e8ffe10d86b3719b5d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-24nb/amd/pi/00660F01: Remove variable set but not usedElyes HAOUAS
Change-Id: I14c69b324de795ba6dead7932b3267887130a6df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-04-25src/northbridge/amd: Remove unused variablesElyes HAOUAS
Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-08nb/amd/pi/agesawrapper: Drop stale comment about IS_ENABLED()Nico Huber
We decided to not care about compile-time errors. So drop the comment, the code was updated already. Change-Id: Ib115fa6e2c48bfde7f67c327d42b3fe0e7af8c1f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-08nb/amd/pi, mb/amd/bettong: Fix null pointer checksJacob Garber
The dev pointers were being dereferenced before the null check. Move the checks so they are done earlier. Found-by: Coverity Scan, CID 1241851 (REVERSE_INULL) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ie578787c3c26a1f3acb4567c135486667e88a888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-19Fix 'unsigned int' to bare use of 'unsigned'Subrata Banik
Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-22AGESA/binaryPI: Add NULL pointers checkKyösti Mälkki
Fix regression after commits 4ad7f5b AGESA: Use pcidev_on_root() 33ff44c binaryPI: Use pcidev_on_root() Previously used call dev_find_slot() returned pointers to PCI device nodes that were actually not present in the hardware at all. Register reads would come back with invalid (0xff) values and writes would be ignored. After change to pcidev_on_root(), attempting to do register operations with non-present PCI hardware immediately halts with error get_pbus: dev is NULL! Change-Id: I785350c171a642207c5fab884a953d45a3bfe592 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-14binaryPI: Drop CONFIG_CBB and CONFIG_CDBKyösti Mälkki
Static values, copy paste from multi-node fam15 code. Add header that shall have declarations of functions common to different families factored out. Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-14binaryPI: Drop invalid northbridge.h fileKyösti Mälkki
Pointless to declare static struct in a header. Change-Id: I757f6346017681e32900f67b25fb5700a68d86b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10binaryPI: Drop warning on EXT_CONF_SUPPORTKyösti Mälkki
Copy-paste from fam15 code. Change-Id: Ic52031c57a8b659bff5ca03a66ec2291140d2233 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-09agesawrapper.c: check if HOP_COUNT_TABLE exists before AmdInitLate()Krystian Hebel
If HOP_COUNT_TABLE doesn't exist AmdInitLate() returns error when creating CDIT, which scaries users. This patch turns off CDIT generation. After this patch AGESA_UNSUPPORTED is returned due to a bug in AGESA which cannot be walked around without disabling DMI table generation (`AGESA_STATUS Status = TRUE`, present in open source version of AGESA too). Change-Id: I868aa840ad3495a66a9d70b7803af237e7d5f049 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/30475 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04binaryPI: Use pcidev_on_root()Kyösti Mälkki
We have constant CONFIG_CBB==0, replace ill dev_find_slot() with safe pcidev_on_root(); Change-Id: If536adf11aacef8faa3455692285552f97531df9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26483 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03nb/amd/pi/00{630F01,730F01}: Use ARRAY_SIZEElyes HAOUAS
Use already defined ARRAY_SIZE macro. Change-Id: Ie22e3557e958b562816921a985411dd55c712142 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29302 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src/mainboard: Remove unused "HW_MEM_HOLE_SIZE_AUTO_INC"Elyes HAOUAS
Change-Id: I10e89de270a20dbd28647e8b0f8a2425c515b350 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-05amd: Fix non-local header treated as localElyes HAOUAS
Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29103 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-20nb/amd/pi/00730F01: use MMIO and performance counters from AGESAPiotr Król
This patch contain minimal set of changes to initial IVRS implementation to make it work reliably. Code in this patch was tested with Xen 4.8 and Debian 4.14.y - this software stack survived 100x reboots without any hang on PC Engines apu2c4. Previously using IVRS provided by AGESA lead to 29/100 hangs. MMIO base shall not be hard coded since this value depends on platform design. Performance counters were selected experimentally, since lack of them cause 4.14.y panic: [ 1.064229] AMD-Vi: IOMMU performance counters supported [ 1.069579] BUG: unable to handle kernel paging request at ffffaffc4065c000 [ 1.073554] IP: iommu_go_to_state+0xf8a/0x1260 [ 1.073554] PGD 12a11f067 P4D 12a11f067 PUD 12a120067 PMD 129b69067 PTE 0 [ 1.073554] Oops: 0000 [#1] SMP NOPTI [ 1.073554] Modules linked in: [ 1.073554] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.14.50 #13 [ 1.073554] Hardware name: PC Engines apu2/apu2, BIOS 4.8-1174-gf12b3046f0-d2 [ 1.073554] task: ffff8d5d69b9f040 task.stack: ffffaffc40648000 [ 1.073554] RIP: 0010:iommu_go_to_state+0xf8a/0x1260 [ 1.073554] RSP: 0018:ffffaffc4064be28 EFLAGS: 00010282 [ 1.073554] RAX: ffffaffc40658000 RBX: ffff8d5d69bae000 RCX: ffffffff99e57b88 [ 1.073554] RDX: 0000000000000000 RSI: 0000000000000092 RDI: 0000000000000246 [ 1.073554] RBP: 0000000000000040 R08: 0000000000000001 R09: 0000000000000170 [ 1.073554] R10: 0000000000000000 R11: ffffffff9a435e2d R12: 0000000000000000 [ 1.073554] R13: ffffffff9a29a830 R14: 0000000000000000 R15: 0000000000000000 [ 1.073554] FS: 0000000000000000(0000) GS:ffff8d5d6ec80000(0000) knlGS:00000 [ 1.073554] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1.073554] CR2: ffffaffc4065c000 CR3: 000000010fa0a000 CR4: 00000000000406e0 [ 1.073554] Call Trace: [ 1.073554] ? set_debug_rodata+0x11/0x11 [ 1.073554] amd_iommu_init+0x11/0x89 [ 1.073554] pci_iommu_init+0x16/0x3f [ 1.073554] ? e820__memblock_setup+0x60/0x60 [ 1.073554] do_one_initcall+0x51/0x190 [ 1.073554] ? set_debug_rodata+0x11/0x11 [ 1.073554] kernel_init_freeable+0x16b/0x1ec [ 1.073554] ? rest_init+0xb0/0xb0 [ 1.073554] kernel_init+0xa/0xf7 [ 1.073554] ret_from_fork+0x22/0x40 [ 1.073554] Code: d2 31 f6 48 89 df e8 d8 15 02 ff 85 c0 75 d1 48 8b 44 24 2 [ 1.073554] RIP: iommu_go_to_state+0xf8a/0x1260 RSP: ffffaffc4064be28 [ 1.073554] CR2: ffffaffc4065c000 [ 1.073554] ---[ end trace 44588f98aa7c7c0b ]--- [ 1.255973] Kernel panic - not syncing: Attempted to kill init! exitcode=0x09 [ 1.255973] [ 1.259934] ---[ end Kernel panic - not syncing: Attempted to kill init! exi9 Possible future improvements: - compare device entries with values returned by AGESA - enable EFRSup (this is enabled in AGESA) - try various IVHD flags (there is difference between initial implementation and AGESA) Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/27602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-18nb/amd/pi/00730F01: Don't use device_t in ramstageElyes HAOUAS
Use of device_t has been abandoned in ramstage Change-Id: Ifc32b0f6964a8c3e3a100c787ac2a889b39322a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-15nb/amd/pi/00730F01: Add initial native IVRS supportTimothy Pearson
- Iteration over devices in add_ivrs_device_entries were simplified to decrease complexity. - Code was structured to satisfy checkpatch Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/15164 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15nb/amd/pi/00730F01: Initialize IOMMU deviceKyösti Mälkki
Change-Id: I12d3ed35770ee06626f884db23004652084c88c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15186 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-23AGESA binaryPI: Remove code for CONFIG_CBB!=0Kyösti Mälkki
These are single-node platforms with CONFIG_CBB==0 everywhere in the tree. Remove guarded code that was not built. Change-Id: I6118249937e6c8032acd78018c7c83b1da078f7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-20AGESA binaryPI: Fix and optimize for MAX_NODES_NUMKyösti Mälkki
With nodeid<8, CONFIG_CDB==0x18, PCI device number does not overflow. CONFIG_CDB is not a value we can configure. Change-Id: I23e9707a8ec12dcd80c00688d6237d085d1abf36 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14AGESA binaryPI: Drop RAMBASE and RAMTOPKyösti Mälkki
With platforms moved to RELOCATABLE_RAMSTAGE, these overrides no longer have a meaning. Overrides existed because AGESA ramstage did not fit within the default 1 MiB of RAMTOP - RAMBASE, when placed low. Change-Id: I0185875dc550de74877c94f36128d5979e5553d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26813 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-23nb/amd/pi: Get rid of device_tKyösti Mälkki
Change-Id: I9b1c597f5c6995f19e9697e8aa698fa672a220b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26473 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 06:37:08 +0000