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path: root/src/northbridge/amd/amdmct
AgeCommit message (Expand)Author
2015-11-18cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequenceTimothy Pearson
2015-11-16northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15hTimothy Pearson
2015-11-16amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10hTimothy Pearson
2015-11-16nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slotsTimothy Pearson
2015-11-15northbridge/amd/amdmct: Reduce maximum number of DDR3 DIMMsTimothy Pearson
2015-11-15northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failureTimothy Pearson
2015-11-15northbridge/amd/amdmct/mct_ddr3: Properly indicate clobbered registersTimothy Pearson
2015-11-15northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when both DCTs are in useTimothy Pearson
2015-11-15northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt valuesTimothy Pearson
2015-11-15northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangsTimothy Pearson
2015-11-15northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issueTimothy Pearson
2015-11-15northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errorsTimothy Pearson
2015-11-15amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT valuesTimothy Pearson
2015-11-15cpu/amd: Fix AMD Family 15h ECC initialization reliability issuesTimothy Pearson
2015-11-15northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC initTimothy Pearson
2015-11-14northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statementsTimothy Pearson
2015-11-14northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tablesTimothy Pearson
2015-11-12northbridge/amd/amdmct/mct_ddr3: Update prefetcher configurationTimothy Pearson
2015-11-12northbridge/amd/amdmct: Clear memory before enabling ECCTimothy Pearson
2015-11-12src/northbridge/amd/amdmct: Add option to override bad SPD checksumTimothy Pearson
2015-11-12northbridge/amd/amdmct: Verify MCT NVRAM options before skipping trainingTimothy Pearson
2015-11-11northbridge/amd/amdmct: Fix crash on startup due to NULL pointer accessTimothy Pearson
2015-11-11northbridge/amd/amdmct: Fix hang on boot due to invalid array accessTimothy Pearson
2015-11-11northbridge/amd/amdmct: Skip DCT config write to Flash if unchangedTimothy Pearson
2015-11-11cpu/amd: Add CC6 supportTimothy Pearson
2015-11-11mainboard/asus/kgpe-d16: Enable CC6Timothy Pearson
2015-11-11northbridge/amd/amdfam10: Enable CC6 DRAM save area setupTimothy Pearson
2015-11-11amd/amdmct/mct_ddr3: Use training values from previous boot if possibleTimothy Pearson
2015-11-11amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliabilityTimothy Pearson
2015-11-10northbridge/amd/amdmct/mct_ddr3: Clean up curly brace style violationsTimothy Pearson
2015-11-10northbridge/amd/amdmct: Read SPD data into cache to decrease bootup timeTimothy Pearson
2015-11-08amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15hTimothy Pearson
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
2015-11-02northbridge/amd/amdmct/mct_ddr3: Fix S3 suspend overrunning the stack size limitTimothy Pearson
2015-11-02northbridge/amd/amdfam10: Set DIMM voltage based on SPD dataTimothy Pearson
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-30northbridge/amd/amdmct/mct_ddr3: Add initial Suspend to RAM (S3) supportTimothy Pearson
2015-10-27northbridge/amd/amdfam10: Limit maximum RAM clock to BKDG recommendationsTimothy Pearson
2015-10-26northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalizationTimothy Pearson
2015-10-23northbridge/amd/amdmct: Fix Family 15h detectionTimothy Pearson
2015-10-23northbridge/amd/amdmct/mct_ddr3: Fix curly brace style violationsTimothy Pearson
2015-06-10northbridge/amd/amdmct: Honor MMCONF_BASE_ADDRESSTimothy Pearson
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-04-01northbridge/amd/amdfam10: Collect DIMM information for ramstage useTimothy Pearson
2015-04-01northbridge/amd/amdmct: Pack MCT and DCT info structsTimothy Pearson
2015-03-07northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and laterTimothy Pearson
2015-03-03northbridge/amd/amdmct: Add revision D to K10 revision mask listTimothy Pearson
2015-02-16northbridge/amd/amdfam10: Remove Kconfig memory controller optionsTimothy Pearson
2015-02-16northbridge/amd/amdfam10: Fold back memory frequency based on MCT loadTimothy Pearson
2015-02-15northbridge/amd/amdmct: Fix FTBFS with node interleaving enabledTimothy Pearson
2015-02-15northbridge/amd/amdmct: Allow override of memory settings via NVRAMTimothy Pearson
2015-01-25northbridge/amd: Add Kconfig options for ECC redirectionTimothy Pearson
2015-01-25northbridge/amd: Add Kconfig options for ECC scrub rateTimothy Pearson
2015-01-08northbridge/amd: Doxygen fixesMartin Roth
2015-01-06northbridge: Drop print_ implementation from non-romcc boardsStefan Reinauer
2014-07-29Uniformly spell frequency unit symbol as HzElyes HAOUAS
2014-07-24northbridge/amd: Remove trailing whitespaceElyes HAOUAS
2014-07-08northbridge: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-05-23northbridge/amd/amdmct: Incorrect usage of logical over bitwise andEdward O'Callaghan
2014-05-23northbridge/amd/amdmct: Superfluous parenthesis in if-statementsEdward O'Callaghan
2014-05-22northbridge/amd/amdmct/mct: Initialize variables at the eolEdward O'Callaghan
2014-01-28x86: add common definitions for control registersAaron Durbin
2013-12-23Coding style: punctuation cleanup [1/2].Idwer Vollering
2013-06-03northbridge/amd/amdmct: Use `static const` instead of `const static`Paul Menzel
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2012-05-08Some more #if cleanupPatrick Georgi
2012-05-08Clean up #ifsPatrick Georgi
2012-03-02Fix ECC disable option for AMD Fam10 DDR2 and DDR3.Marc Jones
2011-11-01remove trailing whitespaceStefan Reinauer
2011-10-15AMD CPU and chipset fixes for compilation with gcc 4.6Stefan Reinauer
2011-09-24Add AMD Family 10h PH-E0 supportQingPei Wang
2011-06-03This patch sets max freq defaults for ddr2 and ddr3for fam10.Marc Jones
2011-03-28Add AMD C32 support.Zheng Bao
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-01-20For Cx, each ChipSel need to be sent MR command.Zheng Bao
2011-01-17The code is tested on my board with register DIMMs. More tests need to beZheng Bao
2011-01-06Fix some settings fo AMD MCT. It is based on BIOS test suite.Zheng Bao
2010-12-02More explicite and straight way to set seed.Zheng Bao
2010-11-13MTRR related improvements for AMD family 10h and family 0Fh systemsScott Duplichan
2010-10-13Trivial. Clean up code and add some comments.Zheng Bao
2010-10-09Trivial. Spell checking.Zheng Bao
2010-10-09Trivial. Spell checking.Zheng Bao
2010-10-08Trivial. Spell checking.Zheng Bao
2010-10-08Trivial. Fix the typo.Zheng Bao
2010-10-01Trivial. Re-indent the code.Zheng Bao
2010-09-28Trivial. re-Indent the code.Zheng Bao
2010-09-27Obviously missing brackets.Xavi Drudis Ferran
2010-09-21Complete the code which was missing.Zheng Bao
2010-09-21Fix the typo. Field DisAutoRefresh is in DramTimngHi.Zheng Bao
2010-09-09Please find appended. This patch gets rid of the %gs magic altogether,Arne Georg Gleditsch
2010-09-09Also improve boot time on AMD for the DDR3 code path.Arne Georg Gleditsch
2010-09-09Apparently, it's not crucial to clear this at the exact moment we switchArne Georg Gleditsch
2010-09-05Trivial. Currently the max frequency is preset as 400Mhz. We need to set aZheng Bao
2010-09-04AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.Kerry She
2010-08-31Get Byte65/66 for register manufacture ID code. RegMan1Present willZheng Bao
2010-08-30Multi-DIMMS on AMD ddr2 MCT channel B fixed.Kerry She
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