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Age
Commit message (
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Author
2009-09-14
Use the coreboot pci config read/write functions instead of direct cf8/cfc
Marc Jones
2009-08-25
Without this patch, if we only got a DIMM in Channel B, memory can not be
Zheng Bao
2009-08-24
This patch is about the DA-C2 and RB-C2. Chip with install processor
Zheng Bao
2009-08-19
The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instea...
Zheng Bao
2009-07-17
This is an obvious bug which I overlooked when I worked on the AM2r2
Zheng Bao
2009-07-01
Add AMD family 10 AM2r2 support.
Zheng Bao
2009-06-06
Fix for Erratum 350 for AMD Fam10h CPUs.
Marco Schmidt
2009-05-14
Update equivalent processor revision ID to load latest microcode patches and
Marc Jones
2008-12-05
Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de>
Stefan Reinauer
2008-07-23
Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).
Marc Jones
2008-04-25
Remove inline from FAM10 CPU initialization functions.
Marc Jones
2008-04-22
Add early MSR and PCI register initialization.
Marc Jones
2008-04-11
Bring Fam10 memory controller init up to date with the latest AMD BKDG
Marc Jones (marc.jones
2008-01-18
Rename almost all occurences of LinuxBIOS to coreboot.
Stefan Reinauer
2008-01-18
Please bear with me - another rename checkin. This qualifies as trivial, no
Stefan Reinauer
2007-12-19
Initial AMD Barcelona support for rev Bx.
Marc Jones
