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Author
2019-08-10
src: Include <stdint.h> instead of <inttypes.h>
Jacob Garber
2019-07-02
src: Use CRx_TYPE type for CRx
Elyes HAOUAS
2018-11-12
src: Remove unneeded include "{arch,cpu}/cpu.h"
Elyes HAOUAS
2018-11-05
amd/mtrr: Fix IORR MTRR
Elyes HAOUAS
2018-10-30
{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros
Elyes HAOUAS
2018-10-18
cpu/amd: Use common AMD's MSR
Elyes HAOUAS
2018-07-09
src/northbridge: Use "foo *bar" instead of "foo* bar"
Elyes HAOUAS
2018-06-14
src: Get rid of unneeded whitespace
Elyes HAOUAS
2018-05-09
{device,drivers,lib,mb,nb}: Use only one space after 'if'
Elyes HAOUAS
2017-01-11
amd/mct/ddr3: Avoid using uninitialized register address in ECC setup
Timothy Pearson
2017-01-10
amd/mct/ddr3: Fix incorrect DQ mask calculation
Timothy Pearson
2017-01-10
amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc
Timothy Pearson
2017-01-04
amdfam10: Perform major include ".c" cleanup
Damien Zammit
2016-09-21
northbridge/amd/amdmct: Improve code formatting
Elyes HAOUAS
2016-08-31
northbridge/amd: Add required space before opening parenthesis '('
Elyes HAOUAS
2016-08-01
Remove non-ascii & unprintable characters
Martin Roth
2016-05-09
nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15h
Timothy Pearson
2016-05-01
nb/amd/mct_ddr3: Stop receiver enable cycle training after window found
Timothy Pearson
2016-05-01
nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0
Timothy Pearson
2016-03-26
nb/amd/amdmct: Select max_lanes based on ECC presence or absence
Damien Zammit
2016-03-24
nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
Timothy Pearson
2016-03-21
nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set
Timothy Pearson
2016-03-13
nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training
Timothy Pearson
2016-03-12
nb/amd/mct_ddr3: Consolidate duplicated code
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Require minumum training quality for both read and write
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop
Timothy Pearson
2016-02-05
nb/amd/mct_ddr3: Work around RDIMM training failure
Timothy Pearson
2016-01-24
nb/amd/mct_ddr3: Add additional verbose-level debug statements
Timothy Pearson
2015-12-01
nb/amd/mct_ddr3: Add Family 15h tristate enable codes
Timothy Pearson
2015-11-30
nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training time
Timothy Pearson
2015-11-30
nb/amd/mct_ddr3: Use antiphase to better center DQS window
Timothy Pearson
2015-11-29
nb/amd/mct_ddr3: Fix odd rank data corruption
Timothy Pearson
2015-11-23
amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs
Timothy Pearson
2015-11-16
northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15h
Timothy Pearson
2015-11-16
amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h
Timothy Pearson
2015-11-15
cpu/amd: Fix AMD Family 15h ECC initialization reliability issues
Timothy Pearson
2015-11-02
cpu/amd: Add initial AMD Family 15h support
Timothy Pearson
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-26
northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization
Timothy Pearson
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-01-06
northbridge: Drop print_ implementation from non-romcc boards
Stefan Reinauer
2014-07-29
Uniformly spell frequency unit symbol as Hz
Elyes HAOUAS
2013-06-03
northbridge/amd/amdmct: Use `static const` instead of `const static`
Paul Menzel
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2011-10-15
AMD CPU and chipset fixes for compilation with gcc 4.6
Stefan Reinauer
2011-01-06
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Zheng Bao
2010-10-13
Trivial. Clean up code and add some comments.
Zheng Bao
2010-10-08
Trivial. Spell checking.
Zheng Bao
2010-08-30
Multi-DIMMS on AMD ddr3 MCT channel B works.
Kerry She
2010-04-23
DDR3 support for AMD Fam10.
Zheng Bao