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Author
2016-04-28
nb/amd/mct_ddr3: Restart system on training failure instead of using die()
Timothy Pearson
2016-04-22
Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"
Timothy Pearson
2016-04-08
Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"
Timothy Pearson
2016-04-08
nb/amd/mct_ddr3: Add MCE reporting logic
Timothy Pearson
2016-04-08
nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level
Timothy Pearson
2016-03-31
nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
Timothy Pearson
2016-03-31
nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs
Timothy Pearson
2016-03-31
nb/amd/mct_ddr3: Disable MCE framework during DRAM training
Timothy Pearson
2016-03-30
nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed
Timothy Pearson
2016-03-30
northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)
Damien Zammit
2016-03-28
nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()
Timothy Pearson
2016-03-26
nb/amd/amdmct: Select max_lanes based on ECC presence or absence
Damien Zammit
2016-03-24
nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
Timothy Pearson
2016-02-19
nb/amd/amdmct: Add socket specific configuration for FM2
Damien Zammit
2016-02-05
nb/amd/mct_ddr3: Work around RDIMM training failure
Timothy Pearson
2016-01-29
nb/amdmct/mct_ddr3: Enable mainboard voltage set
Timothy Pearson
2016-01-24
nb/amd/mct_ddr3: Update drive strength configuration
Timothy Pearson
2016-01-24
northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devices
Timothy Pearson
2016-01-24
northbridge/amd/amdmct: Add termination and timing values for C32 sockets
Timothy Pearson
2015-12-01
nb/amd/mct_ddr3: Add Family 15h tristate enable codes
Timothy Pearson
2015-11-29
nb/amd/amdmct/mct_ddr3: Ensure channel clock skew is properly set
Timothy Pearson
2015-11-24
northbridge/amd/amdmct/mct_ddr3: Add CC6 setup information messages
Timothy Pearson
2015-11-24
amd/amdfam10: Control Fam15h cache partitioning via nvram
Timothy Pearson
2015-11-23
amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs
Timothy Pearson
2015-11-22
amd/amdmct/mct_ddr3: Set prefetch double stride to improve performance
Timothy Pearson
2015-11-22
nb/amd/amdmct/mct_ddr3: Force DRAM retraining on every boot
Timothy Pearson
2015-11-19
northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file
Timothy Pearson
2015-11-18
cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequence
Timothy Pearson
2015-11-16
northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15h
Timothy Pearson
2015-11-16
amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h
Timothy Pearson
2015-11-16
nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots
Timothy Pearson
2015-11-15
northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure
Timothy Pearson
2015-11-15
northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when both DCTs are in use
Timothy Pearson
2015-11-15
northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values
Timothy Pearson
2015-11-15
northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangs
Timothy Pearson
2015-11-15
amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT values
Timothy Pearson
2015-11-15
cpu/amd: Fix AMD Family 15h ECC initialization reliability issues
Timothy Pearson
2015-11-15
northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC init
Timothy Pearson
2015-11-14
northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements
Timothy Pearson
2015-11-14
northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tables
Timothy Pearson
2015-11-12
northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration
Timothy Pearson
2015-11-12
northbridge/amd/amdmct: Clear memory before enabling ECC
Timothy Pearson
2015-11-12
src/northbridge/amd/amdmct: Add option to override bad SPD checksum
Timothy Pearson
2015-11-12
northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training
Timothy Pearson
2015-11-11
northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged
Timothy Pearson
2015-11-11
cpu/amd: Add CC6 support
Timothy Pearson
2015-11-11
northbridge/amd/amdfam10: Enable CC6 DRAM save area setup
Timothy Pearson
2015-11-11
amd/amdmct/mct_ddr3: Use training values from previous boot if possible
Timothy Pearson
2015-11-11
amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability
Timothy Pearson
2015-11-10
northbridge/amd/amdmct/mct_ddr3: Clean up curly brace style violations
Timothy Pearson
2015-11-10
northbridge/amd/amdmct: Read SPD data into cache to decrease bootup time
Timothy Pearson
2015-11-08
amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h
Timothy Pearson
2015-11-02
cpu/amd: Add initial AMD Family 15h support
Timothy Pearson
2015-11-02
northbridge/amd/amdfam10: Set DIMM voltage based on SPD data
Timothy Pearson
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-30
northbridge/amd/amdmct/mct_ddr3: Add initial Suspend to RAM (S3) support
Timothy Pearson
2015-10-26
northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization
Timothy Pearson
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-04-01
northbridge/amd/amdfam10: Collect DIMM information for ramstage use
Timothy Pearson
2014-07-29
Uniformly spell frequency unit symbol as Hz
Elyes HAOUAS
2014-05-23
northbridge/amd/amdmct: Superfluous parenthesis in if-statements
Edward O'Callaghan
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2012-03-02
Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
Marc Jones
2011-10-15
AMD CPU and chipset fixes for compilation with gcc 4.6
Stefan Reinauer
2011-06-03
This patch sets max freq defaults for ddr2 and ddr3for fam10.
Marc Jones
2011-01-06
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Zheng Bao
2010-10-08
Trivial. Spell checking.
Zheng Bao
2010-09-28
Trivial. re-Indent the code.
Zheng Bao
2010-09-27
Obviously missing brackets.
Xavi Drudis Ferran
2010-09-21
Fix the typo. Field DisAutoRefresh is in DramTimngHi.
Zheng Bao
2010-09-09
Also improve boot time on AMD for the DDR3 code path.
Arne Georg Gleditsch
2010-09-05
Trivial. Currently the max frequency is preset as 400Mhz. We need to set a
Zheng Bao
2010-09-04
AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.
Kerry She
2010-08-31
Get Byte65/66 for register manufacture ID code. RegMan1Present will
Zheng Bao
2010-08-30
Trivial syntax correction of AMD mct_ddr3 dir.
Kerry She
2010-04-23
DDR3 support for AMD Fam10.
Zheng Bao