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2013-09-11CBMEM AMD: Fix calls to set_top_of_ram_once()Kyösti Mälkki
We can postpone the call to set_top_of_ram_once() outside the loops and make just one call instead. As set_top_of_ram() is now only called once, it is no longer necessary to check if high_tables_base was already set. Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-11CBMEM AMD: Remove references to global high_tables_baseKyösti Mälkki
Prepare for removal of globals high_tables_base and _size by replacing the references with a helper function. Added set_top_of_ram_once() may be called several times, but only the first call (with non-zero argument) takes effect. Change-Id: I5b5f71630f03b6a01e9c8ff96cb78e9da03e5cc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-11Set PCI bus operations at buildtime for ramstageKyösti Mälkki
PCI bus operations are static through the ramstage, and should be initialized from the very beginning. For all the replaced instances, there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for the northbridge, so these continue to use PCI IO config access. Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-24AMD: Drop empty root_complexKyösti Mälkki
There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-05-10Get rid of a number of __GNUC__ checksStefan Reinauer
In the process of streamlining coreboot code and getting rid of unneeded ifdefs, drop a number of unneeded checks for the GNU C compiler. This also cleans up x86emu/types.h significantly by dropping all the duplicate types in there. Change-Id: I0bf289e149ed02e5170751c101adc335b849a410 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3226 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-08Drop CONFIG_AP_CODE_IN_CARStefan Reinauer
This option has not been enabled on any board and was considered obsolete last time it was touched. If we need the functionality, let's fix this in a generic way instead of a K8 specific way. This was mostly a speedup hack back in the day. Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3211 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-12Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"Nico Huber
This reverts commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5: commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5 Author: Patrick Georgi <patrick.georgi@secunet.com> Date: Tue Apr 9 15:41:23 2013 +0200 siemens/sitemp_g1p1: Make ACPI report the right mmconf region ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> It sneaked in without it's dependencies and, therefore, broke the build for all amdk8 targets. Paul Menzel already commented on the issue in [1]. It also doesn't look like the dependencies would be pulled soon [2]. [1] http://review.coreboot.org/#/c/3047/ [2] http://review.coreboot.org/#/c/2662/ Change-Id: Ica89563aae4af3f0f35cacfe37fb608782329523 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3063 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-04-10siemens/sitemp_g1p1: Make ACPI report the right mmconf regionPatrick Georgi
ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-28Drop CONFIG_WRITE_HIGH_TABLESStefan Reinauer
It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1928 Tested-by: build bot (Jenkins)
2012-11-28amdk8/amdfam10: Use CAR_GLOBAL for sysinfoPatrick Georgi
This gets rid of the somewhat unstructured placement of AMD's sysinfo structure in CAR. We used to carve out some CAR space using a Kconfig variable, and then put sysinfo there manually (by "virtue" of pointer magic). Now it's a variable with the CAR_GLOBAL qualifier, and build system magic. For this, the following steps were done (but must happen together since the intermediates won't build): - Add new CAR_GLOBAL sysinfo_car - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR - remove DCACHE_RAM_GLOBAL_VAR_SIZE - from CAR setup (no need to reserve the space) - commented out code (that was commented out for years) - only copy sizeof(sysinfo) into RAM after ram init, where before it copied the whole GLOBAL_VAR area. - from Kconfig Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Get rid of drivers classPatrick Georgi
The use of ramstage.a required the build system to handle some object files in a special way, which were put in the drivers class. These object files didn't provide any symbols that were used directly (but only via linker magic), and so the linker never considered them for inclusion. With ramstage.a gone, we can drop this special class, too. Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-10-07Remove chip.h files without config structureKyösti Mälkki
Also deletes files not included in build: src/southbridge/amd/cimx/sb700/chip_name.c src/southbridge/amd/cimx/sb800/chip_name.c src/southbridge/amd/cimx/sb900/chip_name.c Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1473 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-08-28Fix AMD UMA for RS780Kyösti Mälkki
In commit 6b5eb1cc2d1702ff10cd02249d3d861c094f9118 setup of UMA memory region was moved to happen at a later state and this broke UMA with RS780 southbridge. Share the TOP_MEM and UMA settings before any of the PCI or CPU scanning takes place. Change-Id: I9cae1fc2948cbccede58d099faf1dfe49e9df303 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1488 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-27AMD northbridges: factor out CPU allocationKyösti Mälkki
Factor CPU allocation out of AMD northbridge codes. As CPU topology information is required for generation of certain ACPI tables, make this code globally available. For AMDK8 and AMDFAM10 northbridge, there is a possible case of BSP CPU with lapicid!=0. We do not want to leave the lapic 0 from devicetree unused, so always use that node for BSP CPU. Change-Id: I8b1e73ed5b20b314f71dfd69a7b781ac05aea120 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1418 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-27AMD northbridges: rewrite CPU allocationKyösti Mälkki
Use of alloc_find_dev() prevents creation of a device duplicates for device_path and is SMP safe. Reduce scope of variables to make the code more readable and in preparation for refactoring the allocation out of northbridge.c. Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1186 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-22Auto-declare chip_operationsKyösti Mälkki
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-09AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki
Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed to AP CPUs and factor out the debugging info from setup_uma_memory(). Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1387 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1184 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-02AMD and GFXUMA: move setup_uma_memory() to northbridgeKyösti Mälkki
UMA region can be determined at any time after the amount of RAM is known and before the uma_resource() call. Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1379 Reviewed-by: Zheng Bao <zheng.bao@amd.com> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-02AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_baseKyösti Mälkki
The code in rs690 or rs780 is always used with K8 or AMDFAM10 northbridge. Without GFXUMA, both of these set the same static value indirectly using the variable uma_memory_base. Make the register setting with immediate value, to remove the obscure use of variable uma_memory_base. Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1246 Reviewed-by: Zheng Bao <zheng.bao@amd.com> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-16AMD: Fix GFXUMA with 4GB or more RAMKyösti Mälkki
Northbridge code incorrectly adjusted the last cacheable memory resource to accomodate room for UMA framebuffer. If system had 4GB or more memory that last resource is not below 4GB and not the one where UMA is located. There are three consequences: The last entry in coreboot memory table is reduced by uma_memory_size. Due the incorrect code in northbridge code state.tomk, end of last resource below 4GB, had not been adjusted. Incrementing that by uma_memory_size diverts a region possibly claimed for MMIO to RAM, as TOP_MEM is written. Since the UMA framebuffer did not have IORESOURCE_CACHEABLE, it was ignored from the MTRR setup and not set uncacheable. The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs, should be copied from BSP to all APs instead of deriving the data separately for each Logical CPU. Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1217 Tested-by: build bot (Jenkins) Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Move setup_uma_memory() to K8 northbridgeKyösti Mälkki
These boards had identical UMA code: amd/dbm690t amd/pistachio technexion/tim5690 technexion/tim8690 The ones below had whitespace or debug level change compared to the one above: kontron/kt690 siemens/sitemp_g1p1 These boards use AMDFAM10 guidelines in code: asrock/939a785gmh amd/mahogany Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1210 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Define global uma_memory variablesKyösti Mälkki
Use of the uma_memory_base and _size variables is very scattered. Implementation of setup_uma_memory() will appear in each northbridge. It should be possible to do this setup entirely in northbridge code and get rid of the globals in a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Add global uma_resource()Kyösti Mälkki
Like ram_resource(), but reserved and not cacheable. Switch all AMD northbridges to use this one. Change-Id: I88515c6a0f59f80fd8607c390d0d4a2a35d805f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-08Some more #if cleanupPatrick Georgi
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} + (manual tweak since it hit a false positive) Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} + Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1006 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-03-16VIA southbridge K8T890: Apply un-written naming rulesKyösti Mälkki
Use separate Kconfig option to select a driver directory for build and the specific type of southbridge to support. Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/685 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-07Move C labels to start-of-linePatrick Georgi
Also mark the corresponding lint test stable. Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-14k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-xFlorian Zumbiehl
Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/481 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-11-23k8 raminit: fix bug, improve clock selection, add clock limit for sock754Florian Zumbiehl
in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/377 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-16fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminitFlorian Zumbiehl
Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/376 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-07Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26Florian Zumbiehl
Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/370 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-15AMD CPU and chipset fixes for compilation with gcc 4.6Stefan Reinauer
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/266 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-12amdk8: ASL include for K8 temperature sensor support in ACPIChristoph Grenz
Add a ACPI Source Language snippet which if included as shown in the comments in the file, exposes the 4 possible temperature sensors in the CPU as ACPI thermal zones. Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/222 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platformsenok71
The hp/dl145_g1 motherboard did not work since commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That commit added TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process stopped very early (no console output whatsoever). The same symptom was reported on other AMDK8 based boards with amd8111 southbridge chips. This commit seems to fix the bug. It adds a bootblock.c under src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the problem was that enum_ht_chains needs to be called before the southbridge bootblock.c function, not after. Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4 Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/235 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-30Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP andRudolf Marek
for the transmit clock driving control. Unfortunately this is not enough to make the HT1000 work reliably, therefore blacklist this for now in CPU HT code. If ever anyone figure out what is wrong, it could be removed. The downgrading now makes the board work on HT800, which is certainly better than not at all with a HT1000 CPU. Change-Id: I949bfd9b0b48ee12bd0234c2fb1deaaa773bd235 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/68 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-05-11Work around unclean CMOS handling for nowPatrick Georgi
Stefan switched away from #ifdef across the tree (and is absolutely right with that), but unfortunately there are some special cases that trigger in even more special situations. Revert one such change selectively. It's destined to go once CMOS is reworked. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-10Change read_option() to a macro that wraps some API uglynessPatrick Georgi
Simplify read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault) to read_option(foo, somedefault) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21more ifdef -> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19cleanup wrong use of defined() after exporting all variables in KconfigStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24Add compile-time defaults to some K8 CMOS options in case they're absent in CMOSJosef Kellermann
This affects the CMOS options iommu, ECC_memory, max_mem_clock, hw_scrubber, interleave_chip_selects. If they're absent in cmos.layout, a Kconfig value is used if it exists, or a hardcoded default otherwise. [Patrick: I changed the ramstage CMOS handling a bit, and dropped the reliance of hw_scrubber on ECC RAM, as it has nothing to do with it - it's the cache that's being scrubbed here.] Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Errata #169 works on HT, not MCJosef Kellermann
Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10Implemented workaround for erratum 169, obsoleting erratum 131.Alexandru Gagniuc
Workaround for 131 removed. Changed workaround for erratum 110 to only include pre-revision-F processors. For details, check AMD publications: #25759 (Errata for Fam F pre-revision F processors) #33610 (Errata for Fam F revision F and later processor) Based on work and previous patches by: Rudolf Marek <r.marek@assembler.cz> Josef Kellermann <seppk@arcor.de> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13Attached patch implements the memory speed reductions (and 2T/1T clock ↵Rudolf Marek
logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3. The patch looks at certain DDR configurations (dual rank/single rank) and lowers the clocks to 2T or frequency as guide suggest. It sets the DualDIMMen bit which I believe should be set for non-dual channel configs. The patch does not implement support for three dimm configurations supported from revE. On the other hand it should improve greatly memory stability across the 939 platform. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13Following patch adds support to bring out the memory out of self refresh ↵Rudolf Marek
when doing resume. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> The patch is based on my 2008 patch. Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13We hardcode highmemory size in every northbridge! This is bad, and ↵Rudolf Marek
especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic. Abuild tested. Please check all changes if I did not make any wrong while converting this to bytes. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11After this has been brought up many times before, rename src/arch/i386 toStefan Reinauer
src/arch/x86. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08second round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-221) wraps the s3 parts of chipset code/memory init code with if ↵Rudolf Marek
CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c 2) the patch implements get_cbmem_toc in chipset specific way if defined. On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached) 3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself. 4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right. I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again. Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22Printing coreboot debug messages on VGA console is pretty much useless, sinceStefan Reinauer
initializing VGA happens pretty much as the last thing before starting the payload. Hence, drop VGA console support, as we did in coreboot v3. - Drop VGA and BTEXT console support. Console is meant to be debugging only, and by the time graphics comes up 99% of the risky stuff has already happened. Note: This patch does not remove hardware init but only the actual output functionality. The ragexl driver needs some extra love, but that's for another day - factor out die() and post() - drop some leftover RAMBASE < 0x100000 checks. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: QingPei Wang<wangqingpei@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Some more DIMM0 related cleanups and deduplication.Uwe Hermann
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do. - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of romstage.c files and lots of spd_addr.h files. Don't even bother for those spd_addr.h which aren't even actually used, drop them right away. - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1, and 0xa0 with (DIMM0 << 1) where appropriate. - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0, SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC. - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines. - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do. Then, replace 0xa0 (which now becomes 0x50) with DIMM0. - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes. - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Fix/drop some obsolete comments,Uwe Hermann
- s/Options.lb/devicetree.cb/ - s/Config.lb/devicetree.cb/ - s/cache_as_ram_auto.c/romstage.c/ - h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in the tree now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17This problem was introduced withTobias Diedrich
http://tracker.coreboot.org/trac/coreboot/changeset/3953 Note that all corresponding DSDTs only ever check TOM2 against 0. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-13MTRR related improvements for AMD family 10h and family 0Fh systemsScott Duplichan
-- When building for UMA, reduce the limit for DRAM below 4GB from E0000000 to C0000000. This is needed to accomodate the UMA frame buffer. -- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En and Tom2ForceMemTypeWB) are not set consistently across cores. -- Enable TOM2 only if DRAM is present above 4GB. -- Use AMD Tom2ForceMemTypeWB feature to avoid the need for variable MTRR ranges above 4GB. -- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for DRAM above 4GB. AMD systems use this option to conserve MTRRs. -- Northbridge.c change to deduct UMA memory from DRAM size reported by ram_resource. This corrects a problem where mtrr.c generates an unexpected variable MTRR range. -- Correct problem causing build failure when CONFIG_GFXUMA=1 and CONFIG_VAR_MTRR_HOLE=0. -- Reserve the UMA DRAM range for AMD K8 as is already done for AMD family 10h. Tested with mahogany on ECS A780G-GM with 2GB and 4GB. Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10Make amdk8 printk_raminit() accept just a single string parameterPeter Stuge
The function is called with no format specifiers in the first parameter throughout the code, so it needs to work also with just one parameter. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Move K8_ALLOCATE_IO_RANGE to Kconfig.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05Move QRANK_DIMM_SUPPORT to Kconfig, removing it from romstage.cPatrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11Factor out a few commonly duplicated functions from northbridge.c.Uwe Hermann
The following functions are moved to devices/device_util.c: - ram_resource() - tolm_test() - find_pci_tolm() There are only two tolm_test() / find_pci_tolm() which differ from the defaults, one of them can easily be eliminated in a follow-up patch, maybe even both, but for now keep it simple and only eliminate the majority. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-07Remove duplicate line from pci_ids.h.Jonathan Kollasch
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Jonathan Kollasch <jakllsch@kollasch.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05Use %p instead of %x to print void *.Jonathan Kollasch
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Jonathan Kollasch <jakllsch@kollasch.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-02Fix spelling/typos in comments.Jonathan Kollasch
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,Patrick Georgi
rename it slightly, make it visible only on relevant northbridges, drop it entirely from via boards (as they seem to have picked it up from AMD code without using it themselves), and make it default to false for all boards. Some romstages used to set this to "true" (ie. "print debug output"), but I didn't follow up on it in Kconfig - if you need it to debug CAR, enable it yourself. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30Rename build system variables to be more intuitive, andPatrick Georgi
at the same time let the user specify sources instead of object files: - objs becomes ramstage-srcs - initobjs becomes romstage-srcs - driver becomes driver-srcs - smmobj becomes smm-srcs The user servicable parts are named accordingly: ramstage-y, romstage-y, driver-y, smm-y Also, the object file names are properly renamed now, using .ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently. Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't easily fit in the build system and aren't useful anyway. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coreystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25- Fix race condition in option_table.h generation by moving the includeStefan Reinauer
statement to those files that actually need it. This significantly reduces the number of dependencies, so it's no longer extremely ugly to specify them manually (see the src/pc80/Makefile.inc portion) - Add double include guards around option_table.h defines - Also, drop the AMD DBM690T work around for the issue Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-10Move memory type information out of some AMD sockets.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-27drop three unneeded config variables:Jens Rottmann
- HAVE_HIGH_TABLES - HAVE_LOW_TABLES - FALLBACK_SIZE Jens Rottmann sent an almost identical patch at the same time, so Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /Jens Rottmann
chipset support it. But this involves a long list of 'depends', which you have to remember updating manually. Converted this into HAVE_... properties, which will be inherited automatically if someone copies a chipset to create a new one. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-09Trivial -Werror fix.Cristi M
Signed-off-by: Cristi M <cristi.magherusan@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-08Fix all warnings in the tree Stefan Reinauer
(does not fix the cmos.layout race yet) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-07fix some more warningsStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-06Eliminate a couple of warnings from setup_resourcemap.cMyles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-06Re-integrate "USE_OPTION_TABLE" code.Edwin Beasant
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-06A bug fix:Myles Watson
Fix the ctrl_devport_conf_clear to clear the enable bit. A simplification: Dynamically enable ck804s that are found instead of relying on #defines. Removing an Opteron changes the number of ck804s that are present. Simple changes to make it easier to compare the factory BIOS with Coreboot when using SerialICE for boards with the Nvidia ck804 chipset: If the mask is zero, don't read the value, just write the new value over it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-17Always enable parent resources before child resources.Myles Watson
Always initialize parents before children. Move s2881 code into a driver. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-09Same conversion as with resources from static arrays to lists, exceptMyles Watson
there is no free list. Converting resource arrays to lists reduced the size of each device struct from 1092 to 228 bytes. Converting link arrays to lists reduced the size of each device struct from 228 to 68 bytes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-09Make k8 & fam10 northbridge.c code more similar.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-04This patch replaces the headers of the following files:Frank Vibrans
src/cpu/amd/model_fxx/model_fxx_update_microcode.c src/northbridge/amd/amdk8/amdk8_acpi.c src/southbridge/amd/amd8132/amd8132_bridge.c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> http://www.coreboot.org/pipermail/coreboot/2010-June/058668.html git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-21Fix amdk8_util.asl and explain behaviour a bit.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-21Use lists instead of arrays for resources in devices to reduce memory usage.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14more acpica fixes... The tricky part is the stuff in the AMD mainboard ↵Stefan Reinauer
directories. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-10High tables don't have to be on node 0 on K8. Make it less restrictive.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-30Get rid of a few more warnings.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27Since some people disapprove of white space cleanups mixed in regular commitsStefan Reinauer
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25zero warnings daysStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-23zero warnings days...Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-22zero warnings days...Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-20As Myles suggested a while back: Switch long time #warnings to be commentsStefan Reinauer
only. Keeping them as #warnings will not likely that they're fixed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-15zero warnings days...Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-14Remove few more warnings and some dead code.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-09fix the broken nvidia chipset boards,Stefan Reinauer
remove more warnings. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-09zero warnings days.Stefan Reinauer
The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning. The 1000 ways of how the AMD code waits for the cores to be started up are a real pain for the brain. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-091. This patch adds CAR for Intel P6 series processors.Joseph Smith
2. Add support for Micro-FCBGA 479 Celeron and PIII's 3. Add support for model_6bx and microcode updates 4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000 Build and boot tested. Signed-off-by: Joseph Smith <joe@settoplinux.org> The change to CAR reveiled a few more warnings in the ICH4 and i830 code, I fixed them on the fly. Checking this in because my last two commits broke Joseph's CAR patch. This version fixes the issues. Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-08Replace dual_core and quad_core CMOS (nvram) options with multi_core. Fix ↵Myles Watson
some white space. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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