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2018-03-07mb/scaleway/tagada: Override baudrate with bmcInfoJulien Viard de Galbert
Change-Id: Idd93b64ef91a569127a0713fdb499dff2a1f11db Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/scaleway/tagada: Implement console loglevel override using bmcInfoJulien Viard de Galbert
Change-Id: I0093cfafe7eaa4a4381e67c9b871fdf28abc470d Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/scaleway/tagada: Add bmcInfo interfaceJulien Viard de Galbert
This interface gives access to configuration information stored in flash by the Tagada BMC before booting the SoC. Change-Id: I4351aa11b08bdf65e14706b261c532bbf8837aed Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/google/poppy/variants/nami: Add memory detection logicShelley Chen
Alkali will use LPDDR3, so need to have Nami support both DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO. BUG=b:73514687 BRANCH=None TEST=None Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07mb/google/poppy/variants/nami: Add spd filesShelley Chen
Add spd files for LPDDR3 based on info received from factory team. BUG=b:73287172 BRANCH=None TEST=None Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-06google/snappy: enhance CCD type-A USB 2.0 phy strengthKevin Chiu
Alan(11")/BigDaddy(14") right type-A(port#2), CCD(port#4) are occasionally undetectable. USB 2.0 phy needs an override to enhance drive strength. right type-A port#2 PERPORTPETXISET: 4 PERPORTTXISET: 4 IUSBTXEMPHASISEN: 1 PERPORTTXPEHALF: 0 CCD port#4 PERPORTPETXISET: 7 PERPORTTXISET: 7 IUSBTXEMPHASISEN: 1 PERPORTTXPEHALF: 0 BUG=b:72922816 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I2b18c11709280d00ec3a6ef10f93a416acb4fb45 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/24969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06mainboard/google/fizz: Check HDMI HPD and DisplayPort HPDDaisuke Nojiri
Some type-c monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Also, if an HDMI monitor is connected, no wait is needed. If only an HDMI monitor is connected, currently the API always loops until the stopwatch expires. This patch will make the AP skip DisplayPort wait loop if it detects an HDMI monitor. And if an HDMI monitor is not detected, the AP will wait for DisplayPort mode (like before) but also its HPD signal. This patch also extends the wait loop time-out to 3 seconds. BUG=b:72387533 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-06mb/google/fizz: Skip FSP init for UART 0Duncan Laurie
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot and should not be used as a UART device. coreboot is setting the pins to GPIO Mode but FSP is re-configuring them for Native Mode and the behavior is unexpected when the kernel tries to initialize the UART device. The UART 0 device is PCI function 0 so it needs to be enabled for other functions to be visible to the OS so it can't just be disabled. Instead, set the device to PchSerialIoSkipInit so that FSP will not change the pin state. BUG=b:73006317 TEST=Tested with add-in card on fizz hardware to ensure the pin state does not change when FSP runs or the kernel boots. Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06Revert "mainboard/google/meowth: enable PCH iSCLK"Lijian Zhao
This reverts commit 2e81f394cffc6f1993a5f004356ed35f6064fe48, as it will have side effect that will make system shutdown failure. System will not enter S5 sleep state, instead a global reset will be generated. Once camera driver ACPI framework ready, isclk programing will be moved into APCI method, in _PS3, isclk will be turned off to save power. BUG=b.72532565 BRANH=master TEST=Apply the changes and flash coreboot, on meowth devices, issue "halt" in OS stage, system can shutdown successfully. Change-Id: If35697911f97c524d9b52bdf4dae5c9ef1cc8618 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25006 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-05mb/google/poppy: Allow use of optional secondary SPDFurquan Shaikh
This change adds support for variants to use secondary SPD if required. This enables a variant to have different types of memory supported using the same image. BUG=b:73514687 Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05mb/google/poppy/variants: Set pch_trip_temp to 75CFurquan Shaikh
Similar to Soraka, this change sets the pch_trip_temp value to 75C. This is important so that PMC can shutdown the thermal sensor when CPU is in C-state and DTS temp <= pch_trip_temp. BUG=b:74089135 Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-02sb/intel/common: Fix conflicting OIC register definitionNico Huber
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location) makes some platforms use the wrong OIC register defi- nition. It was extended to 16-bit in the corporate version of ICH10. So let's give the new size and location a new name: EOIC (extended OIC). This only touches the systems affected by the mentioned change. Other platforms still need to be adapted before they can use the common RCBA definitions. Change-Id: If9e554c072f01412164dc35e0b09272142e3796f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/24924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-03-02mb/google/zoombini/variants/meowth: Enable NVMeBora Guvendik
Turn on pcie ports 9,10. Enable Root Port 9 and set up clkreq 3. BUG=b:72120814 TEST: Boot to OS via NVMe Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/23208 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02mb/hp: Enable additional ports at WWAN slot for ElitebooksIru Cai
2760p: enable PCIe 8470p: enable mSATA 8460p: enable PCIe, also add comments according to circuit diagram 2570p: comment for some USB ports Change-Id: Ib5209f2dfb249fca5bae89bc6da3b704c8e903dd Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/23357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-02mainboard/google/zoombini/variant/meowth: enable speed shiftNick Vaccaro
BUG=b:73817825,b:69011806 BRANCH=master TEST=Build and flash to meowth, verify cpufreq shows up in kernel for all cores : localhost ~ # find / -name "cpufreq" /sys/devices/system/cpu/cpu3/cpufreq /sys/devices/system/cpu/cpu1/cpufreq /sys/devices/system/cpu/cpufreq /sys/devices/system/cpu/cpu2/cpufreq /sys/devices/system/cpu/cpu0/cpufreq /sys/module/cpufreq /usr/share/laptop-mode-tools/modules/cpufreq Change-Id: I63242b2b049e37167c0d3b8eab630cb6e15a75fd Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/24902 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/google/reef/sand: Override USB2 phy settingsKatherine Hsieh
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-sand coreboot chromeos-bootimage Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/23879 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mainboard/google/meowth: Turn on DBC over USB3.0Lijian Zhao
Intel DCI (direct connect interface) allows debug Intel target using USB3.0 ports. It will support debug via USB stack (DCI Dbc) using USB3.0 only. BUG=None TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot image. Using DAL to halt/run CPU. Change-Id: I39e68dabfcb9e659733019334299e562eee3681d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-03-01mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa settingSeunghwan Kim
If switch to VT2 on nautilus, screen flicker appears. We found if we rollback the change of slew rate setting, then the flicker issue will be gone: https://review.coreboot.org/c/coreboot/+/22588 But nautilus board needs slew rate tuning to reduce EE noise, so we decided to change only SlowSlewRateForSa to 2 (Fast/8) instead of rollback the whole change of the CL:22588. It can remove the flicker on VT2. BUG=b:71397040 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/23877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-01mb/google/reef: Override USB2 phy settingsTim Chen
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-reef coreboot chromeos-bootimage Change-Id: Iab782ac6dfd81af839fff0e60e2b2460ce722733 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/23878 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/google/coral: add usb2 phy setting override for some variantsSheng-Liang Pan
Due to there are some chances USB devices can not be detected. USB2 port#1 and #4 PHY register need to be overridden for variants Santa/Lava/Blue/Bruce/Astronaut. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I401905685cc3078df657919b162272c3de320296 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/23881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-01mb/{amd/gardenia,google/kahlee}: Initialize GPIOs earlierJustin TerAvest
The GPIOs for PCIe reset and power enable for WLAN must be set up before amdinitearly for wlan to function. BUG=b:73898539 TEST=Boot, see WLAN controller in lspci Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/24916 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/scaleway/tagada: set SMBIOS Enclosure Type in KconfigJulien Viard de Galbert
Change-Id: I7acffcf3fc36742c77ce00b253f5b0a68d435798 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24911 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-28mainboard/google/zoombini: consolidate SPD makefilesNick Vaccaro
- consolidate commonality in meowth and zoombini's SPD makefiles into a common zoombini/spd/Makefile.inc - move all SPD hex files into zoombini/spd directory - move SPD_SOURCES definitions to variants/$(VARIANT_DIR)/Makefile.inc BUG=b:69011806,b:71776625 BRANCH=master TEST=Verify 'emerge-meowth coreboot' and 'emerge-zoombini coreboot' compile and boot successfully. Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23874 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-28mb/google/poppy/variants/nami: Enable elan touchscreenCrystal Lin
BUG=b:72062694 BRANCH=master TEST=Verify touchscreen on nami works with this change. Change-Id: Iaec71a11121b3d2849f12d18cda0e506be2ace09 Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28mb/google/octopus: Add LPDDR4 memory initRavi Sarawadi
Add LPDDR4 initialization support. BUG=b:73136980 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ieffcfa2f9d075eb0be13562f1a0c7ee503b005d9 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
Many generations of Intel hardware have identical code concerning the RCBA. Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-26mainboard/google/zoombini: enable 4 coresNick Vaccaro
BUG=b:70731385 BRANCH=master TEST='emerge-meowth coreboot chromeos-bootimage', flash image.serial.bin to meowth board, boot into kernel, and verify 4 cores are running. Change-Id: Ia233e41acd19b317f82433a5d41d84ea934a66c4 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23839 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-26mb/siemens/mc_bdx1: Avoid dereferencing a NULL pointerWerner Zeh
Coverity scan has found an error where a NULL pointer is dereferenced. The bug would happen if the devicetree does not contain a valid entry for PCA9538. In this case the code * if (dev->path.i2c.device == PCA9538_SLAVE_ADR) would dereference to a NULL pointer. This patch fixes this issue. Thanks coverity! Found-by: Coverity (CID 1386126: Null pointer dereferences (REVERSE_INULL)) Change-Id: I75e271d86c16fa3938420c43575ebba910f6a2fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/23808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-23mb/google/fizz: Enable PCIe port 11, 12Zhongze Hu
Our CFM daughter card would like to use individual PCIe lanes for two different devices on the card. dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b connector on fizz to meet the requirement: https://chrome-internal-review.googlesource.com/571936 We also need to enable the ports on device tree. BUG=b:72523836 TEST=none BRANCH=fizz Change-Id: Icded9850d833752680e0174b6c476e657817b319 Reviewed-on: https://chromium-review.googlesource.com/923867 Commit-Ready: Zhongze Hu <frankhu@google.com> Tested-by: Zhongze Hu <frankhu@google.com> Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924860 Commit-Queue: Shelley Chen <shchen@chromium.org> Tested-by: Shelley Chen <shchen@chromium.org> Signed-off-by: Zhongze Hu <frankhu@chromium.org> Reviewed-on: https://review.coreboot.org/23845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-02-22mb/google/kahlee/mainboard.c: Fix mainboard_picr_dataRichard Spiegel
While programming interrupts, a message "perhaps this device was defined wrong?" shows up twice. This is caused because some devices have interrupt programmed for APIC mode, but not for non-APIC mode. Fix mainboard_picr_data table by identifying devices programmed with value 0x1F while programmed differently on mainboard_intr_data table. Do so only for devices that are used by kahlee or interrupt required by old OS. BUG=b:70788755 TEST=Build and run kahlee, Verify that message disappears from serial output. Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-22mb/google/kahlee: Use GPIO macros for baseboardJustin TerAvest
This commit uses newly defined macros to make it easier to read which iomux function pads are being configured to use. TEST=Booted grunt, confirmed display backlight came on. BUG=b:72875858 Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22mb/google/kahlee: Correct bad gpio entryJustin TerAvest
There's no need to set the output enable here; this is already handled by the native function. I'm making this correction in this change to prevent the GPIO pin descriptions from getting confusing. BUG=b:72875858 TEST=Booted, confirmed S5_MUX_CTRL high with and without this change. Change-Id: I9e047be7169586c59892ef2bdab915683feeebda Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22mainboard/google/meowth: enable PCH iSCLKLijian Zhao
Turn on PCH iSCLK for meowth platform. BUG=None TEST=Boot up into OS and check register programming with iotools, the command is iotools mmio_read32 0xfdad8000, returned value is 0x03. Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23368 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22mainboard/google: Disable big, pit, and ryu ec buildsMartin Roth
The EC builds for nyan_big, peach_pit, and smaug (ryu) have been removed from the latest EC codebase, so don't try to build them by default anymore. Change-Id: I53901b32753c5b9b050f517bbf3f10b9071913d4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22mainboard/google/zoombini: Add config for meowth audioSathyanarayana Nujella
Add NHLT and dt support for meowth with max98373 amp. BUG=b:71724897 TEST='emerge-meowth coreboot' compiles correctly TEST=check SSDT and verify entries for max98373 TEST=check NHLT ACPI tables included blobs for max98373 Change-Id: Ic89bf669c7ab2ef39ce64e4da6a57a7069ee75f9 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-21mainboard/google/kahlee: Add tis_plat_irq_statusChris Ching
For variants that have a cr50 tpm, this enables faster polling when interacting with the tpm. BUG=b:72838769 BRANCH=none TEST=verified on grunt that irq is used and not timeouts for tpm Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428 Signed-off-by: Chris Ching <chingcodes@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-20mb/google/poopy/variants/nami: Add Pmax settingGaggery Tsai
This patch adds the Pmax setting in device tree. The Pmax is from MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W. BUG=b:72138778 BRANCH=None TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage & ensure the Pmax value is passed to FSP-S. Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-20mb/google/kahlee/OemCustomize.c: Disable bank interleaveRichard Spiegel
AmdInitPost returns AGESA_WARNING. This is because AGESA by default enables bank interleaving, while the HW does not meet the requirements for it. Disable bank interleaving, thus clearing AGESA_WARNING. BUG=b:73118857 TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost() returned AGESA_SUCCESS". Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-20mb/compulab: Mark Intense-PC as single board computer in board_info.txtJonathan Neuschäfer
Based on the pictures at http://www.fit-pc.com/web/products/intense-pc/, the Intense PC does not look like a laptop. In its documentation it is described as "mini-PC" or "Single Board Computer". This patches moves the Intense-PC into the correct category on the Supported Motherboards page. Due to thermal considerations, I have not removed the "select SYSTEM_TYPE_LAPTOP" in Kconfig. Fixes: de7f8d3a19 ("mainboard/compulab: add support for CompuLab Intense-PC") Change-Id: I4343306a2f82eed8211981cbd3b084f5d112d30b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-20mb/emu/spike-riscv: Move usage instructions into Kconfig helpJonathan Neuschäfer
... and fix them in the process. The Kconfig help text seems to be a slightly better place for such documentation than a comment in Kconfig. Change-Id: I4114e17ad9c486a9de059040b0e2821540c31aad Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-17mb/google/fizz: Wait until display is readyDaisuke Nojiri
Fizz fails to show pictures on a type-c monitor because VBIOS runs before DisplayPort link is ready. With this patch, when firmware needs to display something, Fizz calls google_chromeec_wait_for_display to make sure display is ready. The penalty is up to 2 sec per boot in dev and rec boot. Normal boot won't affected unless there is EC update. BUG=b:72387533 BRANCH=none TEST=Verify screens are displayed on Fizz as follows: 1. Put DUT in normal mode 2. Flash EC image to trigger EC sync (critical update) 3. Trigger manual recovery (insert) 4. Hit ctrl+d to switch to dev mode (to-dev) 5. Confirm to reboot (dev warning) 6. Warm reboot (dev warning) 7. Cold reboot (dev warning) 8. Flash EC image to trigger EC sync (critical update) 9. Trigger manual recovery (insert) Change-Id: I90befe94f93e13904987acda50b2598d034b0031 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-17soc/amd/stoneyridge: Normalize GPIO initJustin TerAvest
This makes the flow for GPIO initialization more closely follow that what is performed for other boards so that it's easier to read the flow (and stops relying on BS_WRITE_TABLES). BUG=b:72875858 TEST=Built and booted grunt, built gardenia. Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23679 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-16mb/google/{soraka,poppy,nautilus}: Set psys_pmax to 45WNaresh G Solanki
Soraka, Poppy & Nautilus are designed to operate at max power of 45 Watt. Hence set psys_max to 45W. BUG=b:66066340 BRANCH=None TEST=Build and boot soraka. Change-Id: If6f624733830b462329b5f539c20e2aea664143e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/23757 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-02-16mb/scaleway/tagada: Remove unused board_idJulien Viard de Galbert
Change-Id: I6175ce3d3ef739c4f503db826036ffe8feff9ddc Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16mb/scaleway/tagada: Update GPIO configurationJulien Viard de Galbert
Change-Id: Ia0293a0ec85c752686750dadb9730a159fd0c073 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16mb/scaleway/tagada: Remove eMMC configurationJulien Viard de Galbert
The board does no support eMMC so no need to configure it. Change-Id: If29009a09f39484b1da16fb650b4f9cbee2a6d19 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16mb/scaleway/tagada: Remove memory down optionJulien Viard de Galbert
The board does not have memory down, only 2 DDR4 Slots. Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16mb/scaleway/tagada: Update HSIO configurationJulien Viard de Galbert
Change-Id: I213ea13078fdc28489eb4572a084146df333a31d Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16mb/scaleway/tagada: Update device treeJulien Viard de Galbert
Change-Id: I1c42519dbe848b0bbcafa7f923d862ba7c9d8ed5 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16mb/scaleway/tagada: Copy intel/harcuvar and renameJulien Viard de Galbert
Change-Id: I6fc1f8393ce3f5ba6f52edad7cf8efa5524d2704 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16mb/google/zoombini/variants/meowth: enable FPMCU interruptVincent Palatin
Enable the micro-controller interrupt line as a real IRQ. BUG=b:71986991 BRANCH=none TEST=on Meowth, run 'ectool --name=cros_fp fpmode capture' and see the number of interrupts incrementing and the MKBP event happening. Change-Id: Ic0cf03d2a3508148b6482a5a595eaa213eff52c7 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/23769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-16google/gru: Fix GPIO_WP pull and polarity for ScarletJulius Werner
Turns out the write-protect GPIO polarity for Scarlet is different than for Kevin/Gru, and nobody ever told us. Also, it must not be configured with an internal pull-up or we'll not read the correct value. This patch fixes both issues. BRANCH=scarlet BUG=b:73356326 TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the right value in all cases. Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-15mb/google/poppy/variant/nautilus: Enable and configure DPTFSeunghwan Kim
This change enables DPTF and configures the policy. DPTF parameters were provided by internal power team. BUG=b:67877437 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/23731 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-15mb/intel/glkrvp: Add FPF_STATUS section in fmd fileHannah Williams
Read cse file was not getting cached and taking about 500ms on every boot. Change-Id: I8c92eefc64fe146c628d9c104d7dfb016204004c Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15mb/google/octopus: Add new boardHannah Williams
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp. TODO: Fix as per octopus schematic. Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23685 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-15siemens/mc_bdx1: Show mainboard hardware version on consoleWerner Zeh
Show mainboard version in the console log so that one can easily see it. Change-Id: I33bae8b340fce13c0cbe525521828929038b069a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/23750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15siemens/mc_bdx1: Enable PCA9538 I/O expanderWerner Zeh
The I/O expander on the mc_bdx1 is used to get the hardware version of the mainboard. This patch enables the chip driver for the I/O expander. Change-Id: I98c667fe4dccf0698ab4cb5ede6082f020c70ec6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/23749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-14mb/*/spd: Use normal binary numbers (0b0010) instead of special format (2b0010)Jonathan Neuschäfer
This format (one hex digit, followed by 'b', followed by binary digits) is arguably useful, but also confusing. Use the more common format instead. Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-13mb/google/poppy: Fix the SPD for samsung_dimm_K4A8G165WBFurquan Shaikh
Original SPD provided by the vendor had bytes after 254 shifted by 16 bytes. This change fixes the SPD data based on the latest details received from the vendor. BUG=b:72749394 TEST=Verified that the device with this memory part boots to OS fine. Also, mosys is able to dump the right memory information. Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12mainboard/google/zoombini/variants/meowth: enable touchscreenNick Vaccaro
BUG=b:69011806, b:72179988 BRANCH=master TEST=Verify touchscreen on meowth works with this change. Change-Id: Iad3f0b77a02552266435e523fdbb74b14ada101a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/23551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-02-12google/kahlee: Select HAVE_ACPI_RESUMEMarshall Dawson
TEST=Run powerd_dbus_suspend and resume with button press BUG=b:69614064 Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22732 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12google/snappy: enhance BigDaddy USB#2 2.0 strengthKevin Chiu
Fine tune 14" BigDaddy USB#2 2.0 strength: PERPORTPETXISET: 7 PERPORTTXISET: 1 IUSBTXEMPHASISEN: 3 PERPORTTXPEHALF: 0 this value could have USB#2 2.0 EA/function pass. BUG=b:72922816 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I0ea1b966b7c02c95bf0ea1138a5629fd3b576439 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23649 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-11mb/google/fizz: Set SATA GPIOs in bootblockShelley Chen
Previously, we were seeing device boot into the recovery screen with error code 0x5a. This was root caused to the SATA GPIOs (specifically DEVSLP) not being initialized early enough, causing the SATA 1 link detection to time out and the device to reboot into recovery with 0x5a instead of booting into the OS as usual. BUG=b:69715162 BRANCH=None TEST=after flashing BIOS, set gbb flags to 0, then type reboot from the OS. Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-10mb/google/poppy/variants/nautilus: set oem_id, oem_table_id fields of ↵Naveen Manohar
acpi_header_t This change makes the Nautilus platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:68686020 TEST=Build, booted nautilus board. Verified kernel reads new strings. Change-Id: I041f2838f07a2525be7a28fdc69b7f1af46d16f1 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/23648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-10mainboard/google/meowth: Enable ECT againLijian Zhao
Previously ECT was disabled in commit 22401, on D0 stepping system and FSP version 7.x.20.52, disabling ECT will cause memory training failure and the system is stuck at post code 00D5h. BUG=b.72473063 TEST=Apply patch and build coreboot image, flash into meowth P0 system with D0 stepping silicon installed, system can pass memory training and boot up into OS. Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-10mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_tKaiyen Chang
This change makes Nami platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:70646770 TEST=Verify kernel reads new strings. Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://review.coreboot.org/23670 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10mb/google/grunt: Add ADAU7002 to devicetreeDaniel Kurtz
Add an entry to the grunt devicetree defining the ADAU7002 PDM-to-I2S converter. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: I90b59ec64f4b841932db42b8a8970ed924283613 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10mb/google/kahlee: Add grunt audio codecs to devicetreeDaniel Kurtz
Remove manually written asl entries for grunt's DA7219 and MAX98357A audio codecs, and replace them with equivalent devicetree entries. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: Ia658c54a28a5363aabb4c50478adaca1f46d166a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-08mb/intel/kblrvp: Enable Kabylake RVP8V Sowmya
Add support for KBL RVP8 board * Add KBL RVP8 support in Konfig. * Add KBL RVP8 config option in make menuconfig. * Add descriptor and ME binary paths for RVP8 in Kconfig. * Add RVP8 board name Kconfig.name. * Add devicetree.cb for RVP8 in the variants path. * Add gpio.h for RVP8 in variants/include/variant path. TEST= Build and boot RVP8. Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23383 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-08mb/google/poppy/variants/nami: Revise AC/DC loadlinesGaggery Tsai
This patch revises AC/DC loadlines from VRTT reports. +----------------+-------+-------+-------+-------+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------+-------+-------+-------+ | AcLoadline | 11 | 2.4 | 3.1 | 3.1 | | DcLoadline | 10 | 2.46 | 3.1 | 3.1 | +----------------+-------+-------+-------+-------+ BUG=b:72351128 b:72129954 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage & ensure the settings are passed to FSP. Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07mb/google/fizz: Set Pmax to 120 for all SKUsShelley Chen
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4 (71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) + ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W. BUG=b:71594855 BRANCH=None TEST=Make sure correct pmax value is being passed into fsp Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23633 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2018-02-07google/kahlee/grunt: Fix 2 device specific variablesAkshu Agrawal
* micbias_lvl -> micbias-lvl * mic_amp_in_sel -> mic-amp-in-sel BUG=b:71875600 TEST=Checked in kernel the values are set Change-Id: Ife7e8cdd835cc256cd8265593a94df84a510cebb Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/23603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07mb/amd/gardenia: Remove cmos.layoutRichard Spiegel
CMOS layout is not used and can be removed. A change to Kconfig is needed in order not to break the build. BUG=b:64207749 TEST=Build gardenia. Change-Id: I24a71490777b101b069175460f3715ec3ff78240 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07mb/google/poppy/variants/poppy: Enable EC_ENABLE_SECOND_BATTERY_DEVICENicolas Boichat
BRANCH=none BUG=b:65697620 TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are present, data is valid. Change-Id: I869bf08341b83f359066709e1e9c03af99482b2c Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/23599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-02-07mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22Furquan Shaikh
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to match the latest schematic changes). Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is removed from deep_sx_config as well. BUG=b:72697650 TEST=Verified: 1. Wake-on-wifi works. 2. Device is able to enter G3 without WAKE# pin causing unwanted wakes from deep S5. Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23594 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-06google/gru: Add another 512KB to the COREBOOT FMAP regionJulius Werner
With the new extra detachable UI elements, we're running out of space in Scarlet's RO CBFS. Thankfully, the GBB is still massively overdimensioned, so we can steal another half MB from there. This patch changes the FMAP for some boards that have already had production firmware releases. However, all the new changes are to the RO parts of the FMAP, so there shouldn't be a way this could cause a problem for updates. Change-Id: Iec182de3e894e56fec2a64b034c0ca65d78a5522 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06mb/google/kahlee: Fix grunt I2C rise/fall timesJustin TerAvest
I2C bus rise/fall times were measured as follows. Signals were generated with: - bus 0: manual i2c driver in depthcharge - bus 2,3: i2cdetect -r <bus_number> and then measured manually with an oscilloscope. BUG=b:72442912 Change-Id: I291e144249271ec34a93417398e54e68b8e21e23 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06mb/google/kahlee: Remove cmos.layoutRichard Spiegel
CMOS layout is not used and can be removed. A change to Kconfig is needed in order not to break the build. BUG=b:64207749 TEST=Build kahlee. Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-06mainboard/broadcom/blast: Remove unnecessary braces {}Elyes HAOUAS
Fix coding style Change-Id: I1b6913f9fe97e42836a6698645d0d380ceecec0d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23523 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06mb/asus/m2v-mx_se: Add `cmos.default`Paul Menzel
Add `cmos.default` to get rid of four seconds in romstage. Choose 8 MB for size for video RAM. Order the entries like in `cmos.layout`. Change-Id: If2dcc266f6f061807401b62647124ce96e9a3802 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/23468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-02-06mb/google/eve: Enable HotPlug on PCIe root port for WiFiDuncan Laurie
Enable HotPlug for the PCIe root port that the WiFi device is on so the OS can re-train the link without needing a reboot if it goes down unexpectedly at runtime. BUG=b:72417777 TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux that it is identified as a HotPlug capable root port. Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23512 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-06google/kahlee: Initialize non-early i2c buses in mainboard_initDaniel Kurtz
Initialize non-early i2c buses in ramstage. BUG=b:69407112 TEST=Boot depthcharge w/ CLI enabled on grunt. devbeep => plays beep BRANCH=None Change-Id: I634a7a823cc393243841dbd55e52abe3f0e72c5a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23554 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06mb/google/fizz: Determine PsysPl3 and Pl4 valuesShelley Chen
Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid brownouts. According to Intel doc #560604, page 74, the max time window is 64ms (code=6) and the min duty cycle we can set is 4%. BUG=b:71594855 BRANCH=None TEST=Boot to OS and check MSRs using iotools for expected values Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-06mb/google/nautilus: Work around the power issue of MIPI and USB camerasAndy Yeh
On EVT, the USB and MIPI cameras share the same power source. As a result, when the MIPI camera driver turns off the camera once probed, USB camera will be disconnected. To make USB camera work on EVT devices, we will need a hack in coreboot to leave the camera power always-on. BUG=b:72839352 TEST: Verified the MIPI and USB camera function on DUT board TODO: This power issue will be fixed on DVT build. Will revert this patch once confirmed power sources for MIPI and USB camera could be supplied individually. Change-Id: Icaaf7e17447492f2e2f2d03eb9a35bcc53667f28 Signed-off-by: Andy Yeh <andy.yeh@intel.com> Reviewed-on: https://review.coreboot.org/23546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andy Yeh
2018-02-05mb/google/fizz: Get OEM ID and SKU ID from ECDaisuke Nojiri
This patch makes coreboot fetch OEM ID and SKU ID from EC. If it fails, it falls back to GPIO pins. BUG=b:70294260 BRANCH=none TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz. Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23548 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-05mb/intel/glkrvp: Set S0ix lazy wake maskShamile Khan
Enable S0ix wake mask programming from coreboot using unified host event programming interface. BRANCH=none BUG=none TEST=Verify masks with ec hostevent command on S0, S3, S5 and S0ix. Also check that lidclose/lidopen command from EC console wakes system up from S3 or S0ix. Change-Id: I60343aaa9e0ddfd38d42b6d0aa2820e2fd880fb7 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23453 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-05google/lars: Turn on keyboard backlight in romstageJenny TC
Cherry-pick from Chromium: a60ac10 [Lars: Turn on keyboard backlight in romstage] Use the keyboard backlight to provide indication that the system is booting. This is useful for determining that a system is in S0 and is running BIOS code. TEST=boot on Lars and see keyboard backlight come on early Original-Change-Id: I4fede6cff85f4487cedfbccf6cc24c6380d905e0 Original-Signed-off-by: Jenny TC <jenny.tc@intel.com> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I4b1fed10d9bd1ae1b265e848417836f816f252f3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars,lili: Update GPIO mappingdavid
Combination of several commits from Chromium tree: 949037c [Lars: coreboot GPIO changes for EVT] c286789 [Lars: Set USB Type A current limit to 2A] 0f1b26d [lars: set BOOT BEEP GPIO GPP_F_23 to output and Low] 4a0650d [Lili: Support touchscreen] Disable unused GPIOs based on schematic and adds GPIO mappings for HSJ_MIC_DET, PCH_BUZZER and AUDIO_INT_WAK. Set GPIOs USB_A0_ILIM_SEL & USB_A1_ILIM_SEL low to enable 2A charging from the USB Type-A port. GPP_F_23 is set to NC currently and is floating, causing the on-board speaker to have no audio or the audio has noise; set to output/low. These commits bring lars' GPIO mapping in line with the Chromium tree. Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6 Original-Change-Id: I328a8be22dc59492477cbe362a5d5b94aa80a397 Original-Change-Id: I253e55bf2b423363a00347778cabaa4184d85aec Original-Change-Id: I761f7c5ea5fc7a173c07a8c37da1338a1b2cd269 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Tested-by: Balaji Manigandan <balaji.manigandan@intel.com> Original-Tested-by: Kuen Liu <kuen.liu@quantatw.com> Change-Id: Ic2d188fbf913a11fbf6ad1f0eb3a5e72ba4cb1cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: Update the MAINBOARD_FAMILY string in KconfigDuncan Laurie
Cherry-pick from Chromium: 99cd8f8 [lars: Update the MAINBOARD_FAMILY string in Kconfig] This string was left at the default for kunimitsu and should be updated to indicate the proper mainboard. Original-Change-Id: Icc0e162d57242e7b0610fb570ef1a8a45ee16e4f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia4b70227c8cfdfe939e40ea6258d494337a2907b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars,lili: Update SPD DataMatt DeVillier
Combination of several commits from Chromium tree: 3b875a2 [Lars: Update Memory ID for DVT board] b6d7c63 [Lili: Update Memory IDs] f203f99 [Lili: Add new SPD for Hynix H9CCNNN8GTALAR-NUD] a6571bf [Lili: Update Memory IDs] 80e1841 [Lili: Update Memory IDs] 58d4487 [Lili: Fix memory string show error in spd data] These commits bring lars' SPD data in line with the Chromium tree. Original-Change-Id: I54d0e6d2bbe86d5dc2ee5825f332d36abfa99084 Original-Change-Id: I9431393f369a1d2870bdabba1fc55d9cefae5c39 Original-Change-Id: I3b325a1801f49109429eb647d8d98a5537ce1b7b Original-Change-Id: Ie8a32d8a26ea1054e2df8432084a95d1cb03f991 Original-Change-Id: I64c73950e3bea57b6c5a90257211b3d6d7f1baab Original-Change-Id: I0e425fa4f0bae544680d5522c2e05a4f7a3be95a Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I7cc9b01012b0b9ed72804192bb5953243fc859b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: Add sdmode-delay property for max98357aMatt DeVillier
Adapted from Chromium commit: af3ec09 [Lars: Add sdmode-delay device property for maxim98357a] Add "sdmode-delay" as a device property for the maxim98357a codec. This speaker amp requires both SFRM & BCLK to active and stable before it is unmuted. If there is a BCLK and no SFRM, that results in a pop noise. Adding a configurable delay parameter for all Skylake platforms to allow sufficient time for the BCLK & SFRM on I2S to be stable before the amp unmutes itself to avoid a pop noise at the start of playback. Setting the delay to 5ms since the observed delay between SFRM and unmuting of the amp is around 2ms. Adaptation needed to account for parameters having moved from mainboard.asl to devicetree in upstream tree. Original-Change-Id: I1fff4f86ff816e907553e7a6f1d05713f9d85084 Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8a1c52ccdb08df9a4ab293e12bb266309e08737b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: update device properties for Nuvoton codecMatt DeVillier
Adapted from Chromium commit: 848ee3a [Lars: Add device properties for Nuvoton codec] Update sar-threshold, sar-compare-time, sar-sampling-time properties to match values in lars' Chromium branch. Adaptation needed to account for parameters having moved from mainboard.asl to devicetree in upstream tree. Original-Change-Id: Id0c28e50406a29e6f33d04ca78fd2a3e3974fa90 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars,lili: Set new thermal parametersdavid
Cherry-pick from Chromium: 55c0eb3 [Lili: Set new thermal parameters] Set new parameters of DPTF for both Lars and Lili. The acoustic will have higher 1.6dB in transition mode, when using Lili fan table on Lars. Original-Change-Id: I730ac483e2a6d43c8dcfe94da6761194c14f3163 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Change-Id: I3bf16db43bb90a542c6526f3bc891f820da00ca0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: Update DPTF settingdavid
Cherry-pick from Chromium: dff141b [Lars: Update DPTF setting] Original-Change-Id: I1f2686eced07c7fb1bde3c660df6d6efac607695 Original-Signed-off-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifd3e844688588b6d1c69459f75c0d7da93ba3688 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05mb/google/kahlee: Enable wlan card so it can be detectedMartin Roth
The wifi card was not being powered, and was being held in reset during PCI enumeration, so it was not being brought up. BUG=b:72738963 TEST=Verify wlan card shows up in lspci Change-Id: I5a1e83298af35aa80c67c75cd6ec0a2c3213891e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23552 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-02google/gru: Use newer version of Innolux P097PFG panel init codeLin Huang
There is a line artifact in the lower third of the display with the current initialization code. So update it with code provided by Innolux to fix this issue. BUG=b:69689064, b:72191820 TEST=boot on dru with an Innolux panel and artifact line disappear. Change-Id: I9679c4f7f706fd6cd2e1dba7ec79e772fe3f227a Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02mb/google/kahlee/mainboard.c: Create mainboard_pirq_dataRichard Spiegel
When booting kahlee, there's an error message: "Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist". This is generated by write_pci_cfg_irqs due to missing mainboard_pirq_data. BUG=b:70788755 TEST=Build and boot kahlee. Warning message must be gone. Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-01mb/google/kahlee: always load and run display opromAaron Durbin
The kernel requires the display oprom is loaded *and* ran in order for the kernel to not panic. Therefore, select the correct settings such that normal mode works for Chrome OS. BUG=b:72400950 Change-Id: Ibae5bc6b382cbe71a55c2386a24bb420cb8f313f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23506 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31mb/google/kahlee: Add grunt cr50 supportJustin TerAvest
This commit adds an entry for H1/Cr50 into the devicetree for setting up ACPI entries for H1 communication. BUG=b:69250772 TEST=See probe messages in dmesg Change-Id: Id55ce3364ea4acdb62782758e5bcb2a167286cb9 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23514 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31mb/google/kahlee: Add grunt trackpad in devicetreeJustin TerAvest
This commit removes a manually written asl file in favor of configuring the trackpad through devicetree. BUG=b:72121803 TEST=cat /proc/interrupts with trackpad connected Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23508 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 23:23:43 +0000