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The GPIO for EEPROM write-protect should be configured early, before
romstage. This change configures that pad earlier. This pad is the same
on the existing Octopus schematics.
BUG=None
TEST=None
Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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We are enabling at the kernel level, but that is triggering an issue
where FSP expects it to be disabled so it forces a cold reboot on
every warm reboot, clearing the ramoops logs. Enabling in BIOS so it
matches what the kernel expects.
This is the same change that were done for eve:
https://review.coreboot.org/#/c/22449/
BUG=None
BRANCH=None
TEST=echo PANIC > /sys/kernel/debug/provoke-crash/DIRECT
check for /dev/pstore/console-ramoops
Change-Id: Icd0bd01f5aee4c89f503eebba0808a1f3059e739
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The GPIO programming of configure_stoneyridge_UART() can be done by the early
GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart()
became redundant. Remove procedure configure_stoneyridge_uart().
BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.
Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25192
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO_149 is used as ESPI clock feedback and configuring it as a GPO
results in EC communication failure. This change removes the
configuration of GPIO_149 as GPO in ramstage so that it remains
configured for ESPI (as it was when AP came out of reset).
BUG=b:75348718
Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1) Set the critical temperature threshold to 100C to match changes
on other boards. This is intended to reduce DPTF-initiated thermal
shutdowns before it has had a chance to react.
2) Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.
BUG=b:67459049
BRANCH=eve
TEST=manual performance/power testing on Eve hardware
Change-Id: Ib660dcb25422fea0aa692fac5ba65b49808965ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Use gpio_keys driver to add ACPI node for pen eject event. Also
setting gpio wake pin for wake events.
BUG=b:73121017
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: I5d87d938ac3a4e52e676850b9d8b80e83726275d
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Touchscreen power enable for Nami has moved from GBB_C22 to GPP_B4 in
the latest schematics.
BUG=b:74347464
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: I3b1794d44f25c0d42d082d63b9e3ec3dfcef7528
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25154
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Octopus uses MAX98357A speaker amplifier and DA7219 codec.
Add device tree entries and Kconfig settings for these
components.
BUG=b:73292699,b:73230879
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I27b5113677a8bd44dbbae587e27616d9e0b90d7f
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25117
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change uses gpio_keys driver to add ACPI node for pen eject event.
BUG=b:74413116
TEST=Verified using evtest that pen eject event results in events as
expected.
Change-Id: I6019d633f4337137bb9fbba770040cb5b30da773
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/25147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix the IRQ configuration: it must be level-sensitive not edge-sensitive
(and match the GPIO configuration).
BUG=b:71986991
BRANCH=none
TEST=on Meowth, /proc/interrupts shows 'IO-APIC 46-fasteoi chromeos-ec'
then run 'ectool --name=cros_fp fpmode fingerup' and see the number of
interrupts incrementing and the MKBP event happening.
Change-Id: Iba8cff21d637fe6bf4ef5152fc01aaf98906477d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/25110
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable System Agent dynamic frequency support by default.
BUG=None
TEST=Build and flash with debug version FSP, check SaGv in serial print
to be set to "4".
Change-Id: I7dd29db206b06e600407bb0b1d0bc7530f4ac93e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25093
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This creates a yorp variant for octopus; nothing too interesting now,
just picks up values from the baseboard.
BUG=b:74443669,b:74067452
TEST=Build
Change-Id: I55af8f02d33138a3b6bab7860a665e3deb5595c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25086
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables SAR configs when building with CHROMEOS option.
BUG=b:74439919
Change-Id: I11a8fa04a77f688ed288780f2c605b8ac701f5a9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Since nami proto did not have any external pull on MEM_CONFIG_4, use a
weak internal pull down before reading it.
BUG=b:74420123
TEST=Verified that the value read for MEM_CONFIG_4 is correct on nami.
Change-Id: I45989d2ca35b863f391baba9e2f2e602033217d4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The current lpddr4 skus entries do not match the RAMID table in the
schematic. This commit updates that so they are consistent. Thankfully,
the values are the same as for glkrvp, so I just copied from there.
BUG=b:74392818
TEST=None
Change-Id: I2e63ea0b27ef58038e5a37949c31a808989c98c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The following gpios are no longer needed and are now configured as
no-connects : GPP_C6, GPP_H4, GPP_H5
BUG=b:74406599
BRANCH=master
TEST=none
Change-Id: I55769336195db0e57dfbaf5b5770e15050138341
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25070
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make sure that fields that are not updated in
variant_memory_params keep a default value of 0.
In particular, use_sec_spd is intended to have a default value of
0 on all platforms. Without this patch, a random value is used
and all boards (except nami) get stuck on boot.
BRANCH=poppy
BUG=b:74439917
TEST=Nautilus and poppy can boot, and do not get stuck at
"CBFS: 'sec-spd.bin' not found."
Change-Id: I06c6511625de930903ae13788bdcd27667a17886
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/25101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add left and right semtech SAR sensor.
BUG=b:74363445
TEST=Test on meowth, alongside 24962.
Check in sysfs that SX9310 is presented:
/sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:09/SX9310:00
/sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:0d/SX9310:01
Change-Id: I017db1105800003b312e75dc7e1e27be535a457a
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/25062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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we had disabled software sync for bringup - we now have enough
functionality in place to turn on software sync.
Change-Id: Ib7f5a24ed8a47cb44b3f505e3cd49e0cb6931dc0
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23630
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change SECONDARY_SPD_SOURCES to SEC_SPD_SOURCES as that is what the
spd target expects.
TEST=Verified that sec-spd.bin is present in coreboot.rom
Change-Id: I4299df1eb9009095ef899c5b83823750dfc715d8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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GPIO 40 isn't currently being used, so set it to be an input.
BUG=b:73387647
TEST=Build & boot grunt
Change-Id: I5a04cbab1276cd20e7f9c7576e8111089dd2b155
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The Bayhub part is not used on proto with board_id 0, so disable it.
BUG=b:74248569
TEST=Build & boot Grunt. Bayhub part is disabled.
Change-Id: I635356d41bab637726594d403d66dde730f12256
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Return proper SKU IDs so that mosys can return the proper variant.
BUG=b:74059798
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: I665fa491de6e277fea5cc071b1f04a21317bccba
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This #define tells superio.asl to add a "PNP0501" "Plug and Play
16550A-compatible COM port" entry to kahlee's ACPI tables.
The EC on kahlee boards do not provide a "Serial Port 1" that should
be exposed via ACPI to the OS. In fact, this entry confuses the
kernel and in some cases can cause it to try to redirect output to a
non existing port.
BUG=b:74200887
TEST=Deploy to grunt. Boot kernel with SERIAL_PORT_DFNS undefined and
"earlycon=uart,mmio32,0xfedc6000,115200,48000000" on the kernel
command line, and with an image with serial console enabled.
=> System boots with (kernel) serial console enabled, starting from
0.00 (earlycon), with no gaps in its output, and serial console
also allows logging in.
Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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CBI abbreviates Cros Board Info.
BUG=b:74177699
BRANCH=master
TEST=Verify CPU log shows expected SKU ID on Nami.
Change-Id: I42dd177de8c49cf3c122c2ebb1fcf42e5ba4cd75
Signed-off-by: amanda_hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/24996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Hardware updates have suggested we need to configure the K&D panel's
power sequence in software, not in hardware. Without this change, K&D
panels will no longer power on correctly and will instead display a
black screen.
Per K&D's suggestion, we tweak these two commands. From the little HW
docs I have, this looks like it's:
(Address 0xB7, Value 0x02) -> set BC_CTRL=bit(1) (Back light control) to
1
(Address 0xF1, Value 0x22) -> change GPO2_SEL=bits(0:3) from
MIPI_TE(0001b) to BC_CTRL (0010b)
BRANCH=scarlet
BUG=b:73133861
TEST=KD display with and without HW fix on Scarlet
Change-Id: Ia076a378b10417dd9891746f9bc1086360a0f6e6
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://review.coreboot.org/25023
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures the gpios for all the gpio communites.
Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Per vendor datasheet, corrected linkfreq of imx258 as
{633600000, 320000000}
BUG=None
BRANCH=None
TEST=Verified the MIPI and USB camera function on DUT board
Change-Id: Ie5beed44c15e26b9f82cb305a91b8ff90a9ea867
Signed-off-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-on: https://review.coreboot.org/24990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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We want to report the board SKU via the SMBIOS tables. Add support for
this, obtaining the ID itself from the EC.
BUG=b:74175244
BRANCH=none
TEST=manually on grunt with another CL:
mosys platform sku
0
Change-Id: I9e08d64df3f89d3703de047dd9ec8e1717e6b212
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/25011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add WACOM EMR in devicetree I2C #2.
BUG=b:72062737
BRANCH=master
TEST=Verify EMR on nami
Change-Id: Icbe809a48959e5749262aeb1b89b09c4bdafbbc2
Signed-off-by: jasper lee <jasper_lee@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/24997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds SPD files for memory IDs 7 on nami.
BUG=b:73807138
Change-Id: I25fe3b347057eea75c58bfb88df41bdb28cc1460
Signed-off-by: jasper lee <jasper_lee@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=b:69011806
BRANCH=master
TEST=none
Change-Id: I2ea44b03336b901af68f9092f3386b42d8516b72
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/24962
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per the latest schematics, this change configures GPP_B0 as wake
source for WLAN.
BUG=NONE
BRANCH=master
TEST=emerge-nautilus coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b
Reviewed-on: https://review.coreboot.org/23526
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is done by overriding the weak functions from smbios.c
Some values are hardcoded as they are characteristics of the
Tagada system. Other are retrieved from the BMC through the
bmcinfo interface.
Change-Id: I9b08660c6677864f5c96c66002b35bd05a366053
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23843
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idd93b64ef91a569127a0713fdb499dff2a1f11db
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I0093cfafe7eaa4a4381e67c9b871fdf28abc470d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This interface gives access to configuration information stored in flash
by the Tagada BMC before booting the SoC.
Change-Id: I4351aa11b08bdf65e14706b261c532bbf8837aed
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Alkali will use LPDDR3, so need to have Nami support both
DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO.
BUG=b:73514687
BRANCH=None
TEST=None
Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add spd files for LPDDR3 based on info received from factory team.
BUG=b:73287172
BRANCH=None
TEST=None
Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Alan(11")/BigDaddy(14") right type-A(port#2), CCD(port#4) are
occasionally undetectable. USB 2.0 phy needs an override to enhance
drive strength.
right type-A port#2
PERPORTPETXISET: 4
PERPORTTXISET: 4
IUSBTXEMPHASISEN: 1
PERPORTTXPEHALF: 0
CCD port#4
PERPORTPETXISET: 7
PERPORTTXISET: 7
IUSBTXEMPHASISEN: 1
PERPORTTXPEHALF: 0
BUG=b:72922816
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I2b18c11709280d00ec3a6ef10f93a416acb4fb45
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/24969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Some type-c monitors do not immediately assert HPD. If we continue
to boot without HPD asserted, Depthcharge fails to show pictures
on a monitor even if HPD is asserted later.
Also, if an HDMI monitor is connected, no wait is needed. If only
an HDMI monitor is connected, currently the API always loops until
the stopwatch expires.
This patch will make the AP skip DisplayPort wait loop if it detects
an HDMI monitor. And if an HDMI monitor is not detected, the AP will
wait for DisplayPort mode (like before) but also its HPD signal.
This patch also extends the wait loop time-out to 3 seconds.
BUG=b:72387533
BRANCH=none
TEST=Verify firmware screen is displayed even when a type-c monitor
does not immediately assert HPD. Verify if HDMI monitor is connected,
AP does not wait (and firmware screen is displayed on HDMI monitor).
Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot
and should not be used as a UART device. coreboot is setting the
pins to GPIO Mode but FSP is re-configuring them for Native Mode
and the behavior is unexpected when the kernel tries to initialize
the UART device.
The UART 0 device is PCI function 0 so it needs to be enabled for
other functions to be visible to the OS so it can't just be disabled.
Instead, set the device to PchSerialIoSkipInit so that FSP will not
change the pin state.
BUG=b:73006317
TEST=Tested with add-in card on fizz hardware to ensure the pin state
does not change when FSP runs or the kernel boots.
Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This reverts commit 2e81f394cffc6f1993a5f004356ed35f6064fe48, as it will
have side effect that will make system shutdown failure. System will not
enter S5 sleep state, instead a global reset will be generated.
Once camera driver ACPI framework ready, isclk programing will be moved
into APCI method, in _PS3, isclk will be turned off to save power.
BUG=b.72532565
BRANH=master
TEST=Apply the changes and flash coreboot, on meowth devices, issue
"halt" in OS stage, system can shutdown successfully.
Change-Id: If35697911f97c524d9b52bdf4dae5c9ef1cc8618
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds support for variants to use secondary SPD if
required. This enables a variant to have different types of memory
supported using the same image.
BUG=b:73514687
Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Similar to Soraka, this change sets the pch_trip_temp value to
75C. This is important so that PMC can shutdown the thermal sensor
when CPU is in C-state and DTS temp <= pch_trip_temp.
BUG=b:74089135
Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a
common location) makes some platforms use the wrong OIC register defi-
nition. It was extended to 16-bit in the corporate version of ICH10.
So let's give the new size and location a new name: EOIC (extended OIC).
This only touches the systems affected by the mentioned change. Other
platforms still need to be adapted before they can use the common RCBA
definitions.
Change-Id: If9e554c072f01412164dc35e0b09272142e3796f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/24924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Turn on pcie ports 9,10. Enable Root Port 9 and set up clkreq 3.
BUG=b:72120814
TEST: Boot to OS via NVMe
Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/23208
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
2760p: enable PCIe
8470p: enable mSATA
8460p: enable PCIe, also add comments according to circuit diagram
2570p: comment for some USB ports
Change-Id: Ib5209f2dfb249fca5bae89bc6da3b704c8e903dd
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/23357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
BUG=b:73817825,b:69011806
BRANCH=master
TEST=Build and flash to meowth, verify cpufreq shows up in kernel
for all cores :
localhost ~ # find / -name "cpufreq"
/sys/devices/system/cpu/cpu3/cpufreq
/sys/devices/system/cpu/cpu1/cpufreq
/sys/devices/system/cpu/cpufreq
/sys/devices/system/cpu/cpu2/cpufreq
/sys/devices/system/cpu/cpu0/cpufreq
/sys/module/cpufreq
/usr/share/laptop-mode-tools/modules/cpufreq
Change-Id: I63242b2b049e37167c0d3b8eab630cb6e15a75fd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/24902
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need
to be overridden.
port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
BUG=b:72623892
BRANCH=master
TEST=emerge-sand coreboot chromeos-bootimage
Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/23879
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Intel DCI (direct connect interface) allows debug Intel target using
USB3.0 ports. It will support debug via USB stack (DCI Dbc) using USB3.0
only.
BUG=None
TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot
image. Using DAL to halt/run CPU.
Change-Id: I39e68dabfcb9e659733019334299e562eee3681d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
If switch to VT2 on nautilus, screen flicker appears. We found if we
rollback the change of slew rate setting, then the flicker issue will
be gone: https://review.coreboot.org/c/coreboot/+/22588
But nautilus board needs slew rate tuning to reduce EE noise, so we
decided to change only SlowSlewRateForSa to 2 (Fast/8) instead of
rollback the whole change of the CL:22588. It can remove the flicker on
VT2.
BUG=b:71397040
BRANCH=master
TEST=emerge-nautilus coreboot
Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/23877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need
to be overridden.
port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
BUG=b:72623892
BRANCH=master
TEST=emerge-reef coreboot chromeos-bootimage
Change-Id: Iab782ac6dfd81af839fff0e60e2b2460ce722733
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/23878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Due to there are some chances USB devices can not be detected.
USB2 port#1 and #4 PHY register need to be overridden for variants
Santa/Lava/Blue/Bruce/Astronaut.
port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
BUG=b:72623892
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: I401905685cc3078df657919b162272c3de320296
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/23881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The GPIOs for PCIe reset and power enable for WLAN must be set up before
amdinitearly for wlan to function.
BUG=b:73898539
TEST=Boot, see WLAN controller in lspci
Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/24916
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I7acffcf3fc36742c77ce00b253f5b0a68d435798
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24911
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
- consolidate commonality in meowth and zoombini's SPD makefiles into
a common zoombini/spd/Makefile.inc
- move all SPD hex files into zoombini/spd directory
- move SPD_SOURCES definitions to variants/$(VARIANT_DIR)/Makefile.inc
BUG=b:69011806,b:71776625
BRANCH=master
TEST=Verify 'emerge-meowth coreboot' and 'emerge-zoombini coreboot'
compile and boot successfully.
Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23874
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:72062694
BRANCH=master
TEST=Verify touchscreen on nami works with this change.
Change-Id: Iaec71a11121b3d2849f12d18cda0e506be2ace09
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/23872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add LPDDR4 initialization support.
BUG=b:73136980
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: Ieffcfa2f9d075eb0be13562f1a0c7ee503b005d9
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/23832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Many generations of Intel hardware have identical code concerning the
RCBA.
Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
BUG=b:70731385
BRANCH=master
TEST='emerge-meowth coreboot chromeos-bootimage', flash
image.serial.bin to meowth board, boot into kernel, and
verify 4 cores are running.
Change-Id: Ia233e41acd19b317f82433a5d41d84ea934a66c4
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23839
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Coverity scan has found an error where a NULL pointer is dereferenced.
The bug would happen if the devicetree does not contain a valid entry
for PCA9538. In this case the code
* if (dev->path.i2c.device == PCA9538_SLAVE_ADR)
would dereference to a NULL pointer.
This patch fixes this issue. Thanks coverity!
Found-by: Coverity (CID 1386126: Null pointer dereferences (REVERSE_INULL))
Change-Id: I75e271d86c16fa3938420c43575ebba910f6a2fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Our CFM daughter card would like to use individual PCIe lanes for two
different devices on the card.
dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b
connector on fizz to meet the requirement:
https://chrome-internal-review.googlesource.com/571936
We also need to enable the ports on device tree.
BUG=b:72523836
TEST=none
BRANCH=fizz
Change-Id: Icded9850d833752680e0174b6c476e657817b319
Reviewed-on: https://chromium-review.googlesource.com/923867
Commit-Ready: Zhongze Hu <frankhu@google.com>
Tested-by: Zhongze Hu <frankhu@google.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924860
Commit-Queue: Shelley Chen <shchen@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/23845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
While programming interrupts, a message "perhaps this device was defined
wrong?" shows up twice. This is caused because some devices have
interrupt programmed for APIC mode, but not for non-APIC mode. Fix
mainboard_picr_data table by identifying devices programmed with value
0x1F while programmed differently on mainboard_intr_data table. Do so
only for devices that are used by kahlee or interrupt required by old OS.
BUG=b:70788755
TEST=Build and run kahlee, Verify that message disappears from serial
output.
Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This commit uses newly defined macros to make it easier to read which
iomux function pads are being configured to use.
TEST=Booted grunt, confirmed display backlight came on.
BUG=b:72875858
Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
There's no need to set the output enable here; this is already handled
by the native function. I'm making this correction in this change to
prevent the GPIO pin descriptions from getting confusing.
BUG=b:72875858
TEST=Booted, confirmed S5_MUX_CTRL high with and without this change.
Change-Id: I9e047be7169586c59892ef2bdab915683feeebda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Turn on PCH iSCLK for meowth platform.
BUG=None
TEST=Boot up into OS and check register programming with iotools, the
command is iotools mmio_read32 0xfdad8000, returned value is 0x03.
Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The EC builds for nyan_big, peach_pit, and smaug (ryu) have been removed
from the latest EC codebase, so don't try to build them by default
anymore.
Change-Id: I53901b32753c5b9b050f517bbf3f10b9071913d4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add NHLT and dt support for meowth with max98373 amp.
BUG=b:71724897
TEST='emerge-meowth coreboot' compiles correctly
TEST=check SSDT and verify entries for max98373
TEST=check NHLT ACPI tables included blobs for max98373
Change-Id: Ic89bf669c7ab2ef39ce64e4da6a57a7069ee75f9
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
For variants that have a cr50 tpm, this enables faster polling when
interacting with the tpm.
BUG=b:72838769
BRANCH=none
TEST=verified on grunt that irq is used and not timeouts for tpm
Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch adds the Pmax setting in device tree. The Pmax is from
MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and
the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W.
BUG=b:72138778
BRANCH=None
TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage
& ensure the Pmax value is passed to FSP-S.
Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
AmdInitPost returns AGESA_WARNING. This is because AGESA by default
enables bank interleaving, while the HW does not meet the requirements
for it. Disable bank interleaving, thus clearing AGESA_WARNING.
BUG=b:73118857
TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost()
returned AGESA_SUCCESS".
Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Based on the pictures at http://www.fit-pc.com/web/products/intense-pc/,
the Intense PC does not look like a laptop. In its documentation it is
described as "mini-PC" or "Single Board Computer".
This patches moves the Intense-PC into the correct category on the
Supported Motherboards page.
Due to thermal considerations, I have not removed the "select
SYSTEM_TYPE_LAPTOP" in Kconfig.
Fixes: de7f8d3a19 ("mainboard/compulab: add support for CompuLab Intense-PC")
Change-Id: I4343306a2f82eed8211981cbd3b084f5d112d30b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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... and fix them in the process.
The Kconfig help text seems to be a slightly better place for such
documentation than a comment in Kconfig.
Change-Id: I4114e17ad9c486a9de059040b0e2821540c31aad
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Fizz fails to show pictures on a type-c monitor because VBIOS runs
before DisplayPort link is ready.
With this patch, when firmware needs to display something, Fizz calls
google_chromeec_wait_for_display to make sure display is ready.
The penalty is up to 2 sec per boot in dev and rec boot. Normal boot
won't affected unless there is EC update.
BUG=b:72387533
BRANCH=none
TEST=Verify screens are displayed on Fizz as follows:
1. Put DUT in normal mode
2. Flash EC image to trigger EC sync (critical update)
3. Trigger manual recovery (insert)
4. Hit ctrl+d to switch to dev mode (to-dev)
5. Confirm to reboot (dev warning)
6. Warm reboot (dev warning)
7. Cold reboot (dev warning)
8. Flash EC image to trigger EC sync (critical update)
9. Trigger manual recovery (insert)
Change-Id: I90befe94f93e13904987acda50b2598d034b0031
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).
BUG=b:72875858
TEST=Built and booted grunt, built gardenia.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Soraka, Poppy & Nautilus are designed to operate at max power of
45 Watt. Hence set psys_max to 45W.
BUG=b:66066340
BRANCH=None
TEST=Build and boot soraka.
Change-Id: If6f624733830b462329b5f539c20e2aea664143e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/23757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Change-Id: I6175ce3d3ef739c4f503db826036ffe8feff9ddc
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ia0293a0ec85c752686750dadb9730a159fd0c073
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The board does no support eMMC so no need to configure it.
Change-Id: If29009a09f39484b1da16fb650b4f9cbee2a6d19
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The board does not have memory down, only 2 DDR4 Slots.
Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I213ea13078fdc28489eb4572a084146df333a31d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I1c42519dbe848b0bbcafa7f923d862ba7c9d8ed5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I6fc1f8393ce3f5ba6f52edad7cf8efa5524d2704
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable the micro-controller interrupt line as a real IRQ.
BUG=b:71986991
BRANCH=none
TEST=on Meowth, run 'ectool --name=cros_fp fpmode capture' and see the
number of interrupts incrementing and the MKBP event happening.
Change-Id: Ic0cf03d2a3508148b6482a5a595eaa213eff52c7
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Turns out the write-protect GPIO polarity for Scarlet is different than
for Kevin/Gru, and nobody ever told us. Also, it must not be configured
with an internal pull-up or we'll not read the correct value. This patch
fixes both issues.
BRANCH=scarlet
BUG=b:73356326
TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the
right value in all cases.
Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This change enables DPTF and configures the policy. DPTF parameters were
provided by internal power team.
BUG=b:67877437
BRANCH=master
TEST=emerge-nautilus coreboot
Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/23731
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Read cse file was not getting cached and taking about 500ms on every boot.
Change-Id: I8c92eefc64fe146c628d9c104d7dfb016204004c
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp.
TODO: Fix as per octopus schematic.
Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Show mainboard version in the console log so that one can easily see it.
Change-Id: I33bae8b340fce13c0cbe525521828929038b069a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The I/O expander on the mc_bdx1 is used to get the hardware version of
the mainboard. This patch enables the chip driver for the I/O expander.
Change-Id: I98c667fe4dccf0698ab4cb5ede6082f020c70ec6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This format (one hex digit, followed by 'b', followed by binary digits)
is arguably useful, but also confusing. Use the more common format
instead.
Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Original SPD provided by the vendor had bytes after 254 shifted by 16
bytes. This change fixes the SPD data based on the latest details
received from the vendor.
BUG=b:72749394
TEST=Verified that the device with this memory part boots to OS fine.
Also, mosys is able to dump the right memory information.
Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:69011806, b:72179988
BRANCH=master
TEST=Verify touchscreen on meowth works with this change.
Change-Id: Iad3f0b77a02552266435e523fdbb74b14ada101a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/23551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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TEST=Run powerd_dbus_suspend and resume with button press
BUG=b:69614064
Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22732
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fine tune 14" BigDaddy USB#2 2.0 strength:
PERPORTPETXISET: 7
PERPORTTXISET: 1
IUSBTXEMPHASISEN: 3
PERPORTTXPEHALF: 0
this value could have USB#2 2.0 EA/function pass.
BUG=b:72922816
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I0ea1b966b7c02c95bf0ea1138a5629fd3b576439
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/23649
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously, we were seeing device boot into the recovery screen with
error code 0x5a. This was root caused to the SATA GPIOs (specifically
DEVSLP) not being initialized early enough, causing the SATA 1 link
detection to time out and the device to reboot into recovery with
0x5a instead of booting into the OS as usual.
BUG=b:69715162
BRANCH=None
TEST=after flashing BIOS, set gbb flags to 0, then type reboot from
the OS.
Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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acpi_header_t
This change makes the Nautilus platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.
BUG=b:68686020
TEST=Build, booted nautilus board. Verified kernel reads new strings.
Change-Id: I041f2838f07a2525be7a28fdc69b7f1af46d16f1
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/23648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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