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The previous settings caused the I2C frequency for the audio bus to be
too high, at 417kHz. The settings in this commit correct the frequency
to 396kHz.
BUG=b:119423345
Change-Id: Ibed886e6e1b0df4df6b87f6291e515364b3bf718
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This reverts commit ad41f5512306d118047d2f7243678ddb32b4b06b.
Reason for revert: <Issue have seen on EVT platform that vboot always fail to verify keyblock A>
BUG=b:121169122
Change-Id: I2790ef3463a228008b614498009fbdc8b493cfb0
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30286
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When the BMC firmware module is installed on the KGPE-D16, the
RAM SPD multiplexer lines are disconnected by hardware from the
SP5100 GPIOs and attached to BMC GPIO lines instead.
Set the BMC GPIOs to match the state of the SP5100 GPIOs during
RAM setup.
Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac5
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/19820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Enable Elan touchpad and WACOM touchscreen
BUG=b:119924134, b:120103010
BRANCH=master
TEST=Verify touchpad and touchscreen on arcada work with this change.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I3dcdb4eeeb32766e64553d9e69e6b7e2b5ba85aa
Reviewed-on: https://review.coreboot.org/c/30146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Commit d80884ea5a ("mb/google/kahlee: Disable IOMMU") disabled the IOMMU
in all kahlee variants, but omitted the explaining comment only in
liara's devicetree.cb. Copy this comment to liara.
Change-Id: I564013a16217445003467e2a0579abd50597b205
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Using ${...} in some places is slightly confusing.
Fixes: 395cbb4f97 ("mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree")
Change-Id: Id0856a10d92786a41d45ca697945699f6f4c1f4c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Sync'ing the sku_ids list in the master sku sheet.
BUG=b:112876867
Change-Id: I658e8dc67679b5b528ab267861a1151f50e42414
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update dptf settings for Charger throttling. Also, update Power
Limit1 minimum value setting from 4.5W to 3W.
BUG=b:112448519
BRANCH=octopus
TEST=Built and tested on Fleex system
Change-Id: I8c2a796ff28254ebef28ed5745b344f925d6e649
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Bobba would prefer to use different SAR values per sku-id for regulatory
compliance. This commit uses the newly added interface for custom wifi
SAR CBFS filenames.
CQ-DEPEND=CL:*729429
BUG=b:120958726
BRANCH=octopus
TEST=build
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Change-Id: I354382d651d65d533459f0ca460ca6fd6de547fd
Reviewed-on: https://review.coreboot.org/c/30223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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According to bard/ekko cpu types, PL2 need to set the values
1. KBL_U PL2 is 25w.
2. KBL_R PL2 is 29w.
BUG=b:120874861
TEST=power on and check the DUT can boot up well
Change-Id: I5f9d672c4244c363a7cfb362653663a065259fc0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enaebl the RTC driver to be used on mc_apl4.
Change-Id: Ib8d2a9f6b8cea47cd10db4dfcc59eec1b21c7993
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Enable PTN3460 chip initialization to get LVDS attached LCD working on
mc_apl4.
Change-Id: I3ccf5398f16831db321eba846d6b041daadf31dd
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Add GPIO configuration to match the hardware of mc_apl4.
Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30128
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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helper function
This patch replaces cpuid(1) references from icelake mainboard
with x86 cpu common code library functions cpu_get_cpuid().
- cpu_get_cpuid() -> to get processor id (from cpuid.eax)
Change-Id: Ia12d95d911dd6ee60a3a35937264fef668ad9e35
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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This patch implements board reset on the Cheza board. The real board
reset used by the operating system uses the PMIC, but unfortunately the
PMIC needs to be configured right for that to work. The PMIC
configuration currently happens in the Qualcomm blob (QcLib) that is run
from romstage, but vboot needs to be able to reboot during verstage
already. Porting all the PMIC initialization code to run in the
bootblock seems excessive (and at odds with the goal of doing as little
as possible before verification), so we'll just do a little hack and ask
the EC to perform a cold reset instead. For vboot purposes, this should
work just as well.
BUG=b:118501305
TEST=Hacked vboot code to call vboot_reboot(), confirmed that board
reset and came back up as expected.
Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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New emmc DLL values for Bobba.
BUG=b:120561055
TEST=Boot to OS, chromeos-install, mmc_test
Change-Id: I5a0d9587a91b3c71c042cd8ea360c816ea29fb91
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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file Module Part Number
Correct Ram_ID=0b0000 SPD Module Part Number mismatch last alphabet 'C'
to "H5AN8G6NAFR-UHC".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I4f4b83589ad6b53c0a24f2637f0fe8b92a1168e3
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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file Module Part Number
Correct to add Ram_ID=0b0001 SPD Module Part Number mismatch last alphabet 'C'
to "H5ANAG6NAMR-UHC".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I4d320b2e10c4865456a9a9ccb400db5dd9256b3e
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30177
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Creating skeleton files and directories in mainboard for the new Hatch
board. This is to facilitate development for different parties
involved.
BUG=None
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Change-Id: I64e79904c7ad95091ea29d9f80444c4e3b493471
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/29298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Update the TRACKPAD_INT1_1V8_ODL GPIO configuration so that it acts as a
wakeup source
BUG=b:119598593
BRANCH=octopus
TEST=Ensure that the system wakes up on trackpad events. Ensure that the
suspend_stress_test runs successfully for 25 iterations.
Change-Id: I28292682cf9c8037abb87d265e49a60139550db2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/30171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I15cfbbab15b940641c3952f2cfb4b11c37574816
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/29299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add reset delay in power resource to prevent bind to fail after unbind.
BUG=b:119795901
BRANCH=master
TEST=emerge-octopus coreboot,
verified that WACOM touchscreen can re-bind successfully.
Change-Id: Idcf02b1c931ed64951995403ec9ebe6b8f2db31d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30099
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable SATA port 0 and port 1 as that's not used as SATA on platform.
BUG=N/A
TEST=Build and boot up fine on google arcada board.
Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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There's no LAN connection on Arcada board, so disable PCH GBE.
BUG=N/A
Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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There are 2 vendor BIOS's for the Lenovo X200 with the difference being the
settings in the VBT blob to accommodate different backlight frequencies.
Linux however sticks with the setting set by the firmware.
Tested on Lenovo X200 with CCFL backlight.
Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29904
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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correct memory part name
form hynix_dimm_H5ANAG6NCMR-VKC
to hynix_dimm_H5AN4G6NAFR-UHC
BUG=b:113983573
BRANCH=Nami
TEST=emerge-nami coreboot chromeos-bootimage
Change-Id: I0c33343eb1269919fba324333897805da1d1ff9b
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This implementation configures below parameters:
1. Enable SaGv, isclk.
2. Set Pcie rootport enable, Clock source usage and clkreq.
3. Configure SATA and LPSS controllers parameters.
4. Enable CNVI controller, configure Wifi end device under PCIE RP1.
5. Add TPM device support under GSPI1.
Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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PEN_EJECT GPIOs are active high and also require an internal pull-up.
Update the GPIO configuration appropriately.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus
tools open on pen eject. Ensure that the system can enter S0ix and S3
states successfully when the pen is inserted. Ensure that the system
wakes on Pen Eject. Ensure that the system does not enter S0ix and S3
states when the pen is placed in its holder. Ensure that the
suspend_stress_test runs successfully for 25 iterations with the pen
placed in its holder.
Change-Id: Ibf9cb214a8ce7561efbb77a7e99d1e386cf064c3
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update the GPIOs for the next board build. Mostly minor changes but
the polarity change on GPP_E8/RECOVERY on sarien will result in it
booting to recovery every time unless using new hardware.
For this reason the recovery mode GPIO that is passed to vboot is
commented out for sarien. It is only used for testing and currently
it is useful to have an image that works on both board versions.
Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30062
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration
if specific UPD variables are not set as it expects.
This affects the display-related SOC pads with the following UPD variables:
UINT8 DdiPortBHpd; // GPP_E13
UINT8 DdiPortCHpd; // GPP_E14
UINT8 DdiPortDHpd; // GPP_E15
UINT8 DdiPortFHpd; // GPP_E16
UINT8 DdiPortBDdc; // GPP_E18/GPP_E19
UINT8 DdiPortCDdc; // GPP_E20/GPP_E21
UINT8 DdiPortDDdc; // GPP_E22/GPP_E23
UINT8 DdiPortFDdc; // GPP_H16/GPP_H17
Until FSP is fixed to not touch the pad configuration this workaround
will reprogram the GPIO settings after FSP-S step so they are correct
when the OS attempts to use them.
This was found in CoffeLake FSP Gold release:
https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg
As well as the current top-of-tree for the FSP sources.
BUG=b:120686247,chromium:913216
TEST=verify correct GPIO configuration for GPP_E group in the kernel
Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Synaptics Trackpad wake event is incorrectly routed to GPE0_DW2_02. The
concerned GPIO is not connected and hence wont trigger a wakeup. Fix the
GPE wake configuration for synaptics trackpad.
BUG=b:120666158
BRANCH=octopus
TEST=Ensure that the wake on trackpad works with Synaptics touch pad.
Ensure that the system can enter S0ix successfully(run
suspend_stress_test -c 25).
Change-Id: I87b8c266266280f61700839d428e6f8938b0f72f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30105
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP defined a special clock source usage 0x70 for PCH LAN device, update
that to google sarien platform.
BUG=b:120003760
TEST=Boot up into OS, ethernet able to be listed in ifconfig.
Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Part Number
Correct Ram_ID=0b0011 SPD Module Part Number to "MT40A1G16KNR-075:E" from
"4ATS1G64HZ-2G6E1".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I9d582b3753de9a48865eb6eca7e4fbdb31b799ff
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Number
Correct Ram_ID=0b0000 SPD Module Part Number to "H5AN8G6NAFR-UH" from
"HMA851S6AFR6N-UH".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I1f6e885638589a35334a9a8f905af4877c5d1f91
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Part Number
Correct Ram_ID=0b0010 SPD Module Part Number to "MT40A512M16JY-083E:B"
from "4ATF51264HZ-2G3B2".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The Intel Sensor Hub was enabled on the wrong variant so this change
moves the enable from sarien to arcada.
Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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A new liara specific VBIOS updating eDP power sequence is available now,
Change Kconfig to use it if board is google liara.
BUG=b:120534087
TEST=Build liara, booted, tested eDP test compliance.
Change-Id: I444cfa0bd755480e006f11c0d692b25b96129c29
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/30090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The code is based on autoport and that for T430s
Tested:
- CPU i5-3337U
- Slotted DIMM 2GiB
- Soldered RAM 4GiB from samsung (There may be more models here)
- Camera
- pci-e and usb2 on M.2 slot with A key for wlan
- sata and usb2 (no superspeed components) on M.2 slot with B key for wwan
- On board SDHCI connected to pci-e
- USB3 ports
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- TPM1 on LPC
- EHCI debug on SSP2 (USB3 port on the left)
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
Linux payload (Heads), Seabios may also work.
Not tested:
- Fingerprint reader on USB2 (not present on mine)
- Keyboard backlight (not present on mine)
- "sticky_fn" flag in nvram
Not implemented yet:
- Fn locking in nvram (may not be identical to "sticky_fn")
- C-based native graphic init (since T431s has eDP instead of LVDS)
- Detecting the model of Soldered RAM at runtime, and loading the
corresponding SPD datum (3 observed) from CBFS (the mechanism may be
similar to that on x1_carbon_gen1 and s230u, but I do not know how
to find gpio ports for that, and SPD data stored in vendor firmware.)
Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Provide rise/fall times as measured on existing boards. This will
need adjusted for new boards but provides a starting point that
makes I2C clocks look reasonable.
Tested by measuring I2C bus speed and rise/fall times with a scope.
Change-Id: Ic18010f5efc41dcee8925d696767ba2c44e3df4b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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According to issue tracker b:119899090.
https://partnerissuetracker.corp.google.com/issues/119899090
We modify rammus devicetree.cb .i2c[1] configuration to meet ELAN touchpad I2C special timing requirement.
BUG=b:119899090
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and check touchpad I2C characteristics meet requirement
Signed-off-by: YanRu chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ifeb08c2530e6a7674f23f7d48cefa16cfc59cb13
Reviewed-on: https://review.coreboot.org/c/29922
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:119799550
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.
Change-Id: I926c988c141628ae2d98206f9eb615d06357a366
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Re-write the UAO handling code as it had stopped working (#171)
(the flag was not getting read from the RTC properly in SMM)
Remove the SMM code as it's not needed (but EC flag won't be set
upon entering S3 now)
Set the EC flags on boot the same way other flags are set
Document bitwise operators for clarity
Propagate changes to other Thinkpads
(updated X201 to have 2 bits for the flag as it only had 1)
Per Nicola Corna's previous commits, 0x0d is set for "AC only"
"AC only" does exhibit different behaviour - the USB port is
turned on a few seconds after entering S3, rather than < 1 sec,
regardless of AC status
Tested on X220
Change-Id: If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Tested - Lenovo t520 still builds fine with this patch.
Change-Id: I82492c071ca760f0790b992acbdb86021f470cfe
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Turn on the ISH in the device tree.
BUG=b:120295222
Change-Id: I0ba08c245d050aebc6eb06055690c422ab9b51c6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30034
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=build & run
Change-Id: Ie404faf37617d2ad792310709ca2063f9a372076
Signed-off-by: Mukesh Savaliya <msavaliy@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/25392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Move the backlight initialization from bootblock to romstage
BUG=b:120436919
TEST=Careena backlight is enabled
Change-Id: Ia4993b993d37afaf9e23d6f3316ba91053732f1d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Platform have a 32MB SPI chip, so we can increase the bios region from
16MB to 28MB.
BUG=b:119267832
TEST=Build and boot fine on sarien platform.
Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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AMD traditionally claims the resource at I/O port 61 for the onboard
PC-AT speaker. In later designs, the speaker may be omitted in favor
of routing the SPKR signal to the codec.
Some systems implement neither, and for those it is not correct to
identify the resource as a speaker. Modify the EISAID reported to
the OS depending on the system design. The default is that port 61
is reported as reserved. In order to report a speaker, add #define
in mainboard//dsdt.asl.
TEST=check /proc/ioports and iasl -d for both ways using a Grunt
BUG=b:117818432
Change-Id: I33aafb187f9fea7b38aae43c399292c7521fcfc4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ifb08c903e19ef4e93bdc9cbc9844cb1888a8d2fa
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Sort mainboard-specific defines in the same order as in all other Lenovo
boards. This is a purely cosmetic change which just makes diff between
boards smaller.
Change-Id: I4e379bb727b356fc6010e93de492f6d73f97a750
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Most Lenovo mainboards define their own specific defines in dsdt.asl.
Let's make it consistent across all Lenovo mainboards.
Tested - builds fine.
Change-Id: I03fbeb09b25e42af2dfbb220c0f726e6abb73673
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch lets spike boot to "Payload not loaded" again.
Because soc/ucb/riscv/ does not represent a real SoC, but is a dummy
directory for emulators, and different emulators might have different
memory maps, I moved mtime_init to the mainboard-specific directories
for Spike and QEMU.
Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/28873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
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Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ,
implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM
interrupt.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui.
Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/29192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Set GPIO D22 low to get WWAN_PERST#_R asserted.
BUG=N/A
TEST=Boot up with Arcada board, check WWAN get detected as USB devices
through lsusb command.
Change-Id: Ie848cd19fdf3b6c4b6abeb5fa3f566e5e4e7e928
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30030
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:111812662
TEST=flash to nocturne, boot nocturne, run "memtester 1g" and
verify it passes.
Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Add the USB device information for the sarien/arcada variants.
This includes the ACPI _PLD group definitions for the external
ports that indicate which USB2 and USB3 ports share the same
physical interface.
Change-Id: I0b936127954ba09c61ccb871bfc62ee7d99da263
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add ACPI _PLD group definitions for the external ports
that indicate which USB2 and USB3 ports share the same
physical interface.
Change-Id: I7f85720a878a3774d453a9adb82518722f7ba23d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable DPTF support for sarien/arcada boards. This is currently
using placeholder values that are identical that will be updated
after thermal tuning is done.
Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Set WWAN_GPIO_PERST#(GPP_D22) to low at bootblock stage to meet
the logic output for WWAN_PERST#_R to high.
BUG=120004153
TEST=Boot up Sarien board, check WWAN get detected as USB
devices through lsusb.
Change-Id: I16f1101c64dfd4dcb5e8342fdb925951f6f2f90b
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
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* Verify the flash write protection on each boot
* Program non-volatile write protection on first boot
Tested using I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc.
The bootblock is write-protected as long as the #WP pin is asserted low:
* Reprogramming of the status register fails.
* Trying to write to WP_RO region fails.
Programming the WP_RO is only possible if #WP pin is high.
Change-Id: I6a940c69ecb1dfd9704b2101c263570bebc5540e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/29532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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update the new sku ids of bard/ekko
BUG=b:120257865
BRANCH=Nami
TEST=emerge-nami coreboot chromeos-bootimage
write the new sku id in cbi and verify the fw to
check it can get the correct settings by the sku id
Change-Id: I3579d3d8042a270d8ea8e2f7b5612ff8e2cdfa7b
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30031
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables mode change as a wake source from S3 and
S0ix. Thus, any time the device switches between clamshell and tablet
mode while it is suspended, it will be treated as a valid user event
and hence wake source.
BUG=b:120349473
BRANCH=octopus
TEST=Verified that octopus wakes up on mode transitions.
Change-Id: Ib224df434730f873ce5514303e5d043cbc85a9a4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/30001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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This makes the mainboard able to boot again.
Change-Id: Id96fbfd5c815431dba2f030fca62a5ea16b97393
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29994
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"if" is preferable over "#if", because it lets the compiler perform
syntax and type checks even if CONFIG_CONSOLE_SERIAL is disabled.
Change-Id: I45a763f2d854fbe9082795bc74de7a9d0fded3c9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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All Lynx Point board select this, and none build without it.
Change-Id: I4b59b10ee985cff5a8e1442677d36b0be88cf437
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak.
Lynx Point now benefits from being able to write-protect the flash chip.
For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done
in bd82x6x.
Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is
configured, flashrom reports all flash regions as read-only, and does
not manage to alter the contents of the flash chip.
Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to
work as before.
Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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The ASRock H81M-HDS doesn't implement a finalise handler. To fix
this, and reduce code duplication in the process, make a common
implementation. There should be no functional change to boards with
existing finalise handlers, since the code is identical among them and
the new, common implementation.
Tested on an ASRock H81M-HDS. The finalise handler works.
Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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The WACOM 5C01 touch panel power-up delay of 10mS is too aggressive
and causes "failed to change power setting" errors in the kernel, so
this change increases the power-up delay to 20mS which allows enough
time for the WACOM device's i2c controller to wake up.
BUG=b:120090384
BRANCH=none
TEST=flash and boot nocturne, log into kernel, execute the following
command and make sure the string is not found :
dmesg | grep "failed to change power setting"
Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29988
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We discovered that the gpios previously used for FPMCU_INT_L were in
two different groups with two different voltages (C group was at 3.3V
and D group was at 1.8V). Moving both to B group which is at 3.3V.
BUG=b:119447525
BRANCH=Nami
TEST=unlock OS with fingerprint
register fingerprint
run powerd_dbus_suspend and see if it goes int s0ix
Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/29872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Update USB port info according to the schematic file.
BUG=none
BRANCH=master
TEST=Compiles successfully and boot on DUT.
Change-Id: I7383b3d676fd7c775a6d749c70af65b28cf941eb
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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This change selects Kconfig option to disable native SD card
controller in ACPI tables.
BUG=b:119798840
BRANCH=master
TEST=Compiles successfully and boot on DUT.
Change-Id: I68dc9be511a370d882e4656c165efbe5dc6ee52e
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Handle situation when first NIC is not BDF 1:0.0. The PCI enumeration
is different when a external PCIe device is connected to mPCIe2 slot
which is routed to first PCIe bridge. The first NIC is then assigned
BDF 2:0.0, because it is connected to the second PCIe bridge.
Read the secondary bus number from the NIC PCIe bridge before attempting
to read MAC adress and calculating serial number.
Change-Id: I9f89a6f3cd0c23a2d2924e587338f69c260b12f8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/29842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Use of device_t is deprecated.
Change-Id: Ief858f6612d1c7b4b0c286cf5938f8c29055f1b5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
|
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Use acpigen_write_processor_cnot to implement notifications to the CPU.
Automatically generate \PPKG in SSDT.
Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Automatically generate \PPKG in SSDT.
Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29886
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Use acpigen_write_processor_cnot to implement notifications the CPU.
Generate PPKG in SSDT.
Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29885
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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POWER8 is a specific implementation of ppc64, which is by now outdated
(POWER9 has been on the market for a while). Rename arch/power8/ to
potentially cover a wider range of hardware.
TEST=Toolchains built before/after this commit can build coreboot for
emulation/qemu-power8 from before/after this commit.
Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
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The reason for this code cleanup is the legacy
Google Purin board which isn't available anymore
and AFAIK never made it into the stores.
* Remove broadcom cygnus SoC support
* Remove /util/broadcom tool
* Remove Google Purin mainboard
* Remove MAINTAINERS entries
Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29905
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to aleena thermal testing to set STAPM values.
skin scalar for 80%.
time constant for 2500s.
power limit for 7.8w.
BUG=b:72979852
TEST=test build for thermal check.
Change-Id: I09f1c1052dd317969546ac7d2bbde14cc563c160
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Correct Ram_ID=0b0001 SPD Module Part Number to "H5ANAG6NAMR-UH" from "HMAA51S6AMR6N-UH".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This commit create a casta variant for Octopus. The initial settings
override the baseboard GPIO configuration for Touchscreen, LTE, Pen and
Trace modules.
BUG=b:119056117
BRANCH=None
TEST=None
Change-Id: I5d3f7df66981d84fb47a6aa248480ef53dfd90d0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/29763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google
sarien and arcada board.
BUG=b:119058355,119054586
TEST=Confirm audio play back is working on Sarien and Arcada board.
Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
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Remove the __SIMPLE_DEVICE__ define from files used only in romstage.
This is not required since romstage always defines __SIMPLE_DEVICE__.
Change-Id: I8db1b15c9186536c9b8a6b5d667fa5a11af1bad2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29821
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This removes CEIL_DIV and div_round_up() altogether and
replace it by DIV_ROUND_UP defined in commonlib/helpers.h.
Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29882
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is an on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This mainboard also has a SD slot.
Change-Id: I969e8ecb27aee4c8be212e67dfe6bd807ecd3b2f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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PMIC provides power features like auxadc, buck/ldo,
interrupt-controller..etc
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ic247faf73517f6512f9c9a69ba0254c749d68d4c
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/29422
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The aleena board uses a display that's not compatible with current VBIOS.
A VBIOS specific for aleena has been merged into blobs, so modify Kconfig
so that it loads the new VBIOS when building aleena, but load original VBIOS
for all other boards under kahlee folder.
BUG=b:112618193
TEST=Build each board under kahlee, one at a time. After each build, opened
build/config.h and searched VGA_BIOS_FILE to verify that the string only
changed for aleena, all other boards remained with original string.
Change-Id: Iccd0853692680908d951edd142a2d8e13a561391
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hellsenberg <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: Ie06ae528ade3e06ae880b488628692ce43c30f5a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29845
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Assign correct SATA port map.
Tested on HP8200:
All SATA ports are now usable in GNU/Linux.
Change-Id: I5be2b4f33882f6f71213f8173cdb945fc9b7af06
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/29855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This change gets rid of bid0_override_table as part of clean up effort
to deprecate bid0. Additionally, it updates the touchscreen enable
GPIO in overridetree and gets rid of code in variant.c to update enable
gpio at runtime.
BUG=b:119885949
Change-Id: I527973747e7d81ec47997da57eeb15f38d3ac2fd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change is to bump fsp_memory_mainboard_version in order to
trigger MRC full training
BUG=b:119481870
CQ-DEPEND=CL:*716558
BRANCH=reef, coral
TEST=make sure MRC retraining is triggered and the MRC cache is
updated to newer version.
Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/29647
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables HDA audio support on icelake rvp. Add ALC700 codec
verb table and selects SOC_INTEL_COMMON_BLOCK_HDA_VERB config to detect
and initialize codec configuration as specified in verb table.
BUG=none
TEST=verify codec is listed and audio playback is working
Change-Id: Ibdf707f9002a09870ebe879c9db462084ecb01ea
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This implementation adds below changes:
1. Add chrome ec asl support for iclrvp.
2. EC SCI, SMI, S3/S5 wake events.
3. Wake pin and EC SMI GPE confiiguration.
Change-Id: Ie95da92f7125e56fe9ef9d57a1098278c308918e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29797
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This implementation adds support of PNOT method included in cpu.asl.
It is needed to notify CPU APCI device to re-evaluate the _CST table
for list of supported C-states.
Change-Id: I135cc3aa32a912c8ad3449d063d533f8873fcc94
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Use the common Intel code to set up smm and the smihandler. This is
expected to break S3 resume and other smihandler related
functionality as this code is meant to be used with
CONFIG_SMM_TSEG. Platforms (i945, pineview, x4x) using this
southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent
patches.
Tested on Intel D945GCLF, still boots fine but breaks S3 resume
support because it hangs on SMI.
Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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