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2023-01-17mb/google/skyrim: Set winterhold SPI fast read speed to 100MHzMartin Roth
Winterhold runs with the SPI fast read speed set to 100MHz. This decreases boot time by roughly 100ms. BUG=None TEST=Examine boot times. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I879e17fb0212910c7f90ba0e78ee16bea8b7cffa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-17mb/google/marasov: Skip MBP HOB creation to save boot timeSubrata Banik
This change skips the MBP HOB creation since coreboot doesn't use it and also helps to reduce the boot time by ~10msec. Boot time data: Before: * 955:returning from FspSiliconInit 897,278 (33,603) After: * 955:returning from FspSiliconInit 864,543 (21,273) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia97cca560869fcfd55e65c2e1719cceec6f3ab7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71873 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17treewide: Fix old-style declarationsElyes Haouas
Replace old style declaration "const static" with "static const". This to enable "Wold-style-declaration" command option. Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-17mb/starlabs/starbook/adl: Fix alignmentSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a3f871f2418438ef8e780a39935dfa2f86d8dbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-16soc/amd/picasso/include/acpi: introduce and use ACPI_SCI_IRQ definitionFelix Held
The newer AMD SoCs define ACPI_SCI_IRQ in the SoC's acpi.h header file and use this definition in the mainboard code, so port this back to Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib569747aa388d7953e79de747905fb52c2a05e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-16Revert "mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPD"Martin L Roth
This reverts commit 0e945a3426782e3c054a920ff8be3cd865f697ba. Reason for revert: Breaks build. Need to be merged after https://review.coreboot.org/c/coreboot/+/71715 which adds the register that this patch enables Signed-off-by: Martin L Roth <gaumless@gmail.com> Change-Id: I0ac3fb1a44e23e19c9711287f3a6a8402a6ffd79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71283 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-16mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPDSean Rhodes
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id53c9a6495d584c374e89b76d1fd4258654b6f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-15mb/bostentech: Update name in KconfigMartin Roth
The Bostentech mainboard appears out of order - this can be fixed either by renaming the mainboard to start with S, or by the simpler method used here by putting the mainboard directory name as the main name, then noting that the full name is "Shenzhen Bostrontium Teng Technology". Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I31b4c663b68cdcde2d175f080f011f2998e56074 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-15mb/google/skyrim/var/winterhold: Update USB port A0 settingEricKY Cheng
Update USB port Type-A Port A0 setting. BUG=b:261650602 TEST=emerge-skyrim coreboot. Ensure that USB-A port is enumerated correctly in the output of lusub command. Change-Id: I9563f7b141c34b613cf896f1ce92178617a62c93 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71854 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-01-15mb/google/brya/var/marasov: Update Aux settingsFrank Chu
Follow hardware design to correct aux setting on USB-C ports to fix DP monitor can not output data through type-C port 0 USB-C port 0 did not have retimer. USB-C port 1 have retimer. USB-C port 0 AUX_DC_P connect to GPP_E22. USB-C port 0 AUX_DC_N connect to GPP_E23. BUG=b:263212450 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage DP monitor display normally Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I3af7522f7b6477edcd88004ce1d5f86aeebe3393 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71222 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15mb/google/skyrim/var/winterhold: Update I2C bus0 settingsDtrain Hsu
Update settings for touchpad I2C frequency and data hold time. I2C frequency and data hold time need to meet touchpad spec. - I2C frequency: 380kHz - 400kHz - Data hold time: 0.3us - 0.9us BUG=b:262320419 TEST=On winterhold, touchpad i2c measurement from vendor, Frequencies: 395 kHz, Data hold time: 0.66 us Change-Id: I40fa6f9e88656d4ec02a4120f75a2a9413b5abaa Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-13mb/google/skyrim: remove morthal variantMartin Roth
Morthal has been overcome by events. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ice46f4c7400772dbf51eb9d20b61af277daa8513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13mb/lenovo/t520: Disable SATA2 and Thermal on W520Angel Pons
If a discoverable device (e.g. a PCI device) does not appear in the devicetree (typically because it is removable), coreboot enables it by default. Disable the SATA2 (device for SATA ports 4 and 5, which is not used in AHCI mode) and Thermal devices on W520 as well. Both devices were only disabled on the T520. Tested, this change fixes a long boot time when using MrChromebox's edk2 payload on the W520, likely related to the following errors: AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 0 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 1 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 2 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 3 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 4 Change-Id: I0b0483aae05fa84d97987a93db634b740f830e18 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71857 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13mb/lenovo/t520: Also disable PCI bridge on W520Angel Pons
As per Kendo3-WS schematics, the conventional PCI bridge is not used. Change-Id: Ic3aa11cc3a3028c31b06ad8f74875db8c5626a89 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71856 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13mainboard: Remove duplicated <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-13mb/system76/adl-p: Enable AER on CPU PCIe RPTim Crawford
Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - Drive is functional and has no unrecoverable errors on boot - Drive is functional and has no unrecoverable errors after S0ix Change-Id: I51492c97c48f760d4aa9e4a2b2e57b0f1a06d090 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-01-13mb/system76/adl-p: Add CPU PCIe RP RTD3 configsTim Crawford
Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - System still asserts `SLP_S0#` during suspend (power LED blinks) - `slp_s0_residency_usec` still increases after suspend Change-Id: I919d75cb2a88c0d623c46e44c506ec2d85567995 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-01-13mb/msi/ms7d25: Add support for DDR5 variantMichał Żygowski
The DDR5 board is almost identical to the DDR4 one. The only major difference is the board's DDR5 memory design. TEST=Boot MSI PRO Z690-A board successfully to Ubuntu 22.04. Memory: Crucial CT8G48C40U5.M4A1 in all 4 slots. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I652a879d1616df4708fe4690797ad98384897f53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-01-13mb/google/brya/var/omnigul: Update GPIO settingsjamie_chen
Configure GPIOs based from EE. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I5cfaa8fce6df7f09b744fb3e0b7b1d5b6acdc79b Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-12mb/intel/jasperlake_rvp/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I5fee0053ab0281b713c33dbc5862c1d4587e854e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12mb/intel/elkhartlake_crb/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I1c6f6d99cfb3bc08966d662282c023e22e111f90 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12mb/google/skyrim/var/markarth: Update devicetree settingJohn Su
Update devicetree based on the schematic_20230105. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I437425ac4a7cdb883dc213f5f6bb5f8a33a5577b Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71714 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12mb/google/brya: Add romstage early graphics for bryaJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b514 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71696
2023-01-11mb/google/brya: Enable eNEM support for Tanik and SkolasSubrata Banik
TEST=Able to build and boot Google/Tanik and Skolas to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a21122dbc324d3a396e8934e21d42f471cdb0bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11mb/siemens/mc_ehl1: Enable real-time tuningWerner Zeh
Enable the real-time tuning to improve performance in the real-time environment for this mainboard. Change-Id: I91ad7ca58add92b5cc66148aff8378890ee217eb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71234 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/geralt: Use BOE_TV110C9M_LL0 as default mipi panelBo-Chen Chen
We will use BOE_TV110C9M_LL0 for geralt proto board, so update the panel setting. BUG=none TEST=emerge-geralt coreboot; see panel-BOE_TV110C9M_LL0 in coreboot.rom Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I28e9dd87350b55fdc609dd2c562c5a2ad578187c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71786 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/geralt: Keep booting even if MIPI panel not foundBo-Chen Chen
We should keep booting even failed to get the MIPI panel. BUG=none TEST=emerge-geralt coreboot; Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I39d9e04e5908f669ae2a1a8ce8858b93cae20654 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71785 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/skyrim/var/frostflow: Update I2C setting for touchpadRex Chou
Update setting for touchpad I2C frequency. And meet touchpad i2c SPEC (380 ~ 400 kHz). BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 389 kHz Change-Id: Ie9efd4e597e2701c98064185e5b39a6e256a5f1c Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71772 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-01-11mb/intel/mtlrvp: Configure USB devices for MTL-RVPHarsha B R
This patch adds OC configuration of USB devices for MTL-RVP as per MTL-RVP design specification, USB 2.0 usb2_ports0 -> OC0 usb2_ports1 -> OC0 usb2_ports2 -> OC0 usb2_ports3 -> OC0 usb2_ports4 -> OC0 usb2_ports5 -> OC0 usb2_ports6 -> OC_SKIP usb2_ports7 -> OC_SKIP usb2_ports8 -> OC_SKIP usb2_ports9 -> OC_SKIP USB 3.2 Gen 2x1 usb3_ports0 -> OC0 usb3_ports1 -> OC0 TCPx tcss_ports0 -> OC0 tcss_ports1 -> OC0 tcss_ports2 -> OC0 tcss_ports3 -> OC0 BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to chromeOS (on top of CB: 66190). Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: If1a0c31b7bf0f3fc06f039ad76b0cdd41f7cdd90 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-11mb/google/nissa/var/craask: Disable storage devices based on fw_configReka Norman
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:263920313 TEST=Boot to OS on craask eMMC and NVMe SKUs with both unprovisioned fw_config and fw_config set correctly. Change-Id: I4167ee4d00b9ae8fe074c6f5e7a2d5a7382bfe6d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-11mb/google/nissa/var/yaviks: Disable storage devices based on fw_configReka Norman
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:251055188 TEST=Boot to OS on yaviks eMMC and UFS SKUs with both unprovisioned fw_config and fw_config set correctly. On UFS SKU with fw_config set, eMMC no longer shows up in lspci. (On eMMC SKU, UFS and ISH were already disabled by the coreboot PCI scan so there's no change in behaviour.) Change-Id: I31402cb49cffefd98b6fed971f249528448b1d0d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-11mb/google/brya/var/omnigul: Add memory parts supportAmanda Huang
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1) Samsung K3KL8L80CM-MGCT 2) Hynix H58G56BK7BX068 3) Micron MT62F1G32D2DS-026 WT:B 4) Micron MT62F512M32D2DR-031 WT:B BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I699070596a77c975254660a1ba74b0f40026186d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-10mb/intel/mtlrvp: Add romstage and configure DDR5 memory partsJamie Ryu
This patch adds initial romstage code and spd data for DDR5 memory parts for MTL-RVP. This also configures memory based on the board id. Memory - x32 DDR5 SBS SODIMM 1DPC Vendor/Model - SK-Hynix/HMCG66MEBSA092N BUG=b:224325352 TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-10mb/google/dedede/var/dibbi: Generate SPD ID for supported partsLiam Flaherty
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:260934724, b:255447299 BRANCH=dedede TEST=build Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71710 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10mb/google/brya/var/marasov: Update DPTF parametersFrank Chu
Add the first version DPTF parameters. BUG=b:264217345 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I55a3066ef61ce461f40b425a6549d083c29256e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71634 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-10chromeos/cr50_enable_update.c: Clear EC AP_IDLE flagDerek Huang
When AP boots up after Cr50 firmware update and reboot, AP finds that Cr50 reset is required for Cr50 to pick the new firmware so it trigger Cr50 reset and power off the system, AP expects system will power on automatically after Cr50 reset. However this is not the case for Chromebox, Chromebox EC set AP_IDLE flag when system is shutting down, when AP_IDLE flag is set in EC, the system stays at S5/G3 and wait for power button presssend. It cause an issue in factory that the operator needs to press power button to power on the DUT after Cr50 firmware update. This patch sends EC command to direct EC to clear AP_IDLE flag after AP shutdown so AP can boot up when Cr50 reset. BUG=b:261119366 BRANCH=firmware-brya-14505.B TEST=DUT boots up after Cr50 firmware update in factory test flow Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10mb/google/brya: Allow respective variant to choose NEM configSubrata Banik
This patch introduces a new config named `DEFAULT_ADL_NEM` and allows respective brya variants with Alder Lake ESx samples to choose NEM over eNEM as eNEM was fuse disabled till ESx. TEST=The boot flow related to eNEM and NEM behaviour remains the same with and without this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibbd492a3d210739120c7ad16415cb7912f5b70ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/71743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-10mb/google/brya/var/marasov: Disable touch panel power for non-touch skuFrank Chu
Disable touch panel power for non-touch sku by fw_config TOUCH field. BUG=b:263452842 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I4736f94481512806377b733b26fdc7290046c555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71691 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10mb/siemens/mc_ehl1: Limit SATA speed to Gen 2Werner Zeh
Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-09mb/google/dedede: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple dedede variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I91e03bd1d96a6b2f0c3813665910133db0d6c308 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/dedede: Set touchscreen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I212533ffdfb05f841e722c130b52c2976272e670 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/dedede: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on dedede variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). Since the fast majority of dedede variants have a touchscreen option, and those that do use the same GPIOs for enable/reset, set the GPIOs for touchscreen operation in the baseboard and then override for the few (3) variants that do not have a touchscreen. BUG=b:121309055 TEST=tested with rest of patch train Change-Id: Ib95e23545cc3e8589ddbd9e18cd0533bec9333e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/dedede: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: Ic216827a4b53d1d35913efca63a43d4672791c54 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/brya: Increase Resizable BAR address space limit to 33 bitsTarun Tuli
The dGPU used for some Brya projects requests 33 bits of address space for one of its BARs via the Resizable BAR mechanism (requires 6GB). This Kconfig is currently set at 32 bits for brya, so the allocation currently is capped at 32 bits (4GB). This patch sets the limit to 33 bits for brya boards, which is enough for the GPU. BUG=b:214443809 TEST=all of the dGPU PCI BARs on agah can be successfully allocated Change-Id: Ia791be5108fb07a256ae62fc2aee2f057909ef12 Signed-off-by: Tarun Tuli <tarun@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-09mb/google/brya/var/lisbon: Update RTL8168 LAN LED configRobert Chen
Adjust LAN LED config to 0x060f. BUG=b:246657849 TEST=emerge-brask coreboot Change-Id: Idd5ed2bf7eb4ee5990f2a842cba43f967ae3825e Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71698 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-01-09mb/google/brya/var/gladios: Update RTL8168 LAN LED configRobert Chen
Adjust LAN LED config to 0x060f. BUG=b:239513596 TEST=emerge-brask coreboot Change-Id: I17b844b89569fb7653454fd08782fc961c715817 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71697 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-01-09mb/google/skyrim/var/markarth: Enable DPTC supportJohn Su
Enable DPTC support for markarth. BUG=b:263216451 TEST=emerge-skyrim coreboot Change-Id: I18c2c840037f65f4f2ca92054247cece28843e45 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71720 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09mb/google/nissa/var/xivu: Update DPTF parametersIan Feng
Follow thermal table from thermal team. 1. Enable TS3 thermal sensor. 2. Set TS3 passive policy to 63. 3. Set TS3 critical policy to 73. 4. Modify TSR2 passive policy to CPU. BUG=b:263554342 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ia1fcaee15a8b58b755ce0a48a1978e795b66efd7 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71658 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09mb/google/brya/var/gladios: Add ACPI DmaProperty for RTL8168 ethernetRobert Chen
Add ACPI DmaProperty for gladios. BUG=b:239513596 TEST=Verified SSDT on gladios unit. Before: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) } } After: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } } Change-Id: I1c4f6ff7b3eda114f4f365a963c089fe584d8aee Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71699 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-08mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstageMartin Roth
Because skyrim is loading ramstage from SPI with the DMA engine, the size of the compressed image is less important to load speed than decompression time. Because the LZ4 decompression is so much faster than LZMA, compressing with LZ4 saves us roughly 30ms in boot time. For size, we're spending roughly 57KiB: fallback/ramstage 0x9b00 stage 130864 LZMA (305316 decompressed) fallback/ramstage 0x9b00 stage 189126 LZ4 (305316 decompressed) Right now we have 2MiB empty space in Skyrim's RO before this change, and roughly 550KiB empty space in RW, so there aren't currently any size worries. Just for fun, I also tested uncompressed ramstage, and it was still 18ms faster than LZMA, but that makes it roughly 12ms slower than LZ4. BUG=b:264409477 TEST=Boot skyrim, look at boot speed. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-08mb/google/dedede: Create dibbi variantLiam Flaherty
Create the dibbi variant of the waddledee reference board by copying the template files to a new directory. BUG=b:260934018 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a includes GOOGLE_DIBBI Change-Id: I3b8d4e7f8a53323f56567cbbc03bab7f8804f286 Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71709 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08mb/google/skyrim/var/markarth: Update RAM ID tableJohn Su
Add new ram_id:0000 for Micron MT62F1G32D2DS-026 WT:B. Add new ram_id:0010 for Micron MT62F512M32D2DR-031 WT:B The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) BUG=b:263296326, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I3a0d3edb813ef91bfdc68f7400be64fb679dfc04 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-08mb/google/nissa: Enable eNEMReka Norman
Enable eNEM for all nissa variants. This is mostly done to be consistent with other recent Intel platforms. It's not strictly necessary since on nissa the LLC size is larger than the total code + data size used in CAR. There is no change in boot time. BUG=None TEST=Boot to OS on craask Change-Id: Iad48976e405403ab61c71d8f72e0616ea8b85ebd Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-08mb/google/nissa/var/craask: remove SAR UNUSED fw_configEric Lai
This bit is dropped in factory. All skus can use table ID_0. BUG=b:251287101 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71690 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFCDavid Wu
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is not set, it will treat missing SSFC as zero, so Kano needs to set the ov2740 to 0 to avoid probing wrong mipi camera. Before patch >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: ZYDRON_UFC=UFC_MIPI_HI556 >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: STYLUS=STYLUS_PRESENT After patch >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: UFC=UFC_MIPI_OVTI2740 >I2C: 00:20 disabled by fw_config >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: STYLUS=STYLUS_PRESENT BUG=b:262939431 TEST=Boot on kano and check functional with ov2740 camera. Change-Id: I46fac6c820d6006956680a07198db82225630905 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-07mb/google/rex: Disable stage cacheSubrata Banik
This patch disables the stage cache to save boot time. Note: S3 is not POR for Intel MTL mobile skus. Boot time is reduced by ~8ms. Boot time before: 4:end of romstage 1,391,225 (13,724) 100:start of postcar 1,403,339 (12,114) Boot time after: 4:end of romstage 1,380,262 (5,618) 100:start of postcar 1,392,323 (12,060) Change-Id: I9775fc628f345a514894f30435a374e2ffa057c1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-07mb/amd: Update pademelon to eval boardMartin Roth
While pademelon may be a desktop board, it's not available for purchase, which means it should be presented here as an eval board. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5038935bb6f2ba530ea6e16ac84c1746efec8e48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-07mb/starlabs: Remove the bios_version functionSean Rhodes
Remove smbios_mainboard_bios_version so that the default CONFIG_LOCALVERSION can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia94f8683a54a98f4e3b1f51521db7e3ccb56ba48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-01-06mb/amd/mandolin/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: src/mainboard/amd/mandolin/acpi: No such file or directory [-Werror=missing-include-dirs] Change-Id: Ifbe6fda12088ddf51b6a177116aa542dbacc7672 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-06mb/amd/bilby/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: src/mainboard/amd/bilby/acpi: No such file or directory [-Werror=missing-include-dirs] Change-Id: Ie167cd362b55e38870d26a877d8181b2b07b8639 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-06mb/google/brya/var/omnigul: use i2c1 for TPMjamie_chen
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the omnigul variant. BUG=b:263060849 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804 Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-06mb/google/brya/var/omnigul: use RPL FSP headersjamie_chen
To support an RPL SKU on omnigul, omnigul must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for omnigul so that it will use the RPL FSP headers for omnigul. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: If3cfbaeff0472012cb8f30ed8fff3bf5cac23f85 Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Change-Id: I6a0afb04bea4940e13ea62c2cd0a09500b8b5335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71702 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-06mb/google/nissa/var/craask: Modify GPIOs for NVMeRen Kuo
Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for commonality of GPIO settings. To reserve craask GPIO table and add craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will be 2 and clksrc is still 1. BUG=b:259211172 TEST=Verify on reworked craask DUT to boot up from NVMe. Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71170 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-06mb/google/nissa: Disable stage cacheReka Norman
Although S3 is supported on nissa, only S0ix is used on user devices, so we can ignore optimising the S3 resume time. Disable the stage cache to save boot time at the cost on increasing the S3 resume time. Boot time is reduced by ~6 ms. This is mostly from adding postcar to the stage cache, which is slow since TSEG is not cached in romstage. Adding ramstage and FSP-S take negligible time. The S3 resume time is increased by ~89 ms total from loading and decompressing ramstage and FSP-S. Boot time before: 3:after RAM initialization 573,295 (931) 4:end of romstage 583,569 (10,274) 100:start of postcar 587,729 (4,160) Boot time after: 3:after RAM initialization 571,527 (830) 4:end of romstage 575,712 (4,185) 100:start of postcar 579,866 (4,153) S3 resume time before: 101:end of postcar 368,904 (0) 10:start of ramstage 369,165 (260) 971:loading FSP-S 385,742 (16,577) 30:device enumeration 407,105 (21,362) S3 resume time after: 101:end of postcar 363,101 (0) 8:starting to load ramstage 363,101 (0) 15:starting LZMA decompress (ignore for x86) 382,802 (19,701) 16:finished LZMA decompress (ignore for x86) 431,620 (48,817) 9:finished loading ramstage 431,850 (230) 10:start of ramstage 431,927 (76) 971:loading FSP-S 448,357 (16,430) 17:starting LZ4 decompress (ignore for x86) 474,420 (26,062) 18:finished LZ4 decompress (ignore for x86) 474,627 (206) BUG=b:247940538, b:192032803 TEST=Boot and S3 suspend/resume on craask Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71677 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-05mb/google/skyrim/var/markarth: Update GPIO settingsJohn Su
Configure GPIOs based on b/263534907#comment4 from EE. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71635 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-05mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterunChris.Wang
Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-05mb/google/brya/var/marasov: Disable FPMCU interfaceFrank Chu
Set fingerprint control GPIO to NC by HW design. BUG=b:264340020 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71650 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-05mb/system76/tgl-u: Add FSP-S configs per variantTim Crawford
Configure CPU PCIe RP and IOM per variant. Change-Id: I9c38af42206497dbb9436e9f2b8aff46fa4d3fb9 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-01-05mb/google/brya: Create omnigul variantjamie_chen
Create the omnigul variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:263060849 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OMNIGUL Change-Id: I6b4123db9cb77dc050a81f1cb83ef10e2fbffe8d Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-04Revert "mb/google/brya: Define a more suitable MRC training text message"Jakub Czapiga
This reverts commit e45f70423e5da8509bae83aba84b08f8fc0f624e. Reason for revert: Merged out of order, broke tree Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I38a7be6b94199d3a23e78114fb6708c535f241cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-04Revert "mb/google/brya: Add romstage early graphics for brya"Jakub Czapiga
This reverts commit 96d9b756690839c17b307a93b8a1898bd1c02ff5. Reason for revert: Merged out of order, broke tree Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iac2d78f2d6c687f52dc720e8d8dcb5cf7a171c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71280 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya: Define a more suitable MRC training text messageJeremy Compostella
This message is designed to reduce end-user confusion who may not know what memory training is. It also provides a maximum time estimation calibrated for brya devices. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=New message observed on skolas Change-Id: Ie71cd86746427789b3694d41224bf2c170af0f91 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70796 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya: Add romstage early graphics for bryaJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b513 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-04mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVPHarsha B R
This patch will enable Kconfig SOC_INTEL_CSE_LITE_SKU option required to enable CSE-Lite SKU for MTL-RVP. On enabling the respective Kconfig option, CSE reboots the system into CSE_RW FW region on cold reboot. BUG=b:224325352 TEST=Able to boot intel/mtlrvp to ChromeOS and also able to observe CSE boot to RW FW region as part of coreboot console log, localhost ~ # cbmem -c | grep cse [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RW [DEBUG] cse_lite: Next partition = RW Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I325405cc304d245871396317c11ac7a5b062a5bd Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71638 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/skyrim/var/markarth: Generate RAM IDs for new memory partsJohn Su
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) BUG=b:263296326, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I4f00d444bd59443ecba29c6c155d676bab7a3d82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-04mb/google/skyrim: Create markarth variantChao Gui
Create the markarth variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:262092858 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_MARKARTH Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82 Signed-off-by: Chao Gui <chaogui@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-04mb/google/nissa/var/yaviks: Disable external fivrWisley Chen
In next phase, yaviks will remove external fivr. Use the board version to config external fivr for backward compatibility and show message. BUG=b:263842258 TEST=build, boot to OS, suspend/resume work normally. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id85570046c5b8e9d90a112793c1ec8604e6bf533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-04mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOWSubrata Banik
This patch configures GPP_H15 (EN_DMIC_SOC_DATA) as GPO and put into safe state aka LOW/PD. BUG=b:263411621 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya/var/gaelin: Use RPL FSP headersMike Shih
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP. Since we use RPL FSP and it will support ADL as well, we rename "Gaelin4ADL" to "Gaelin". BUG=b:258603624 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Cq-Depend: chrome-internal:5227091, chromium:4113361 Change-Id: Ie7349f3670aeec166228e7df55300cd30d0ca16c Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-03mb/google/brya/var/lisbon: Update audio codec i2c timingKevin Chiu
Adjust audio codec i2c timing to 399 kHz. BUG=b:263050944 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I8495a88f2034e5e4ccf28ff53c81e0d6561e2e0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-03mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMeChris.Wang
winterhold/whiterun has different H/W topology to skyrim that the eMMC device is on a different GPP: skyrim: GPP1 -> SD winterhold : GPP1 -> eMMC BUG=b:263763288 BRANCH=none TEST=s0i3 stress over 2500 cycles. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-03mb/google/samus: Set hidden flag for RT5677AA ACPI deviceMatt DeVillier
Coolstar's Windows drivers don't utilize it, and the Linux drivers don't care about _STA, so hide it from Windows to tidy up Device Manager. Change-Id: I2eb4b3aeed50b9f3ee9f73a57d6585068aa31fbb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-03mb/google/slippy/peppy: Set cypress TP IRQ to Level vs EdgeMatt DeVillier
Change the IRQ triggering from edge to level for cypress touchpad on peppy variant for compatibility with Windows drivers. TEST=boot Linux 5.x/6.x, Windows 10/11 on peppy, verify touchpad functional. Change-Id: Iecf6cb919bf16ec9180ca050e7eafe55247337ed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on drallion, verify touchscreen functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I67c3d1fc3d34e9b67ddb26afcaad3a47ffa92e2f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I1bdbf017bc7480f59cec85c70d6e71dac294dcd2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on drallion, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I6825345f35a7415020e77edf781139f0c9b5f875 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty implementation to be used in a subsequent commit for touchscreen power sequencing. Call method in romstage to program any GPIOs that may need to be set. TEST=tested with rest of patch train Change-Id: I0ad0c18a8b61e59a943a453882bf74762bac4700 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/rex: Update USB2-C1 mappingSubrata Banik
This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1 as per latest Rex schematics dated 12/06/2022. TEST=Hardward awaited. Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Remove USB2_8 ConnectionSubrata Banik
DCI interface deprecated for Proto1. USB2_8 port becomes no-connect. BUG=b:263494661 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f03d600acd8ceaa5a5630fc19c1c7e34a4ea28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71237 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Revise config for the Proto 1 buildSubrata Banik
1. Rename DB_USB4 for KB8010 while adding ANX7452 as different DB_USB4 option. 2. Add audio component for Soundwire. 3. Rename MAX98357_ALC5682I_I2S to MAX98360_ALC5682I_I2S. Change-Id: I9f04c644b8a392feb2609f906bc9db945bf5fce2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70867 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-31mb/google/brya/var/gladios: Update audio codec i2c timingKevin Chiu
Adjust audio codec i2c timing to 399 kHz. BUG=b:262959586 TEST=FW_NAME=gladios emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I2f621e3af39fb40ab270c9de35d51dd43147b8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-31Enable VBOOT_VBNV_FLASH for SOC_INTEL_BRASWELLYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for boards using SOC_INTEL_BRASWELL. Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for CPU_INTEL_HASWELL, SOC_INTEL_BRASWELL and others (see [2]). However, there seems to be no particular reason on those platforms. We've dropped the config for haswell. Now do the same for SOC_INTEL_BRASWELL, so that VBOOT_VBNV_FLASH can be enabled. VBOOT_VBNV_FLASH is enabled for the following boards: - facebook/fbg1701: A 0x2000 RW_NVRAM region is allocated, with the FW_MAIN_A(CBFS) size reduced by 0x2000. - google/cyan, intel/strago: Repurpose RW_UNUSED as RW_NVRAM. [1] https://issuetracker.google.com/issues/235293589 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 ("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config") BUG=b:235293589 TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected) TEST=./util/abuild/abuild -x -t GOOGLE_CYAN -a TEST=./util/abuild/abuild -x -t INTEL_STRAGO -a Change-Id: I46542c2887b254f59245f20b8642b023a7871708 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31mb/facebook/fbg1701: Enlarge COREBOOT region for VBOOT by 64kBYu-Ping Wu
When VBOOT is enabled, the COREBOOT region (of size 0x09B000) is not large enough. Therefore, adjust vboot-rw.fmd (which is used only with VBOOT) layout by moving 0x10000 space from FW_MAIN_A(CBFS) region to COREBOOT(CBFS) region. TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected) Change-Id: I1bc0d6981b873ca631cc4cc0720ab212700a65aa Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31mb/google/rambi: Drop ChromeOS supportYu-Ping Wu
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS [1] and replace with VBOOT_VBNV_FLASH. However, the rambi's CAR is too small for early flash access in romstage: /usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: Cache as RAM area is too full /usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: section .car.mrc_var VMA [00000000fe008000,00000000fe00ffff] overlaps section .car.data VMA [00000000fe000000,00000000fe008787] make: *** [src/arch/x86/Makefile.inc:194: coreboot-builds/GOOGLE_RAMBI/cbfs/fallback/romstage.debug] Error 1 More precisely, DCACHE_RAM_SIZE is 0x8000, and the current .car.data size is 0x76c0. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is unselected, then the _bss region will increase by 0x10c8 bytes (for global variables such as `elog_mirror_buf` and `sfg`), so that .car.data will exceed 0x8000. Since rambi has reached its AUE (2021-09-01), disable MAINBOARD_HAS_CHROMEOS and VBOOT configs. [1] https://issuetracker.google.com/issues/235293589 BUG=b:235293589 TEST=./util/abuild/abuild -t GOOGLE_RAMBI -a TEST=./util/abuild/abuild -x -t GOOGLE_RAMBI -a Change-Id: Id56795dd0653784b4d7141142ebef0b19a46ddc3 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71545 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-30mb/google/skyrim/var/frostflow: Update I2C setting for touchpadJohn Su
Update setting for touchpad I2C frequency. And meet touchpad i2c SPEC (380 ~ 400 kHz). BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 390.1 kHz Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ied00e43e87404489af2b570206a70b685e554b78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71564 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29{ec,mb}/system76/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ia5ae30a1ee976b8059936027b28ac56f37279217 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71516 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29mb/intel/mtlrvp: Add configuration for UART devicesHarsha B R
This patch adds below configuration for MTL-RVP UART devices, Interface -> UART0 PCI -> 0:0x1e:0 Device -> AP UART BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp ito chromeOS using subsequent patches in the train. UART logs appear on AP console. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I4702d603aa49357f4db0d18d646e536d9d81787e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70873 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-29mb/intel/mtlrvp: Configure GPIO Tier-1 GPEs for MTL-RVPHarsha B R
Configure GPIO Tier-1 GPE's that defines the route for GPE events for MTL-RVP. Configure GPE route as below, PMC_GPE0_DW0 -> GPP_B PMC_GPE0_DW1 -> GPP_D PMC_GPE0_DW2 -> GPP_E BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to ChromeOS using subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ieab95b72ade75734b0788a32566649d90acbc48a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70872 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 07:06:09 +0000