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2021-10-13mb/google/guybrush/var/nipperkin: update fw_config fieldKevin Chiu
update fw_config for nipperkin BUG=b:196909635 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Icd2c5509450e70aed158f146179f3a7fa24b547a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-13mb/google/poppy: set SMBIOS enclosure type for all poppy variantsMatt DeVillier
Some poppy variants did not select a system type, which led to the default desktop type being set. Select the best fit enclosure type for each variant. Alphabetize the variant-specific options for improved readability. Change-Id: I7c23f8fa3ae1de67f7a68b8a4e9ec16c4e8044df Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-12mb/siemens/mc_ehl: Remove unneeded 'half_populated' variableWerner Zeh
Since the DRAM population is fixed to both channels on all mc_ehl boards there is no need to have this 'half_populated' variable at all. Simply use a fixed 'false' in the call of 'memcfg_init()' and delete this variable here. Change-Id: I783c17e6d92322a8b0c094cce803108e718011fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12mb/siemens/mc_ehl: Use SPD data from HW-Info in the first placeWerner Zeh
The preferred location for the SPD data on mc_ehl based boards is the HW-Info data structure. Inside this structure there is a field of 128 bytes available for the SPD data. So in order to use it construct a buffer in memory which is 256 bytes long (as FSP requests minimum 256 bytes for the SPD data) and where the upper 128 bytes are taken from HW-Info holding the needed timing parameters for LPDDR4. If there is a case where HW-Info is not accessible or where the contained SPD data is not valid (by checking the CRC in HW-Info SPD) fall back to fixed SPD data set in CBFS. Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12mb/google/dedede/var/sasukette: Generate SPD ID for Samsung K4U6E3S4AB-MGCLZhi Li
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=b:202480992 TEST=emerge-dedede coreboot Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I811f32defd50a940a09f238d38c962d2caf42855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12soc/intel: replace dt option PmTimerDisabled by KconfigMichael Niewöhner
Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-12mb/google/guybrush/var/nipperkin: update MAX98360 HID to MX98360APatrick Huang
Update MAX98360 ACPI HID from "MX98357A" to "MX98360A" BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Cq-Depend: chromium:3195465 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I8a1155848856db0cc4f42cfee0d914f8d1186b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-11mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO DescriptorMatt Papageorge
coreboot normally owns PCIe resets for all Cezanne based systems. However during S0i3 resume coreboot cannot intervene for S0 GPIOs (S5 carry over fine) so we needed an alternate way to de-assert this reset on guybrush. This change feeds in the given S0 reset GPIO (69 in this case) so that SMU may de-assert this reset on S0i3 resume. BUG=b:199780346 TEST=With latest FSP verify SD device trains each of 10 cycles Cq-Depend: chrome-internal:4157948 Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/google/guybrush: drop printk in bootblock_mainboard_early_initFelix Held
bootblock_mainboard_early_init gets called before console_init. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia5a1da336e8dfc451177a5319a656c407c9fef7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF writeFelix Held
Document what setting the PM_ACPI_S5_LPC_PIN_MODE and PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will eventually be factored out and moved to the Cezanne SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush: simplify LPC_MISC_CONTROL_BITS updateFelix Held
Since the LPC_LDRQ0_PD_EN gets set right after it got cleared, we can remove the clearing of that bit. This is split off from the previous patch to be able to use timeless build to verify that the previous patch didn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb300e7c7ce7e74c32ebdade0360ee4bd499b11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush: Use register and bit defines for eSPI setupRaul E Rangel
It's hard to understand what this code is doing because it uses hard coded values, so use the register and bit defines instead. BUG=none TEST=Timeless build for guybrush results in identical binary. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/google/fizz: Drop broken USB ACPI codeMatt DeVillier
Fizz's USB ACPI code is intended to allow the OS to control port charging power, but since Fizz's ports are dumb (vs smart), it controls power to the port itself. The end result is that active ports become disabled when rebooting from Windows (10/11), and power is not restored until the device is powered down (a warm reboot is not sufficient). Subsequent Chromebox models (eg, Puff-based variants) don't bother with EC-controlled USB port power, so just drop it since it's problematic and provides no benefit. Test: boot Windows 10/11, reboot, observe active USB ports still functional (eg, USB KB still works) Change-Id: I2c13d49b3ce8de8b0a38512db3c57d0c8ecbf0ad Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-11purism/librem_bdw: add support for ACPI brightness controlsMatt DeVillier
Test: build/boot Purism Librem 13v1, verify brightness controls work under Windows 10/11 with Tianocore payload. Change-Id: I27d04655adcd4a5dd42b025cfccb508cfd7aaeae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/google/caroline: Update _HID for digitizerMatt DeVillier
Caroline uses a Wacom digitizer, so adjust the ACPI HID so that the proper drivers attach under Windows/Linux. Change-Id: I732b09001dc41a91a32a5f9260abdab435b28b8a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/google/guybrush: Build chromeos.c in verstageHsuan Ting Chen
Before attempting another commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush builds chromeos.c in verstage to call get_ec_is_trusted() in vboot verstage_main(). Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ic22519fdde1b18f6ce0237022dee02ca37181a74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/google/guybrush: Add GPIO EC in RW to early GPIO tablesHsuan Ting Chen
Before attempting another commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush programs GPIO_EC_IN_RW (GPIO_91) as an early GPIO so that it can be read from in verstage. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-11mb/google/dedede/var/galtic: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:198713670 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Iaba136a836b89f42411474ae733380e345cce687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58162 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/ocp/deltalake: Fix SMBIOS type 9 bugsJohnny Lin
1. Fix PCIe slot capabilities not being really read from an IIO root port device. The Hot-Plug capability of IIO root port cannot be enabled due to FSP limitation (v2.1-0.2.2.0), but the code should reflect the true capabilities by reading the root port device's CSR. 2. Initialize the characteristics flags to 0 in the for-loop to fix the issue of the flags values persists to the next iterations. Tested=On OCP Delta Lake, dmidecode -t 9 shows the expected results. For example without the fix it shows 'Hot-plug devices are supported' but in fact it's not: System Slot Information Designation: SSD1_M2_Data_Drive Type: x4 PCI Express 3 x4 Current Usage: Available Length: Short ID: 1 Characteristics: 3.3 V is provided PME signal is supported Hot-plug devices are supported Bus Address: 0000:00:1d.0 With the fix it shows the correct result: Handle 0x0016, DMI type 9, 19 bytes System Slot Information Designation: SSD1_M2_Data_Drive Type: x4 PCI Express 3 x4 Current Usage: Available Length: Short ID: 1 Characteristics: 3.3 V is provided PME signal is supported Bus Address: 0000:00:1d.0 Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58100 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason, we have to adjust the PIR8 register (0x3150) which is responsible for PCIe device 25h. The bridge is connected to PCIe root port 7. The following routing is required: INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# TEST: - Boot into system software Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11mb/siemens/mc_ehl: Add variant_mainboard_final()Mario Scheithauer
In upcoming patches, we need mainboard specific adjustments. Change-Id: Icf9d829b19b2d26a39ad34be4658064083e9da6d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Enable LPC ComBMario Scheithauer
Enable LPC ComB on this mainboard. TEST: - Boot Linux and check with 'dmesg | grep tty' Change-Id: I7ec58685a723c177df18144011934b206e6425d0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer
This mainboard uses an eSPI-to-LPC bridge for console output. For this reason, the internal LPSS UART must be disabled. Change-Id: I86777cf719def331f4d257ddd94e9a87125ebce8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Adjust GPIOsMario Scheithauer
Set the GPIOs according to the circuit diagram for this mainboard. Change-Id: I19dc24a16ee9f533b45879bf60fb441e24018cc8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Disable SATA Port 0Mario Scheithauer
This mainboard has only SATA Port 1 available with no device sleep feature. Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Enable SD-CardMario Scheithauer
This mainboard has SD slot available and therefore it should be enabled. Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2Mario Scheithauer
This board has the RTC RX6110SA connected to the I2C2 instead of SMBus as in mc_ehl1. Set the bus speed for I2C2 to 100 kHz, since this RTC only supports the standard speed. TEST: - Console Log shows no errors for RX6110SA during I2C2 init - Finalize device for I2C 00:32 shows correct date and time Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11mb/siemens/mc_ehl2: Update SPD for DDR4 devicesMario Scheithauer
Since this variant uses different DDR4 devices compared to mc_ehl1 in a memory down configuration, the SPD data file must be adapted. In a first configuration we use Micron MT53D512M32D2NP modules. Following values were adjusted according to this board characteristic and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules JEDEC Spec and the Specification for this Micron modules itself: - SPD Byte 4 - only 4Gb density instead of 8Gb for mc_ehl1 - SPD Byte 5 - different Row and Column Address Bits - SPD Byte 29/30 - 4Gb LPDDR4 needs 130ns tRFCab - SPD Byte 31/32 - 4Gb LPDDR4 needs 60ns tRFCpb Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11mb/google/dedede/var/pirika: Add Synaptics I2C touchpad deviceAlex1 Kao
Add Synaptics touchpad device support in devicetree. BUG=b:201043984 BRANCH=dedede TEST=Touchpad device function is OK Change-Id: Ifb240d7113e401de827384697fc752a76fbf7ac7 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-11mb/google/brya/var/redrix: select CHROMEOS_DSM_PARAM_FILE_NAMEWisley Chen
Enable CHROMEOS_DSM_PARAM_FILE_NAME to report dsm parameter file name. BUG=b:197076844 TEST=build and check SSDT. Change-Id: I726e5854bc6a8fb125cb3b7572ddedff49c3c403 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS supportIan Feng
Add ALC5682-VS codec support in corori. ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO field of ssfc. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:201372531, b:194436265 TEST=ALC5682-VD/ALC5682-VS audio codec can work. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2f3edb0b594066714b42050a411103a215e68b12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2021-10-11mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMeKevin Chiu
nipperkin has different H/W topology to guybrush that the eMMC device is on a different GPP: guybrush: GPP3 nipperkin: GPP2 Hence we need to enable RTD3 for nipperkin additionally which refers to this one: https://review.coreboot.org/c/coreboot/+/54967 BUG=b:200246826 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage run suspend test on eMMC sku Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-09mb/system76: tgl-u: Add gfx register for GMA ACPITim Crawford
Add gfx register to System76 TGL-U boards so GMA ACPI data is generated. Change-Id: If944a90921b518efdcd5f0e0998bddb4f56e5764 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-08mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tablesTim Wawrzynczak
Before attempting another commit 6260bf71 ("vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants all program EC_IN_RW as an input GPIO in bootblock so that it can be read from in verstage. Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
2021-10-08mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-M RVPBora Guvendik
This patch enables eNEM flow for ADL-M TEST=Able to build and boot ADL-M RVP using eNEM mode. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-08mb/prodrive/hermes: Enable SATA power optimizerAngel Pons
Enable SATA power optimizer as recommended by Intel. Tested, a SATA SSD is still detected correctly by SeaBIOS (version 1.14.1). Change-Id: Ia6d29de08583dfc0c2d38e8395adcaa2c540ec7b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-07mb/google/brya: Disable unused i2s pins for BT offloadSugnan Prabhu S
BT offload hardware design is using only i2s0 pins. Need to disable i2s2 pins which are not used. As per the hardware spec there is an OR operation between vgpio and physical gpio pins related to i2s2. During BT offload configuring the i2s2 pins to its native function is causing offload issue on proto 2 boards. BUG=b:201736222 TEST=Verified BT offload on brya on proto 1 and proto 2. Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-10-07mb/google/dedede/var/bugzzy: Update GPP_D5 configurationSeunghwan Kim
As we checked the panel doesn't display firmware screen if we hold GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy uses the built-in touch screen on the panel, the panel seems like under reset state by the TOUCHSCREEN_RESET signal. This change sets default GPP_D5 level to high for bugzzy. BUG=b:None BRANCH=dedede TEST=built and verified bugzzy showed firmware screen Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Doan <edoan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-07mb/google/brya: Add PsysPmax setting to 145WRyan Lin
This patch adds the setting of PsysPmax to 145W according to the brya board design. BUG=b:195615830 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Signed-off-by: Ryan Lin <ryan.lin@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-07sc7280: Add SHRM firmware supportRavi Kumar Bokka
SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-04mb/google/trogdor: Add new vaviant quackingstickSheng-Liang Pan
New boards introduced to trogdor family. BUG=b:201263032 BRANCH=none TEST=make Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I8299ddda14eb82103f17f8464a14992aa757afa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-04mb/*/brya/variants/brask: Enable dynamic GPIO PMMeera Ravindranath
GPIO PM was disabled for brask to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot brask to OS, ensure no TPM errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-10-04mb/intel/adlrvp{p,m}: Enable dynamic GPIO PMMeera Ravindranath
GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot adlrvp to OS, ensure no TPM timeout errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-04mb/google/brya: Enable DDR4 SODIMM for braskDavid Wu
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in brask device tree and add SPD addressese for the two DIMMs. Separate the Kconfig items of brya and brask. Move HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya and add config SPD_CACHE_IN_FMAP to brask. Add a new section RW_SPD_CACHE to fmd for caching SPD data. The renamed romstage.c is used by both brya and brask and a new function variant_get_spd_info is provided to support the different SPD source types. BUG=b:194055762 BRANCH=None TEST=build pass Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04mb/google/brya/variants/kano: Correct MIPI camera infoLai, Jim
Correct OVTI2740 information for Kano: MIPI camera CIO port, HID and Link Freq BUG=b:200974074 TEST=Build and boot on Kano camera driver is not probed before, and it can now be probed properly after this change. Signed-off-by: Lai, Jim <jim.lai@intel.com> Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-02soc/mediatek: Fix I2C failures by adjusting AC timing and bus speedDaolong Zhu
1. The original algorithm for I2C speed cannot always make the timing meet I2C specification so a new algorithm is introduced to calculate the timing parameters more correctly. 2. Some I2C buses should be initialized in a different speed while the original implementation was fixed at fast mode (400Khz). So the mtk_i2c_bus_init is now also taking an extra speed parameter. There is an equivalent change in kernel side: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1 BUG=b:189899864 TEST=Test on Tomato, boot pass and timing pass at 100/300/400/500/800/1000Khz. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01mb/google/dedede/var/bugzzy: Update device treeSeunghwan Kim
Update bugzzy device tree override based on the EVT schematics. BUG=b:195215785 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Iba8e3fd24461b4228c6e6fa933c0093e3e45ee97 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-01mb/google/brask/var/brask: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for brask BUG=b:197385770 TEST=emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I71026565b876739d2a08ef79940f47c476ca70a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58041 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01mb/intel/adlrvp: set PL4 value dynamically for thermalSumeet Pawnikar
Set PL4 value dynamically for adlrvp board based on CPU SKUs which is detectable at runtime. These values are based on platform design specification. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board On 682: Overriding power limits PL1 (4000, 28000) PL2 (64000, 64000) PL4 (140000) Change-Id: I9c0c418e2548cc7f9aa647a5ad98123b33e9f9b8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brya: move MILLIWATTS_TO_WATTS macro in header fileSumeet Pawnikar
Move MILLIWATTS_TO_WATTS macro in power_limit header file so all other files can use the same macro. BUG=None BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/intel/adlrvp: set power limits dynamically for thermalSumeet Pawnikar
Set power limit values dynamically based on CPU TDP and PCI ID of SKU. These values are as per platform design specification. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brask: Correct SSD power sequenceEric Lai
M.2 spec describes PERST# should be sequenced after power enable. Follow up commit 658d7c5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I508f7e21888cc1938aa9a6f0066c17029773974b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brya/var/felwinter: Correct SSD power sequenceEric Lai
M.2 spec describes PERST# should be sequenced after power enable. Follow up commit 658d7c5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I494e0edc135d730cf7bb437f0196cdf233d970d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brask/var/baseboard/brask: Update GPIO GPP_B5 and GPP_B6David Wu
Update GPIO GPP_B5 and GPP_B6 based on schematics. BUG=b:197385770 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If83e02eec7c48b9ab41d346aa8baef7c0c881df1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-10-01mb/siemens/mc_ehl: Move UART_FOR_CONSOLE switch to variant levelWerner Zeh
There are currently two variants for mc_ehl where different UARTs are used for the console. Move the Kconfig switch UART_FOR_CONSOLE to the Kconfig of the variant and select the matching value there. Change-Id: I7152013a0e32ff151b92932a47953705e591dc0d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58052 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01mb/siemens/mc_ehl: Add a new variant mc_ehl2Werner Zeh
Add a new variant of the mc_ehl board called mc_ehl2. This patch just copies the files and renames things where needed. Following patches will adapt the needed features for this new variant. Change-Id: I3ec3c091017fd66fe6a09216203cdc7c9e833846 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-10-01mb/siemens/mc_ehl1: Enable LPSS UARTWerner Zeh
Enable LPSS UART for coreboot console on mc_ehl1. Change-Id: Id995953741d48fbbe2482ff7c0ef81cac5a31207 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-10-01mb/google/brya/var/kano: Add Synaptics touchpadDavid Wu
Add Synaptics touchpad for kano. BUG=None TEST=emerge-brya coreboot and check touchpad function work. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iec43aaa9525309d2a0e3c9822038869786f5fe66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30mb/amd/bilby: Use I2S TDM interfaceAamir Bohra
Bilby uses I2S TDM interface for audio, instead of HDA interface. Change-Id: I7c8ec02d0e63730cb54a27d3bea1d102e037823d Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2021-09-30mb/intel/adlrvp_m: correct SSD power sequenceSelma Bensaid
This is to fix SSD detectiong failure in warm boot observed on ADL-M RVP. This patch implements the coreect power sequence: SSD_PREST Low - SSD_PWR_EN High - SSD_PREST High Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: If6f9fc17a30c28c2948809cdbade9919d4ddd6c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-30mb/intel/adlrvp: Update Rcomp target value for DDR4 RVP SKUSubrata Banik
Update to recommended Rcomp drive strength value for DDR4 as per MRC team's input. Additionally, add space around the `targets` array. Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507d99a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30mb/google/brya/variants/gimble: Correct SSD power sequenceMark Hsieh
M.2 spec describes PERST# should be sequenced after power enable. BUG=b:201512872 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie164ddb29f947e190fa87b31165e3c84b07926e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58034 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29google/trogdor: Always initialize eDP bridge I2C QUP firmwareJulius Werner
In CB:52662 when MIPI display support was added, we accidentally changed the code flow for eDP displays such that i2c_init() will no longer be called when display_init_required() is false. This is a problem because on this platform, i2c_init() does not just prepare the I2C controller for firmware use, it also loads firmware to the controller that makes it behave like an I2C device in the first place -- a step that the kernel cannot later do on its own if the firmware didn't already do it. Skipping this initialization means the I2C controller becomes unusable to the kernel. This patch fixes the issue by making the i2c_init() unconditional again. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie4546c31d87d91113eeef7dc7a18599a87e6d6eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58026 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29herobrine: Initialize SAR sensor QUPShelley Chen
Initializing SAR sensor (QUP2, address 0x988000) BUG=b:198456205 BRANCH=None TEST=Boot into kernel and make sure no i2c errors for 0x988000 in dmesg Change-Id: I75b0e9173d4c49b5e7308158a678964d6637b225 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-29mb/google/herobrine: Change preprocessor to C codeShelley Chen
BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: I10f8a9682200b883474dc385331c5dae84cbdb08 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-29herobrine: Add fingerprint power sequencingShelley Chen
For Herobrine variants that include a finger print sensor, we will need to power sequence it. We are using the same FP sensor as trogdor, so we will follow the timings used for trogdor from CL:2695676. BUG=b:198474942 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: Ica6eafc47cf1b95eeb8d94c6e0a8c88519665e3f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58021 Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29mb/google/guybrush/var/nipperkin: Add ALC5682I and MAX98360 supportPatrick Huang
Add ID "10029836" for machine driver, "RTL5682" for ALC5682I and "MX98357A" for MAX98360. BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Iab9d11adb7cd08effa2a9b6a627832bd89cb3cb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-29mb/google/dedede/var/boten: Add fw_config probe for ALC5682-VD & VSStanley Wu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define SSFC bit 9-11 in coreboot for codec within ec. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:193694180 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Iba91b51cbbe7adc502372c9a026867de61d8035d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-29mb/google/mancomb: Delete board supportKarthikeyan Ramasubramanian
Mancomb mainboard has been cancelled. Hence delete the board support. BUG=b:190404616 TEST=None Cq-Depend: chromium:3188634 Change-Id: I3ce02efb1fa5ea488447099abe08da6051fb6fc6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-29mb/intel/adlrvp, mb/google/brya: Add ADLP 242 PLx configurationsTracy Wu
Add ADLP 242 sku PLx related settings, which follow the settings of ADLP 282 sku (both are 15w). BUG=b:201253904 TEST=USE='fw_debug' emerge-brya intel-adlfsp coreboot chromeos-bootimage Change-Id: If9b60893ab3e2c4a88e7d2cf45223c5fbce6f847 Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-29mb/google/brya: Update PCH power cycle related durationsTim Wawrzynczak
The voltage rail discharge times have been measured, so therefore the boot time on a cold boot when the CSE must go through a global reset and thus a trip to S5 can be optimized. Select the lowest applicable value for each PchPmSlp UPD that can be used with these measurements. This is programmed in the baseboard because the measured discharge times leave (what should be) plenty of margin for variants to also not violate any power sequencing guidelines from the PDG. BUG=b:184799383 TEST=verified time in S5 during a global reset is ~1s instead of 4s Change-Id: Ia373c47b3967d68ddac21707c6eb4565d9d6519e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-09-29mb/google/dedede: Remove drawcia_legacy board supportKarthikeyan Ramasubramanian
Support for drawcia_legacy board is cancelled. Hence remove the board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I76cd3e388439f5aee94a17fe35ae210f449cfbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29mb/google/dedede: Remove Boten_Legacy board supportKarthikeyan Ramasubramanian
Support for Boten_legacy board is cancelled. Hence remove the board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If26dc869ff95dff70c0f83a13f6f727aa5992dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/57999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29mb/google/dedede: Remove wheelie variant board supportKarthikeyan Ramasubramanian
Wheelie variant board has been cancelled. Remove wheelie variant board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3ad5bc1c987feb55183a663937794781c7301a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29mb/google/dedede: Remove cappy variant supportKarthikeyan Ramasubramanian
Cappy variant is cancelled. Hence delete the cappy variant support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If43188a3e6bf4f4449c7e2d08be7609efe58dca1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-28mb/purism/librem_skl: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I2c4fb1933eda2eb75bfe9181f13e189ec66cadf9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-09-28mb/google/brya/variants/taeko: add NVMe GPIOs to early_gpio_tableKevin Chang
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that taeko can successfully boot into OS with non-serial coreboot. BUG=b:199969366 & b:200711149 TEST=Build FW and test with non-serial FW reboot 20 times pass. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I032c5b90fb2148c4075d6ead3e4161c0cc659b20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-28mb/google/dedede/var/magolor: Add custom Wifi SAR for magmaTyler Wang
Add wifi sar for magma. Due to fw-config cannot distinguish between magolor and magma. Using sku_id to decide to load magma custom wifi sar. BUG=b:192423859 TEST= emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iac15e958e61be6e3c136fb9be18b4695823ad1c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-28mb/google/dedede/var/galtic: Update PL1 min and max for Galith/GallopFrankChu
Update PL1 min and max values to 6 W for Galith/Gallop systems. BUG=b:201010771 BRANCH=None TEST=Build and verify on Galith/Gallop system Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I0dfda3c2c830a2ce203668431f396859e782aa3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-28mb/google/brya/primus: modify HID to MX98360A for next build phaseMalik_Hsu
For the next build phase, modify the HID of the speaker amp to MX98360A. BUG=b:199098681 BRANCH=none TEST=build coreboot without error Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0c318464fca7d35bbffd7ea0f5694b83acedff0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-28mb/google/dedede/var/kracko: refactor DPTF section for overridesRobert Chen
Refactor DPTF section of code under the kracko overridetree. This makes kracko override dptf section of dedede/baseboard, because the DPTF tool's CRT, PSV and TSR3 settings are different than expected. BUG=b:187482019 BRANCH=dedede TEST=Built and tested on dedede system Change-Id: Iacc543f961a7f4652ee8583920b1794f916c7ec9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/brya/var/kano: Move max98373 amp ACPI info to I2C0David Wu
Move max98373 amp ACPI info to I2C0 according to kano's schematics version KANO_MLB_Proto_0811. BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8f7a7938dd407666e0104ba64b22da85216a145f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/brya: Correct SSD power sequenceEric Lai
SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PREST should be sequenced after power enable. BUG=b:199822704 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If0a9e36cda4dc91bbccec02f39ccb9b658d24056 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/hatch/moonbuggy: Update DPTF parametersKenneth Chan
Update the DPTF parameters received from the thermal team. BUG=b:188596619 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I081963b97ed2dae0f5d026f6443c954b52347a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57919 Reviewed-by: Joe Tessler <jrt@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27mb/system76/gaze15: Disable OC supportTim Crawford
Clevo indicated that DIMMs running at 2933 MHz are not supported on a number of processors used for this model. Change-Id: Iadf611a64de664c783696e51cfe858ca95903936 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27mb/system76/lemp10: Use PME virtual wire for SWITim Crawford
Match the behavior of the other TGL-U boards. Change-Id: Ida962255f7a2435319d739d59eb2dc58fe342ae8 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27mb/system76: rtd3: Remove SrcClk pin on CPU RPTim Crawford
Setting srcclk_pin only works for PCH PCIe devices. Disable them on the CPU RP and add a TODO. Change-Id: I32db116feb33a8448eb8586fe9e882b8879489d4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27mb/intel/kblrvp: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: Ibb63f3ecd9cfbb6f564e0a9968c2776c25d84f79 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/51nb/x210: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I7255ac1ec6c43dd4b21325ae60e117458bea956d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/razor/blade_stealth_kbl: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I375ab879dd95d6a7a20644dc36312a1e62f58226 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/facebook/monolith: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Change-Id: I4e5be60d2784d003a388c52254514d0ab4d002b0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-09-27mb/google/glados: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Change-Id: Id26d9dfc3822b9120360fc2cb2ced8d67345a659 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/intel/kunimitsu: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Change-Id: I42458f16a323d3e37d0ee1bd8335e1f8d0e1fadc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/intel/saddlebrook: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I730cd3eeffff60b3b569bfb748febbdc8ca85990 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/google/dedede/var/blipper: Generate SPD ID for supported partsZhi Li
Add the relevant memory configuration of beetley to the blipper coreboot code The memory parts being added are: 1. Micron MT53E512M32D1NP-046 WT:B 2. Samsung K4U6E3S4AB-MGCL 3. Hynix H54G46CYRBX267 BUG=b:200000608 TEST=emerge-dedede coreboot Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I0b04f64cb007a58ae98f5ed187feb4859a43b1b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57670 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-24mb/google/guybrush: Remove ALS presentationGwendal Grignou
guybrush does not have a light sensor, do not include ACPI0008 ACPI device (Light sensor that will be managed by acpi-als IIO kernel driver). BUG=b:200823325 TEST=Check on Guybrush360 the sensor is not presented. Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: Id1dcb3a01ee43f780e4b118d88a0351e4c543f5a Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-09-24mb/google/brya/variants/primus: config dram speed to 3733Casper Chang
This change config the DRAM speed to 3733 for primus. BUG=b:200752480 BRANCH=none TEST=Verified that `dmidecode -t17` shows the correct configured memory speed Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I2f3a9489dddcf102b0ffc71eb9cdab6ad38d1391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/intel/adlrvp: Switch to using device pointersFurquan Shaikh
This change replaces the device tree walks with device pointers by using alias for dptf_policy device. Change-Id: I02ca63ac2cc1b8ed2f5a381b3824c9beff7f33ec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57870 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-24mb/google/zork: Switch to using device pointersFurquan Shaikh
This change replaces the device tree walks with device pointers by using alias for following devices: 1. audio_rt5682 2. xhci0_bt 3. xhci1_bt 4. acp_machine 5. i2c2 Change-Id: I56921ab54716e4d771d9de1a479f191ca5657eba Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 18:49:46 +0000