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2024-04-30mb/google/brox: Add 20K pulldown to GPP_D14Shelley Chen
GPP_D14 is floating when ISH is not being used and wasting power. Add pulldown to prevent this from happening. BUG=b:336654954 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage make sure OS boots up HW team validated that power usage is 20 mW lower Change-Id: I4e19e98fa31022ece66a47402a2a4461b430ef70 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-04-29mb/hp/280_g2: Fix comment in `gma-mainboard.ads`Angel Pons
The DVI connector on this board is DVI-D (digital only), not DVI-I. Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82112 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-29mb/google/brox: Fix the pad reset config for Touchpad interruptKarthikeyan Ramasubramanian
Update the pad reset config for Touchpad Interrupt from PLTRST to DEEP so that it can still act as a wake source during S3 suspend. BUG=b:336398012 TEST=Build Brox BIOS image and boot to OS. Suspend to S3 and wakeup using Trackpad. 246 | 2024-04-25 16:55:18-0700 | ACPI Enter | S3 247 | 2024-04-25 16:55:34-0700 | ACPI Wake | S3 248 | 2024-04-25 16:55:34-0700 | Wake Source | GPE # | 67 249 | 2024-04-25 17:00:38-0700 | ACPI Enter | S3 250 | 2024-04-25 17:00:47-0700 | ACPI Wake | S3 251 | 2024-04-25 17:00:47-0700 | Wake Source | GPE # | 67 Also suspend to S0ix and wakeup using Trackpad. Change-Id: If1a275e42c6c7ad743eedc9cd3320776008bfd62 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-29mb/google/brya/xol: Add Fn key scancodeAseda Aboagye
The Fn key on Xol emits a scancode of 94 (0x5e). BUG=b:327656989 TEST=Flash xol, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I34ed93d9666504bfd4d439e166911e49f58e5ff5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82069 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-26mb/framework: Push initial port of azalea (Framework 13 AMD 7040)Martin Roth
This is a minimal framework that allows the build to compile. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ief4b5c75471a2ef5bedaaee9b4737510c2826b6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-26mb/google/rex: remove duplicate config for karisYH Lin
Remove duplicate config entry CHROMEOS_WIFI_SAR as it is used at the baseboard. BUG=None TEST=emerge-rex coreboot Change-Id: Iabf0e490103c2097f3f033036839b77b5a0bb1b3 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81226 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-25mb/google/brox/var/lotso: Add fw_config field for storagetongjian
Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config field to prevent depthcharge build break. BUG=b:333494257 TEST=emerge-brox coreboot depthcharge sys-boot/chromeos-bootimage Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82056 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel moduleDaniel_Peng
1.Enable CHROMEOS_WIFI_SAR flag to load a SAR table for Intel module. 2.Describe the FW_CONFIG probe for the settings on glassway. - WIFI_SAR_0 for Intel Wi-Fi module AX211 BUG=336051631 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81781 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25mb/google/brya/var/nova: Add initial configurationsKenneth Chan
Upload initial configuration for nova based on proto schematics. Memory: SAMSUNG 2G*4 K4U6E3S4AB-MGCL HYNIX 2G*4 H9HCNNNBKMMLXR-NEE BUG=b:328711879 TEST=FW_NAME=nova emerge-constitution coreboot chromeos-bootimage Change-Id: Ic9ff3ed2fb3a7f0f100385d0a0444d38fcff5c51 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2024-04-25mb/google/nissa/var/yaviks: Add stop pin for G2 touchscreenWisley Chen
Add stop pin control for G2 touchscreen BUG=b:335803573 TEST=build and verified Touchscreen work normally Change-Id: I7e0bbc7722cdda6bcca0485009fcf8510b1f55e2 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81971 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25mb/google/corsola/var/wugtrio: Add STA_ER88577 MIPI panelYang Wu
Add STA_ER88577 MIPI panel for Wugtrio. Datasheet: 2081101BH8028073-50E_Pre Spec_240424.pdf BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I279d431d80ca0770540d88e213d4aeafe77038ce Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82055 Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-24mb/dell/optiplex_9020: Implement late HWM initializationMate Kukri
There are 4 different chassis types specified by vendor firmware, each with a slightly different HWM configuration. The chassis type to use is determined at runtime by reading a set of 4 PCH GPIOs: 70, 38, 17, and 1. Additionally vendor firmware also provides an option to run the fans at full speed. This is substituted with a coreboot nvram option in this implementation. This was tested to make fan control work on my OptiPlex 7020 SFF. NOTE: This is superficially similar to the OptiPlex 9010's SCH5545 however the OptiPlex 9020's SCH5555 does not use externally programmed EC firmware. Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81529 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-24mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jackJianeng Ceng
Add a new GPIO port cbj-sleeve for kernel driver to call. At the same time, a new rt5645 driver is added to replace the generic driver to parse gpio. After entering the system, it is pulled high by the kernel to enable the MIC function. BUG=None TEST=MIC function is normal Change-Id: I093be6a3e357aae389fcbe8291a9701c40b62e15 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81774 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-23mb/google/rex/var/deku: Update USB _PLD valuesTony Huang
Fix custom_pld for USB2-C2 and USB3-C3 with same PLD group. Update USB2-A4 PLD group token. USB2/USB3 Type-C Port C2 "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))" USB2/USB3 Type-C Port C3 "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))" BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST= emerge-ovis coreboot Change-Id: Ieecf0f7dda671a421e4e4a4adbf83240fadd018d Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-23mb/google/rex/var/deku: Configure GPIOTony Huang
Set unused pin to NC internal PU 20K BUG=b:325674908 BRANCH=firmware-rex-15709.B TEST= emerge-ovis coreboot Change-Id: I78eddaa41c14721eeb6ff33a4cb15382853e430b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-22cpu/intel/model_206ax: Allow to configure VR settingsPatrick Rudolph
Allow to set board specific CPU voltage regulator settings. The VR12 compatible voltage regulator for the CPU can be configured by two MSRs. Currently a default value is applied, which mimics the Intel reference code and is what the BWG suggest. However most board vendors fill in the actual VR parameters to support OC or ULV board variants. When the mainboard design is too different from the Intel reference design, not updating the VR settings might result in: - unstable system behaviour - limited turbo performance - excessive battery drain - no over-clocking capability This patch adds support to set the board specific current limit for Icc and Igfx. It also allows to adjust PSI1, PSI2 and PSI3, which are powerstates used by the VR, that consume less energy when the system is idle. Test on Lenovo X220 with full CPU load after 1 minute, compared to previous code with default settings: - Limiting PP0 max current below Iccmax results in less CPU performance. RAPL readings show that less power is drawn over time. - Limiting PP0 max current to Iccmax results in equal CPU performance. RAPL readings show that the same power is drawn over time. - Setting the PP0 max current to a value >> Iccmax results in equal CPU performance. RAPL readings show that the same power is drawn over time. - Updating the MSR at runtime has no effect. Change-Id: I59edab47fc4fbe0240e1dd7d25647f7549b4def2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-22acpigen_ps2_keybd: Add assistant key to linux,keymapAseda Aboagye
If the ChromiumOS EC indicates that the device has an assistant key, we should also add it to the generated linux,keymap binding. This commit simply does so by examining the keyboard capabilities reported by the EC. BUG=b:333088656 TEST=With a device that has an assistant key, flash AP FW and verify that the key is mapped to `KEY_ASSISTANT` in the Linux kernel using `evtest`. Change-Id: I217220e89bce88e3045a4fc3b124954696276442 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81996 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-04-22mb/google/nissa/var/craaskov: modify 6W and 15W DPTF parametersIan Feng
The DPTF parameters were defined by the thermal team. Based on thermal table in 330817690#comment33. Set 6w "tcc_offset" to "15" by fw_config. BUG=b:330817690, b:290705146 BRUNCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I19100d960919dc3087fd067c24659de467eea276 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81997 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-04-19mb/google/brox/variants/lotso: add missing hda_verb.hFelix Held
Commit 00b40090aecf ("mb/google/brox: Move hda verb to variant dir") introduces a variant-specific file for the HDA verb tables, which commit 1bf0c3f1897c ("mb/google/brox: Create lotso variant") was missing which caused the build to fail when both patches were submitted. To fix the tree, add this file to the newly created lotso variant. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8a85115a204d9d9447a58da71eb65b1de963023d Reviewed-on: https://review.coreboot.org/c/coreboot/+/82014 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-19mb/google/brox: Create lotso variantKun Liu
Create the lotso variant of the brox reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:333494257 BRANCH=None TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_LOTSO Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-04-19mb/google/brox: Move hda verb to variant dirtongjian
Others variant boards might use diff HDA Codec, so move hda verb to brox variant dir. BUG=b:314702466 BRANCH=None TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Device list: cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name ALC256 cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name Realtek Headphone detection: evtest 8 Event: time 1713404716.656768, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1 Event: time 1713404716.656768, -------------- SYN_REPORT ------------ Event: time 1713404722.802661, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0 Event: time 1713404722.802661, -------------- SYN_REPORT ------------ Change-Id: Id987c248c37dc8bdc63be7a2513fa8997b5ddc33 Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81945 Reviewed-by: Poornima Tom <poornima.tom@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-19mb/asus/p8z77-m: Squelch PNP error about 2e.b irq 70Fabian Groffen
[ERROR] PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I2231afd67031c963045b6e7930d239368c723aa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75142 Reviewed-by: Keith Hui <buurin@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-19mb/asus/p8z77-m: Disable deep sleepFabian Groffen
One can argue whether or not this is desirable, but disabling this means you cannot use power from the USB ports when the board shuts down, which is better controlled from an option, but at the very least disabled so as to replicate default vendor firmware behaviour. Disable deep sleep like it is disabled on all other variants. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I660f2efebf197df055ee7b9c349e4c2b64bda6cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/75139 Reviewed-by: Keith Hui <buurin@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-19mb/asus/p8z77-m: Enable Port 80 UARTFabian Groffen
Copied this bit from asus/p8z77-m_pro, without it a GRUB2 payload will get stuck in an endless loop showing Unknown key 0xff detected whenever there is an USB device (such as a keyboard) connected. In this mode GRUB2 is so busy showing this message repeatedly that no other keypress ever gets handled, and thus no other remedy is possible than a reset via mb pins and unplugging the USB device. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Iebd433e2762a69241257e1b4f859319536a8d8f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75138 Reviewed-by: Keith Hui <buurin@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-19mb/google/brox/var/greenbayupoc: Add fw_config field for storageEren Peng
Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config field to prevent depthcharge build break. BUG=b:333325006 TEST=emerge-brox coreboot depthcharge with no errors Change-Id: I0e220787d6ac73ec8fa2469ed958981d0801920e Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-04-18mb/dell/optiplex_9020: Add support for TPM1.2 deviceMate Kukri
These machines come with a TPM1.2 device by default. It is somewhat obsolete these days, but there is no harm in enabling it. Change-Id: Iec05321862aed58695c256b00494e5953219786d Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-18mb/asus/p8z77-m: Disable WDT1Fabian Groffen
WDT1 is currently enabled but gives these errors: [ERROR] ERROR: Resource didn't fit!!! PNP: 002e.8 60 * size: 0x8 limit: fff io [ERROR] PNP: 002e.8 60 io size: 0x0000000008 not assigned in devicetree Therefore, just disable it, like it is disabled on all other variants. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Ie33c219eae60f55d272b261480283a02c2d502e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75144 Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-18mb/asus/p8z77-m[_pro]: Blink power LED during suspendKeith Hui
Set GPIO27 of PCH to blink before going to sleep. This blinks the power LED. Revert after waking up. Tested on p8z77-m. Power LED blinks in suspend. Change-Id: Ie1b40ae17fa2ef397585b86ac82730099b611dda Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-18mb/asus/p8z77-m[_pro]: Correct PCH GPIO configKeith Hui
According to a boardview, GPIO27 is connected to the front panel power LED, and should be output. It will be made to blink before entering S3 suspend in a follow-up. Change-Id: I7e47f63999e8c0bfbd37e3273d33c00bc035bcbb Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-18mb/google/nissa/var/glassway: Add SPD IDs for two new memory partsDaniel_Peng
Support Memory for Hynix H58G66AK6BX070 and Samsung K3KL9L90CM-MGCT in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign H58G66AK6BX070 4 (0100) K3KL9L90CM-MGCT 5 (0101) BUG=b:335341310 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/glassway/memory/ \ src/mainboard/google/brya/variants/glassway/memory/\ mem_parts_used.txt" Change-Id: Ic07ec36a8015ce6433196a93e894b818a515b954 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81955 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
2024-04-17mb/google/brox: Enable SAGvAshish Kumar Mishra
Enable SaGv support for brox BUG=None BRANCH=None TEST=Boot brox with SAGv enabled and verify in fsp debug logs Change-Id: I80c44e7df1d75732c6982b27e44ecd6060b1b3f1 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81556 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-17mb/google/brya: Enable UFS driver for edk2 payloadMatt DeVillier
Several brya-based boards use UFS for storage, so enable the edk2 UFS driver when using the edk2 payload. TEST=build/boot google/brya (banshee, craaskov), verify internal boot media functional with edk2 payload. Change-Id: I3dc018582e974bf73c7668f78da9b81eeb038c01 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81871 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-17mb/google/zork: Enable eMMC driver for edk2 payloadMatt DeVillier
Several zork-based boards use eMMC for storage, so enable the edk2 eMMC driver when using the edk2 payload. TEST=build/boot google/zork (morphius, vilboz), verify internal boot media (both eMMC and NVMe) functional with edk2 payload. Change-Id: Ib7e98f309594554dbcf1ddd875d47c89bd9e0e44 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-17mb/google/corsola: Add new board variant VeluzaFrank Wu
Add a new Krabby follower device 'Veluza'. BUG=b:333630131 BRANCH=corsola TEST=none Change-Id: Idedcbfbddd6d98a51cf28a0963d68f6d8c68382c Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81791 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-17mb/up/squared: Make mini PCIe port mode configurableReto Buerki
Add config choice menu and pad configuration to put Mini PCIe port into mSATA mode. The vendor firmware's "Chipset->Mini PCIe / mSATA Switch" option has been used together with the output of inteltool and intel2pm to deduce the exact pad configuration. Note: the vendor firmware does not autodetect the mode, and the default setting for the port is "Mini PCIe". Tested with Kingston SUV500MS120G mSATA SSD. Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Signed-off-by: Reto Buerki <reet@codelabs.ch> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-16mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)Joel Linn
This is another readily available (used market) system. Based on autoport. * All peripherals should work. * Automatic fan control as well as S3 are working. * The board was tested to boot Linux and Windows. EHCI debug is untested. * When using MrChromebox edk2 with secure boot build in, the board will hang on each boot for about 20 seconds before continuing. There are some quirks for doing the first flash, see the documentation. Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-16mb/google/nissa/variant/sundance: Modify i2c device for touch deviceLeo Chou
1. Remove non-use i2c address 0x10, 0x24 and 0x40 of touch IC for touch screen 2. Add new i2c address 0x5d of Goodix touch IC for touch screen 3. Add new i2c address 0x38 of Focal touch IC for touch pad BUG=b:333804572 TEST=FW_NAME=sundance emerge-nissa coreboot chromeos-bootimage Change-Id: I8e2c60820a07b99b69860fd4f6557b448aef2341 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-16mb/google/nissa: Create pujjoga variantLeo Chou
Create the pujjoga variant of nissa reference board by copying the template files to a new directory named for the variant. Due to new_variant.py limitation that repo can no longer be used in inside, created this CL manually following google suggestion. BUG=b:333839287 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJOGA Change-Id: Ia8eb11eb65f9013e83abd45eefe7705d05b8697e Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81891 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-16mb/packardbell/ms2290: Correct header includedKeith Hui
It uses ibexpeak southbridge and should include its pch.h, not bd82x6x's. TEST=Timeless binary did not change. Change-Id: Iafa83b7f3c1cd2d8ab9af51aa331ca673d9a66df Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-15mb/google/zork: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot zork (morphius) with SMMSTORE enabled. Change-Id: Ifd3be9b0757e270d2f106e2fbebf3991e49dec65 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15mb/google/skyrim: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot skyrim (frostflow) with SMMSTORE enabled. Change-Id: I34f9d27c27ab7148dfc530322f741a576c348de7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15mb/google/myst: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. Change-Id: Ic45324b8c5bbd205e889e934c9d5dd17f7775152 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81867 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15mb/google/guybrush: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot guybrush (dewatt) with SMMSTORE enabled. Change-Id: Ic4fdacd493d83fa3c1683a06d1276b0190f6db8b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15mb/amd/*: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. Change-Id: I04d57ff7f74d79118652cfe227cf223375df6472 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81865 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15mb/google/fizz: Use variant-specific gma-mainboard.ads filesMatt DeVillier
The karma variant, being a Chromebase, has an internal eDP output for the built-in display whereas the fizz/endeavour variants do not. Use separate gma-mainboard.ads files so that karma's internal panel works properly with libgfxinit. TEST=build google/fizz (fizz/karma) with libgfxinit enabled, ensure correct gma-mainboard.ads file is included in the build. Change-Id: Ia6aca538ba8c13b48aa80901222071d704b5f0c0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-15mb/google/brox: Create greenbayupoc variantEren Peng
Create the greenbayupoc variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:329530883 BRANCH=None TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_GREENBAYUPOC. Change-Id: I90936d97b41e59c49dd92997146caf580bce1f4f Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-15mb/google/corsola: Add new board variant SkittyHerbert Wu
Add a new Krabby follower device 'Skitty'. BUG=b:331702790 TEST=emerge-corsola coreboot chromeos-bootimage BRANCH=corsola Change-Id: I2f12bccfda591a5baf8d23d217b6f1f81b059d15 Signed-off-by: Herbert Wu <herbert1_wu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81772 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Geoffrey Chien <geoffrey_chien@pegatron.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Shawn Ku <shawnku@google.com>
2024-04-15src/mb: Rename new Makefile.inc files to Makefile.mkMartin Roth
These files were added after the switch. Change-Id: I1986e4f921e0e56fe5255433d4b9216dc7c4dc59 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81856 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-13mb/samsung/stumpy: Set initial fan PWM to 30%Matt DeVillier
Recent changes to the ITE 8772F SIO code caused the initial fan PWM to change from 0 to 50%; set it to 30% to reduce fan noise while still providing some temp control before the OS/ACPI takes over. TEST=build/boot stumpy to payload, verify fan noise is negligible. Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81514 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-13mb/google/beltino: Set initial fan PWM to 30%Matt DeVillier
Recent changes to the ITE 8772F SIO code caused the initial fan PWM to change from 0 to 50%; set it to 30% to reduce fan noise while still providing some temp control before the OS/ACPI takes over. TEST=build/boot google/beltino to payload, verify fan noise is negligible. Change-Id: I0177235d73e051f02b5333cf1d735556382b919f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81513 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-13superio/ite: Unify it8772f with common codeJoel Linn
The it8772f is now configured by the much better common code that is used for other chips in the family as well. This mainly concerns the EC, the GPIO functionality was not moved to common as it currently lacks a sane abstraction in any codebase. The datasheets of the it8772e(f) and it8728f (for reference) were studied and verified against the common code, adding exceptions where needed. Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-13lenovo/haswell: enable ONBOARD_VGA_IS_PRIMARYLeah Rowe
Haswell ThinkPads have Nvidia Optimus wired in on some models. With recent coreboot changes, legacy VGA decode is now disabled on the iGPU, and the iGPU itself is disabled, when a dGPU is present. This is a problem on Optimus laptops, because it means that the Intel GPU would be effectively disabled, when it is the one that has to handle the framebuffer. On these boards, you can enable ONBOARD_VGA_IS_PRIMARY so that coreboot does not disable the iGPU. This is because on Optimus laptops, the Nvidia GPU is only used for offloaded rendering. Enable ONBOARD_VGA_IS_PRIMARY by default on these boards. Change-Id: I8f1e0ca2861d1cc9a9ad41e7c9257aeca1a62a31 Signed-off-by: Leah Rowe <info@minifree.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81645 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12mb/google/brox: Initialize NOTE_BOOK_MODE GPIOShelley Chen
The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. Also initializing it (if ISH is enabled) to be NF2 (ISH_GP4). Also took the liberty of alphabetizing all the ISH GPIOs to they're easier to search through. BUG=b:316421831 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Make sure that brox device still boots up with this change. Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81789 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12mb/dell/optiplex_9020: Fix SATA port mapsMate Kukri
Previously incorrect sets of SATA ports were enabled. There are no publically available schematics, but I am almost certain the new values are correct. The original 0x33 value was carlessly copy pasted, and only enables ports 0, 1, 4, 5, leaving 2, 3 disabled. On the SFF, with 0x33 only the first 2 ports worked. I have verified by plugging in devices under the stock firmware that 0, 1, 2 are the ones that should be enabled, so setting the value to 0x7 per datasheet. This was also tested in practice to work. I don't have an MT, but I was told the two white ports didn't work with 0x33, so those are most certainly ports 3, 4, hence me setting the value to 0xf. If the MT's working ports are port 0, 1 on the PCH this is correct. Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/81550 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12tree: Drop duplicated <stdarg.h> and <stdio.h>Elyes Haouas
<string.h> is supposed to provide <stdarg.h> and <stdio.h> Change-Id: I021ba535ba5ec683021c4dfc41ac18d9cebbcfd2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81853 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12mb/google/brya/var/sundance: Add GPIO tableLeo Chou
Fill GPIO table for Sundance. BUG=b:327520553 TEST=emerge-nissa coreboot Change-Id: I53ed5874347006985ca5231d1531fa519088f796 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81613 Tested-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-04-11tree: Drop unused <timer.h>Elyes Haouas
Change-Id: Ib454330c5f584760c47ff0127a720cec5773b922 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-04-11tree: Drop unused <edid.h>Elyes Haouas
Change-Id: I66265727b68b6ad10722439314b466298dbfff28 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81821 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11tree: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11mb/google/nissa/var/craaskov: Disable external fivrIan Feng
In next phase, craaskov will remove external fivr. Use the board version to config external fivr for backward compatibility and show message. BUG=b:330253778 TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS work normally. Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81607 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-11mb/google/karis: Add FW_CONFIG and device for VPUJamie Ryu
BUG=b:333605309 TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0) is enabled when bit20 is set, and disabled when cleared. Change-Id: I6e2230715d783ea7108d71699fd19684ce19e2ff Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-11mb/google/brya: Create trulo variantDinesh Gehlot
This patch adds a new variant trulo for the baseboard trulo. BUG=b:333314089 TEST=abuild -a -x -p none -t google/brya Change-Id: I91157d252ef56c8938bfc08ed0f734c5dc7e614d Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81627 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-04-11mb/google/brya: Add new baseboard truloDinesh Gehlot
This patch adds a new baseboard trulo. This commit is a stub which only adds the minimum code needed for a successful build. BUG=b:333314089 TEST=abuild -a -x -p none -t google/brya Change-Id: Iad6230064c6b8359698d37c3e0440614cc7b073d Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-11tree: Drop unused <string.h>Elyes Haouas
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0Shuo Liu
MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and POSTCAR_STAGE which are used by all Xeon-SP platforms. After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0 is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X, POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE. TEST=Build and boot on intel/archercity CRB Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81783 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10tree: Drop unused <elog.h>Elyes Haouas
Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10tree: Drop unused <stdio.h>Elyes Haouas
Change-Id: I26c2abfce3417ed096d945745770fcae91a1e4ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81814 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10mb/google/corsola/var/wugtrio: Correct the display orientationYang Wu
Set orientation of KD_KD101NE3_40TI to LB_FB_ORIENTATION_RIGHT_UP to align the volume up/down direction with menu up/down in FW screen. BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage, and check FW screen on wugtrio, test volume key behaves as expected. BRANCH=corsola Change-Id: Ie101cc8b983d3d16587f88fa787ed622e59d27eb Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81752 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10mb/google/brya: Remove baseboard-specific FMD namesDinesh Gehlot
This patch renames the 16MB FMD file to remove the baseboard-specific name 'Nissa'. This allows other supported baseboards to utilize the 16MB SPI flash. Additionally, the patch attempts to create a generic, unified 32MB FMD file for both brya and nissa variants. BUG=b:333314089 TEST=Build and boot Nivviks. Change-Id: I9151a4bcbe9cc084cc19b1a3e91c0321fe4dcc37 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81676 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <delay.h>Elyes Haouas
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09mb/google/*: Drop unused header file console/console.hRuihai Zhou
The header file console/console.h is unused, just drop it. TEST=abuild -t google/corsola -b wugtrio -a TEST=abuild -t google/geralt -b ciri -a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: If3689afe532b63384b7905116c44c598e5fa13ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/81685 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-04-08mb/google/brox: Update verb table to fix headset detectionPoornima Tom
Correct verbtable value for pin widget 20 of Realtek ALC256 based on the updated verbtable received from Realtek. Updated Version : 5.0.3.1. This fixes the headset detection failure, when power_save is enabled in legacy hda driver. BUG=b:330433089 BRANCH=None TEST=Verified headset on Brox When connected to audiojack in power_save state of legacy hda driver, headset is detected and audio is resumed. Change-Id: I71b7d59b3ab5310a0b6cdb31fb5033f94263d151 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81654 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Terry Cheong <htcheong@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-08mb/google/brya: Sort Kconfig option alphabeticallyVarshit Pandya
Change-Id: I878c14058e1edc0f64e37c2fc16b8dcf75b90192 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81631 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-04-04mb/google/screebo: Add FW_CONFIG and device for VPUJamie Ryu
BUG=b:332488817 TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0) is enabled when bit20 is set, and disabled when cleared Change-Id: I6d7b35dbf8ac9b0abb42f64a947b4bb94f3c6b0f Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Daniel Kang <daniel.h.kang@intel.com>
2024-04-04mb/google/nissa/variant/sundance: Update devicetree settingsLeo Chou
Based on schematic and gpio table of sundance, generate overridetree.cb settings for sundance. BUG=b:328505938 TEST=FW_NAME=sundance emerge-nissa coreboot chromeos-bootimage Change-Id: I857be7bc7f98281cac57fef85bf9f3cef2ec14e9 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-04mb/google/nissa/var/gothrax: Add touchscreen driver for ILI2901A-A210Yunlong Jia
I2C slave addresses 0x41. BUG=b:332458912 BRANCH=None TEST=emerge-nissa coreboot & working correctly in DUT Change-Id: I2d26bfd4f415aa128b6256f83bc58987b15a557a Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81610 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04mb/google/brya/var/xol: Reduce power limits according to battery statusSeunghwan Kim
When battery level is below critical level or battery is not present, cpus need to run with a power optimized configuration to avoid platform instabilities such as system power down. This will check the current battery status and configure cpu power limits using current PD power value. BUG=b:328729536 BRANCH=brya TEST=built and verified MSR PL2/PL4 values. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) [When connected 60W adapter without battery] Before: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:114000000 After: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:60000000 [When connected 45W adapter without battery] Before: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:114000000 After: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:45000000 constraint_2_power_limit_uw:45000000 Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81614 Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-04mb/google/nissa/var/anraggar: Set EN_SPK_PA to low to avoid noiseJianeng Ceng
In order to avoid the noise caused by the codec output to the audio jack during the shutdown and poweron process, we will use GPP_A11 for the codec power supply gate, keep low during the startup process, and wait for the driver to turn on. This change does not affect the beep output of depthcharge. BUG=None TEST=There is no squeaking sound when turning on and off Change-Id: I5982be5a8d965086b46861f4c2c758d9bdee6e75 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81629 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-03mb/{bd/bd_egs, iventec/transformers}: Fix building with x86_64Arthur Heymans
This fixes a warning about casting an integer to a pointer, where the integer has a different size than the pointer (UINT32). Change-Id: Iceb7cb1dbdc6f5397823a1737e3baeac96966a78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81559 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-03mb/google/corsola: Add new board variant WugtrioYang Wu
Add a new Staryu follower device 'Wugtrio'. And also enables SD card support and MIPI panel support. BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I586de68da4d0ee2dd5b7baea92ebb06db9fcfe8b Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81585 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-03mb/google/corsola: Move MIPI panel selection to BOARD_SPECIFIC_OPTIONS sectionYang Wu
Move starmie mipi panel selection from BOARD_GOOGLE_STARYU_COMMON section to BOARD_SPECIFIC_OPTIONS section. BUG=None TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: Ib5792542f55a78c0840b6169b5ecf092e7cefe98 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81602 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-04-02mb/google/brox: Enable PMC pins to work with PDAshish Kumar Mishra
Enable SMLINK1 interface for PMC-PD communication to configure Type-C muxes. Refer RPL EDS vol 1: 765585. BUG=b:327622474 BRANCH=None TEST=Boot image on SKU2 and check PMC-PD working. Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81207 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Deepti Deshatty <deepti.deshatty@intel.com>
2024-04-02mb/google/brya: Make get_soc_power_limit_config() a public functionSeunghwan Kim
Make get_soc_power_limit_config() a public function to use on brya variants. Add prefix 'variant_' for it. BUG=None BRANCH=brya TEST=emerge-brya coreboot Change-Id: I31f938938e7c9da49c2aa7b52dd4b5f46f793495 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81616 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-02mb/google/nissa/var/sundance: Generate SPD ID for 4 supported memory partsLeo Chou
Add sundance supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6EE BUG=b:332201349 TEST=Use part_id_gen to generate related settings Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81612 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-02mb/google/rex/var/deku: Swap LAN device indices for correct MAC addressTony Huang
Deku has two Ethernet ports. Currently both get assigned the wrong MAC address due to the LAN devices indices being swapped and vpd ethernet_mac0() affects device eth1 and vpd ethernet_mac1() affects device eth0. Correct the device indices for LAN devices so ethernet_mac[0-1] in vpd can apply to the correct ethernet ports. BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=vpd -s ethernet_mac0=<mac address0> vpd -s ethernet_mac1=<mac address1> reboot the system and check ifconfig eth0 and eth1 MAC addresses are fetched correctly Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81564 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-04-01mb/google/{brya,hades}: use soc index for variant_update_power_limits()Seunghwan Kim
The power_limits_config variable for ADL/RPL is array data, but we got soc_power_limits_config variable without its index. So correct the code to get the proper pointer of the data for current CPU SKU. I tried to override the PL4 value to 80W from 114W with following table in ramstage.c as a test for bug b/328729536. ``` const struct cpu_power_limits limits[] = { {PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000}, } ``` And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool. - Before this patch: msr_pl4 was not changed, it's always 114 - After this patch: msr_pl4 was changed to 80 BUG=None BRANCH=None TEST=Built and tested the function could adjust PL4 on xol in local. Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-01mb/google/brya/var/xol: Update GPIO settings for speaker and DMICSeunghwan Kim
Update GPIO configuration according to the schematic changes. The locations of speaker and DMIC are swapped. - Speaker: I2S2 -> I2S1 - DMIC: GPP_S2/GPP_S3 -> GPP_R4/GPP_R5 BUG=b:318584606 TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I3468d79f33d9d9ef8377ccf0f8f628956b02d3c3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81444 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-01mb/google/brox: Configure ISH device based on FW_CONFIGKarthikeyan Ramasubramanian
ISH Firmware name needs to be configured only when full sensing capabilities are enabled through ISH_ENABLE FW_CONFIG. Similarly DMA property needs to be added only when UFS is enabled through STORAGE_UFS FW_CONFIG. Hence configure the ISH device at run-time based on FW_CONFIG. BUG=b:319164720 TEST=Build Brox BIOS image and boot to OS. Change-Id: I678416acd48e03ab77ae299beae6e295a688b8df Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81418 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-01mb/google/nissa/var/glassway: Add 2nd Synaptics touchpadFrank Chu
Add Synaptics touchpad via HID-I2C interface in I2C5 bus for glassway. BUG=b:331677400 BRANCH=firmware-nissa-15217.B TEST=emerge-brya coreboot and check touchpad function work. [INFO ] input: PNP0C50:00 06CB:CE9B Touchpad as /devices/pci0000:00/0000:00:19.1/i2c_designware.5/i2c-17/i2c-PNP0C50:00/0018:06CB:CE9B.0001/input/input4 [INFO ] hid-multitouch 0018:06CB:CE9B.0001: input,hidraw0: I2C HID v1.00 Device [PNP0C50:00 06CB:CE9B] on i2c-PNP0C50:00 Change-Id: Ifbb2cb750a80bc6e8f96609257dcd1e695ad1fa4 Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-01mb/google/nissa: Create sundance variantLeo Chou
Create the sundance variant of nissa reference board by copying the template files to a new directory named for the variant. Due to new_variant.py limitation that repo can no longer be used in inside, created this CL manually following google suggestion. BUG=b:328505938 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_SUNDANCE Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81347 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2024-04-01mb/google/corsola: Add new board variant 'Kyogre'Kei Hiroyoshi
Add a new Kingler follower device 'Kyogre' BUG=b:318614302 TEST=emerge-corsola coreboot Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c Signed-off-by: Kei Hiroyoshi <hiroyoshi.kei@fujitsu.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81218 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-03-30mb/acer: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I335487ca1b17ab958c0d0238f425b92b430014ca Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30mb/inventec: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I51dd9eb5a2fef5800670f981275139e932af2be0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81493 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30mb/google: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-03-30mb/emulation: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I7071cbcc26e2080020e83b894cf4ac4ef46913c3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30mb/amd: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I2dae34441909f6135b95e7b017659ce4f4666b4e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-28cpu/x86: Link page tables in stage if possibleArthur Heymans
When switching back and forth between 32 to 64 bit mode, for example to call a 32-bits FSP or to call the payload, new page tables in the respective stage will be linked. The advantages of this approach are: - No need to determine a good place for page tables in CBFS that does not overlap. - Works with non memory mapped flash (however all coreboot targets currently do support this) - If later stages can use their own page tables which fits better with the vboot RO/RW flow A disadvantage is that it increases the stage size. This could be improved upon by using 1G pages and generating the pages at runtime. Note: qemu cannot have the page tables in the RO boot medium and needs to relocate them at runtime. This is why keeping the existing code with page tables in CBFS is done for now. TEST: Booted to payload on google/vilbox and qemu/q35 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-27mb/google/nissa/var/anraggar: Modify the GPP_F15 of pen to EDGE_BOTHQinghong Zeng
Currently, simply changing the wake event configuration to ANY does not completely resolve the issue of inserting a pen not waking the system. The pen actually needs to wake up the system both when plugged in and when pulled out. This is because in the pen's GPP_F15 configuration, the original attribute is EDGE_SINGLE, which should be changed to EDGE_BOTH. BUG=b:328351027 TEST=insert and remove pen can wakes system up. Change-Id: I1823afd0bcb86804227117d2d5def38788bc7387 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81441 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-27mb/google/brya: Create yavista varianthsueh.rasheed
Create the yavista variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:321583226 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVISTA. Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Signed-off-by: Hsueh Rasheed <hsueh.rasheed@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80342 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 13:47:37 +0000