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De-assert PERST# at romstage to reduce the waiting time in ramstage.
BUG=b:361728592
TEST=The boot time improves 62ms
Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Looking at Intel document 759603 revision 001, Alder Lake N only has 5
PCIe clock outputs and clock request pins. I only have the version 2 of
this board which has a significantly different USB port configuration to
version 1, but there the Ethernet controller on RP 11 and the E key m.2
slot on RP 12 share the last PCIe clock output. The on-board TUBF0304
clock buffer chip takes the clock output form the last PCH PCIe clock
generator output and drives the clock inputs of both the last Ethernet
chip and the E key m.2 slot. Since the last clock output is always
active, since RP 11 has the PCIE_RP_CLK_REQ_UNUSED flag set, using the
non-existent clock output and request for RP 12 didn't break things.
ASPM L0s might still work though, since that one doesn't involve
switching off the PCIe reference clock, but haven't tested that yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I103f7c3fe0b806f5c0a5202b8221f522a4b1c378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83911
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It may come with 8th or 9th Gen CPUs. i5-8500T has been tested here.
Works:
- Serial adapter from daughter board (COM1 connector)
- USB ports front and back
- USB-C port (charging, data)
- HDMI
- Ethernet
- SATA
- NVMe
- internal speaker
- TPM2.0
- PCIe x8 port (x8 riser tested, x4 not)
Does not work:
- front audio jacks
Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80609
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Extend 1 bit [34] for the TOUCHSCREEN_SOURCE.
SSFC range for TOUCHSCREEN_SOURCE is bit[32:34].
2. Touchscreen panel: MUTTO A153728S1Y,
and set TOUCHSCREEN_ILIT2901 to value "4"
3. Datasheet: #153728S1V1.0 SPEC_20240923.pdf
BUG=b:375986645
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: I6e13c948edca5a894e1a00a1954f0f88c4a079cf
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84894
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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commit 6c83a71b0a80 ("skl mainboards/dt: Move usb{2,3}_ports settings
into XHCI device scope") not only moved the USB port definitions under
the XHCI device reference, but also combined multiple register
definitions. In doing so, it broke the inheritance from the baseboard,
since the variant overridetree registers now replaced the entire
usb2_ports/usb3_ports structs, rather than replacing individual array
elements therein. This resulted in any USB ports inherited from the
baseboard and not overridden by the variant being non-functional as they
were not included in the resulting combined devicetree.
To fix this, return to overriding individual array elements in the
usb2/3_ports structs.
TEST=build/boot google/fizz/var/karma. Verify all USB ports present and
functional. Verify mainboard/static.c in built shows all ports.
Change-Id: I0e80bf4949a857c21d44537eb720a7a8a7db2f80
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84955
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures the ESPI_SOC_ALERT_L GPIO pad on fatcat as
NC to enable S0ix low power entry.
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84957
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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Package C-state auto demotion feature allows hardware to determine lower
C-state as per platform policy. Since platform sets performance policy
to balanced from hardware, auto demotion can be disabled without
performance impact.
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: I01f2cb8ac1093ae98cc076e35ad1924baa53aa59
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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1. Modify the I2C frequency of the touchpad between 380 Khz and
400 Khz to meet the spec.
2. Increase clk the time of high (TH) to greater than 600ns.
Before:
I2C0 - 420KHz
TH - 557ns
After:
I2C0 - 398Khz
TH - 630ns
BUG=b:351968527
TEST=Check that the wave form meets the spec.
Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84898
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Add Micron part MT62F2G32D4DS-020 WT:F only for Francka.
DRAM Part Name ID to assign
MT62F2G32D4DS-020 WT:F 0 (0000)
BUG=b:373394046
TEST=emerge-fatcat coreboot
Change-Id: I2de56c8c7a028edefbd3dc53f8b1e26dee3286f7
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84781
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update device tree to support speaker o/p on MAX98357A AIC.
BUG=b:357011633
TEST=build coreboot image and test audio playback on Google/Fatcat board.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I20de87f673e947f0e2332b818ebca01c0fa5e200
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84888
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP
headers for FSP as banshee is using a converged firmware image.
This effort also helps to save banshee boot time by 80-100ms as
RPL FSP is better optimized.
Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which
saves 10ms of the boot time.
BUG=b:358254132
TEST=Able to build and boot google/banshee.
cold boot time w/o this CL
```
Total Time: 1,399,888
```
cold boot time w/ this CL
```
Total Time: 1,295,334
```
Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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From power team's recommendation, increase the VccIn Aux Imon IccMax
to 30A to meet HW settings.
BUG=b:376306118
TEST=Build firmware and check the value is changing as expected.
Paste the firmware log.
[SPEW ] VccInAuxImonIccImax= 0x78
[SPEW ] (MAILBOX) VccInAuxImonIccImax = 120 (1/4 Amp)
[INFO ] Override VccInAuxImonIccImax = 120
Change-Id: I71020c2f631cb517a52d4bb65e35277eb731ced7
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. Right now we simply
wait for 100ms in ramstage for that.
To speed up the boot time, pre-initialize PCIe by asserting PERST#
earlier in the bootblock stage. The pre-initialization time is stored
in the early init data region, so that the PCIe initialization in
ramstage could make sure the required 100ms delay is still reached.
This pre-initialization will speed up the boot time by 100ms on rauru.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I2b84c25ae3ea9069fd38fa6b20b8235a7fc3a484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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We want to configure different VBT timings for panels of different sizes
and distinguish them through SSFC. We select the reserved bit 6 of SSFC
as the flag bit. When using a 12-inch panel, set this bit to 0; when
using an 11-inch panel, set this bit to 1.
Without splitting, the platform_BootPerf test will fail.
BUG=b:374428465
TEST=
1. can match VBT with SSFC
-When SSFC is set to 0x40:
$ cat /sys/firmware/log | grep vbt
Bit 6 of SSFC is 1, use vbt-teliks_panel_11_inch.bin
CBFS: Found 'vbt-teliks_panel_11_inch.bin' @0x1c6140 size 0x50f in mcache @0x76adda14
-When SSFC is set to 0x0:
$ cat /sys/firmware/log | grep vbt
Bit 6 of SSFC is 0, use vbt-teliks.bin
CBFS: Found 'vbt-teliks.bin' @0x1c5bc0 size 0x50e in mcache @0x76add9b0
2. can pass platform_BootPerf test
The platform_BootPerf time measured for all SKUs is less than 1.55s.
Change-Id: Ia8fb45aede5ead4826d983760506c366a70643ee
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84871
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This commit adjusts the EC host command range for the Fatcat board to
0x800-0x807 & 0x200-0x20f.
This change is necessary because the microchip EC used on the Fatcat
board has a smaller host command range than the ITE/Nuvoton ECs used
on other Fatcat variants.
The `gen1_dec` register in the devicetree is updated to reflect this
change.
As per boot log, the `gen1_dec` aka offset 0x84, base address is 800
and size is 8 bytes.
AP FW Boot log:
[SPEW] PCI: 00:00:1f.0 resource base 800 size 8 align 0 gran 0 limit 0 flags c0000100 index 84
BUG=b:376207365
TEST=Able to build and boot google/fatcat w/o any error.
without this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
[ERROR] LPC: Cannot open IO window: 800 size 8
[ERROR] No more IO windows
with this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
Change-Id: Ifcee533341fa583d841a4b564f25831c6d04e951
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84919
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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This commit defines the EC_SYNC_IRQ and GPIO_PCH_WP macros for
different Fatcat variants.
The EC_SYNC_IRQ macro is used for tight timestamps and wake support,
while the GPIO_PCH_WP macro is used for the WP signal to the PCH.
These macros were previously undefined or incorrectly defined for some
variants. This commit fixes these issues and ensures that the macros
are defined correctly for all variants.
Specifically, this commit:
- Defines EC_SYNC_IRQ and GPIO_PCH_WP for Fatcat Nuvo and Fatcat ITE.
- Defines EC_SYNC_IRQ as 0 (not connected) for Fatcat.
- Defines GPIO_PCH_WP as GPP_D02 for Fatcat.
- Leaves EC_SYNC_IRQ and GPIO_PCH_WP as 0 (TODO) for Francka.
TEST=Able to build and boot google/fatcat.
w/o this patch:
```
cros_ec_lpcs GOOG0004:00: couldn't retrieve IRQ number (-22)
cros_ec_lpcs GOOG0004:00: probe with driver cros_ec_lpcs failed with error -22
```
w/ this patch:
```
cros_ec_lpcs GOOG0004:00: Chrome EC device registered
```
Change-Id: I9bd248496f08869c08cf6daafeed6584d0b166b7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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This patch updates the flash map layout to guarantee that the
RW_SECTION_B section starts at the 16MB boundary.
Additionally, fix typo in flash descriptor comment, where comment
incorrectly referred to "MTL" instead of "PTL".
TEST=Successfully builds google/fatcat.
Change-Id: Ia6dba611fba50f9694a75670d954a4630cde4d70
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84899
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When creating variant, it was copied from teliks, and according to the requirements of telith project, update the override devicetree to use ELAN touchscreen.
BUG=b:373510302
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power on proto board successfully
3. touchscreen is functional
Change-Id: If0da85a38f3a68b6f50cfd096a628174b313fcc9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84865
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Create the rull variant of the nissa reference board by copying
the template files to a new directory named for the variant.
And based on schematics NB7559_MB_SCH_V1_2024_1010.pdf
update devicetree settings.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:374673463
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_RULL
Change-Id: If48273f3e9db69507b41ea0313916d94ecabe309
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This change enables the integrated GPU (iGPU) display on the Fatcat
board based on the FW_CONFIG setting (specifically the DISPLAY bit).
By conditionally probing the display based on FW_CONFIG, the iGPU
is dynamically enabled or disabled according to the SKU configuration.
TEST=Verified display functionality on Fatcat with the iGPU:
> cbi set 6 0x58A814 4 (DISPLAY_ABSENT):
- lspci does not list the iGPU.
- No display output, but the device boots to the OS (verified via
console).
> cbi set 6 0x5CA814 4 (DISPLAY_PRESENT):
- lspci lists the iGPU.
- Display output is functional, showing firmware and OS UI.
Change-Id: I5762adf5ec8a86a00c16544670cb2f998055bd35
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84877
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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The iGPU device is enabled by default in the Pantherlake chipset
configuration. Remove the redundant device entry in the Fatcat
devicetree.
This change ensures that the iGPU remains enabled without explicit
configuration in the board-specific devicetree.
TEST=Able to build google/fatcat and able to see firmware and OS
display/UI.
Change-Id: I9a2ec9b47acb389f5bb6b30e61352aaefa327328
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84876
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add PCIe domain support.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I3e06dfaf79924cd5352348afaa526fc7dedbb540
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84700
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a trivial mainboard_needs_pcie_init implementation that always
return true. For now, the storage types of rauru SKUs are still unknown.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6b4f08e15f62da18aa37226075894f2827a9e7ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84697
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ideally lock configuration is not applicable for early GPIO
configuration (like bootblock/romstage) and is only required for GPIO
PAD configuration by later statge (like ramstage).
The GPP_D15 pin was previously configured with LOCK_CONFIG in the
early bootblock GPIO configuration. This is not necessary and prevents
later boot stages from configuring this GPIO.
Change-Id: Ie0e648b750d7579def39ed95eab862dc3245499c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
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Enable BT audio offload of WIFI_CNVI_WIFI6E or unprovisioned
based on fw_config.
BUG=b:373510270
TEST=Build and boot to Lotso. Verify the config from serial logs.
w/o this CL -
```
[SPEW ] -- CNVi Config --
[SPEW ] CNVi Mode= 1
[SPEW ] Wi-Fi Core= 1
[SPEW ] BT Core= 1
[SPEW ] BT Audio Offload= 0
```
w/ this CL -
```
[SPEW ] -- CNVi Config --
[SPEW ] CNVi Mode= 1
[SPEW ] Wi-Fi Core= 1
[SPEW ] BT Core= 1
[SPEW ] BT Audio Offload= 1
```
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Change-Id: I36f8c3fb24166c86d5fc4099fa9cde8cdecb9d49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84768
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:348678529
TEST=on Google Fatcat board. Set the proper CBI fw_config bit(s) and
check that the corresponding GPIO PADs are configured as expected
value accordingly.
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d54
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch updates the flash map layout to guarantee that the
RW_SECTION_B section starts at a 16MB boundary.
TEST=Successfully builds google/fatcat.
Change-Id: I74ea21a8a4107d438bc03a0da182ea7e991e74bc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Nova doesn't support thunderbolt, so disable the TBT setting.
Enabling TBT also causes the system to fail to enter S3/S5 state.
S5 fail log:
24-10-21 20:23:34.610 Port 80 writes:
24-10-21 20:23:34.610 9a02 9a32 9a14 9c15 9c18 9c19 9c20 9c22 9c25 9c28 9c3f 9c43 9c44 9c4f 9c23 9a50 9a5f 9a33 9b40 9b41
24-10-21 20:23:34.620 9b42 9b47 9c80 9c81 9c82 9c83 9a61 9a63 9a03 9a04 9a05 9a06 9a07 9a0f 9a65 9a64 9c6a 9c71 9c7f 99
24-10-21 20:23:34.626 a0 a1 72 24 25 24 25 55 24 25 55 55 73 74 75 75 75 75 75 75
24-10-21 20:23:34.633 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
24-10-21 20:23:34.639 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
24-10-21 20:23:34.643 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 76 77 79 9c
24-10-21 20:23:34.649 93 7a fe 7b f8 aa ab 96 <--new
powerinfo
24-10-21 20:23:59.424 powerinfo
24-10-21 20:23:59.424 power state 4 = S0, in 0x00ff
The correct power state for S5 is G3, not S0.
BUG=b:374213121
TEST=emerge-constitution coreboot chromeos-bootimage. Booting to OS and verify S3/S5 by EC log.
Change-Id: I2bae8ae396f001dbef3322e361f9563792e1a1ef
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84838
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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1. 2nd touch panel: INX N140HCN-EA1 C5
2. Set TOUCHSCREEN_ELAN9004 to value "3"
BUG=b:374899470
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: Ic25bd46c7cb7948e920de4fd44edb87f20cf01c4
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84834
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
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Add the new memory support:
Samsung K3LKBKB0BM-MGCP
BUG=b:374880584
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/glassway/memory/ \
src/mainboard/google/brya/variants/glassway/memory/\
mem_parts_used.txt"
Change-Id: I47d9fd64fa841a2cf60930c5e319a9130019b0a5
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84831
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
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Erying is a Chinese manufacturer selling desktop motherboards with
laptop SoCs and custom shim to mount desktop coolers.
Working:
- Serial port (IT8613E 0x3f8)
- All rear USB ports (3.0, 2.0)
- Both HDMI ports
- Realtek GbE NIC
- Internal audio (ALC897/ TGL-H HDMI)
- Environment Controller (SuperIO fan control)
- All SATA ports
- All PCI-E/M.2 ports
- M.2 NGFF WiFi
- PCI-E Resizable BAR (ReBAR)
- VT-x
WIP/Broken:
- PCI-E ASPM (also broken on vendor's FW, clocks are messed up)
- S3/s0ix (also broken on stock, setting 3VSB register didn't help -
system goes to sleep, but RAM loses power)
- DisplayPort on I/O panel (seemingly a simple fix)
- One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet)
- Automatic fan control (IT8613E can't read CPU_TIN at the moment)
Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as
vendor hasn't enabled any protections on SPI chip.
TEST=Flash coreboot build onto the motherboard, install following PCI-E
cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi.
Power the system up and boot into Windows 10 to check ACPI sanity, then
reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk
benchmark, compilation at the same time to check system's stability.
Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add and use a new helper function to determine if a device is
1) a PCIe device
2) it's mark hot-plug capable
Change-Id: I61cc013844024b43808cd2f054310cb6676ba69e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
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Use dev_find_all_devices_on_stack() to find the PCI device on a given stack.
That way open coded duplicated code can be dropped and there's no need to call
socket0_get_ubox_busno(), which allows to drop socket0_get_ubox_busno().
In addition it adds PCI multi segment support.
Change-Id: Ib0ed177ae22112a9f2ed32199409d91cb5851ede
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84790
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This disables C1 state auto-demotion to run the coreboot with
Panther Lake ES SoC without an issue.
This configuration will be remove later once the related features
are fully verified.
BUG=b:373915085
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: I384dba2918cfd04deb90284513c204fa8c21094b
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84767
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
|
|
There is no ACPI power resource for LTE module Rolling RW101R-GL,
therefore implement the power sequence of power-on, power-off, and
reset timing from GPIO init, bootstate init callbacks, and smihandler
function.
BUG=b:368450447
BRANCH=None
TEST= Build firmware and verify on jubilant with LTE:RW101R-GL.
Measure the power on, power off, and reset timing.
Run warm boot, cold boot and suspend/resume to make sure
WWAN devcie is workable.
Change-Id: I4a205e3db777c7c225d31b6cc802883fd7167089
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Update jubilant CPU PL4 from 9 watt to 14 watt for critical battery
boot. The maximum peak power is set at 14 watt which is 45W multiplied
by 32% efficiency.
Overriding power limits for AC power without battery:
PL1 (15000, 18000)
PL2 (41000, 41000)
PL4 (14)
BUG=b:364441688
BRANCH=None
TEST=Able to successfully boot on jubilant SKU1 and SKU2 with AC only.
Test on AC 65W and 45W w/o battery, and check PL4 values from log.
Change-Id: Id1e58797206a61d241f48b057b304e05c9c323d9
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84784
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add wifi PCIe hosts M.2 E-key WLAN to fulfill
drawman_jsl_schematic_20200528.
BUG=None
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: If414ff1941d2d70c5f0444ac58b228ed5c95303a
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Add a new Rauru follower 'Navi'.
BUG=b:341210522
TEST=emerge-cherry coreboot
Change-Id: Ia2a6c1c09b3cedc0ef7f51ec93fdabf2c07c8885
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84694
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
NAU8318 supports beep function via GPIO control. Configure the
GPIO pins and pass them to the payload.
BUG=b:343143718
TEST=Verify beep function through CLI in depthcharge successfully.
We can test with:
firmware-shell: badusbbeep
firmware-shell: devbeep
Change-Id: I79277bc1947dab517dea5aba583c5b4e0ac81bc4
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84693
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is no powering-on control in the fingerprint kernel driver. The
fingerprint team of ChromeOS suggests powering-on FP MCU in the FW.
Follow trogdor to pull down FP_RST_1V8_S3_L, AP_FP_FW_UP_STRAP,
EN_PWR_FP and pull up EN_PWR_FP in ramstage for power rail to be stable.
BUG=b:340401582
TEST=measure waveform and the fingerprint works on ChromeOS
Change-Id: I05600d90fdf922faeb778a36d8a08f68c1bb4125
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84692
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Configure GPIO EINT28 (XHCI_INIT_DONE) as output, so that payloads
(for example depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:317009620
TEST=emerge-rauru coreboot
Change-Id: I5950974435b56997626886b16d371cd8e6472e3c
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84691
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
FW_CONFIG ids
Based on Gallida360 design, we add two new options for WIFI_SAR_ID:
- WIFI_SAR_ID_INTEL_CONVERTIBLE 2
- WIFI_SAR_ID_INTEL_CLAMSHELL 3
BUG=b:372354703
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I1b58c4f572d4dbcb269d38485664ddc51e378e5e
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84779
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Create the francka variant of the fatcat reference board.
BUG=b:370666276
TEST=util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_FRANCKA
Change-Id: I372f445f7007d0d33020545a8febbce27c260e41
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84769
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the GPIO pad configuration to be performed before memory is set up
along with the relevant devices definition.
This patch includes:
- FW config for pre-mem GPIO PAD configuration
- Add overridetree changes used by pre-mem FW config
BUG=b:348678529
TEST=Boot on Google Fatcat board. Note this cannot be tested by itself
directly. Test with CL:84408, set the proper CBI fw_config bit(s) and
check that the corresponding GPIO PADs are configured as expected value
accordingly.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84718
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
|
|
Create the telith variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=372506691
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TELITH
Change-Id: I4971b9691d3dd293ca640795967c36472afef9c9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84759
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Add support for Arm Neoverse N2 Reference design.
Based on Arm Neoverse N2 reference design
Revision: Release D
TEST=Build Arm Neoverse N2 & make sure there is no error.
Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
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Add the BMC and all PCIe slots that the board implements.
There are 32 RSSDs and 2 M.2 slots.
Change-Id: Id7d72990d6997d1e8b9ce75477ce3dc571c99839
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
1. Add STYLUS fw_config setting.
2. Enable stylus device settings.
3. Disable the stylus GPIO pins based on fw_config.
BUG=b:364798563
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot
2. Confirm command evtest for stylus PRP0001:00 and workable.
Change-Id: Ifa8555eed1c31e9342a50a735fc618106f26d41a
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84713
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
nullptr was introduced in C11 spec and gcc 4.7.
https://en.cppreference.com/w/cpp/language/nullptr
https://stackoverflow.com/questions/16256586/how-to-enable-c11-on-later-versions-of-gcc
coreboot switched to GCC 4.7.2 on October 25, 2021, prior to coreboot v4.1.
https://review.coreboot.org/c/coreboot/+/1609
GCC-13 implemented nullptr constant: https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3042.htm
So use it insted of NULL macro.
Change-Id: I7d47e692a33d739345a81f589d4329a31beeb8c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83860
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
After CB:76315, TPM_RDRESP_NEED_DELAY, whose historical mission has
ended, could be removed.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I51e046fb738d2ff7a23225739de62a1a7780bc1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
|
|
In order to fit the specification, change gpio setting for touch panel
and wwan.
Change items:
1. wwan : Add WWAN_RST_L to 0. And we want WWAN_EN to pull high more
early than WWAN_RST_L, so add WWAN_EN to 1 in romstage stage.
2. touch panel : First we add EN_PP3300_TCHSCR and USI_RST_L to 0 to
init status. And we want EN_PP3300_TCHSCR to pull high more early than
USI_RST_L so delete USI_RST_L pull high in romstage.
BUG=b:357764679
Test=emerge-nissa coreboot
Change-Id: I0a07ea8e2bf3d165dcebd89c4c564f157d9d4846
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84668
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Reduce gspi speed from 10 MHz to 9 MHz, because Raptor
Lake Refresh platform GSPI supports max frequency 9 MHz.
BUG=b:342932183
TEST=emerge-brox coreboot
Change-Id: If5b7885d95cfe21ec71cc37e6d72419935b0844f
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84708
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Setting devices to unprovisioned allows us to perform
functional testing without having to rewrite the fw config
during the SMT phase of factory production.
BUG=None
TEST=Build lotso firmware and boot to OS when fw_config is
unprovisioned and ensure all devices are enable.
Change-Id: I3b8285ce335ee0f3595d184eb0921f697bdbd0c2
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84714
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Rather than hardcoded values, simply change these to -25% of the
defaults for Power Saving, and +25% for Performance.
Change-Id: I16aeb4d5dc25a3f240a775509276c9d3189e9699
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84661
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The Windows driver only checks PCI0, so move the window accordingly
so that it can be used.
Tested on `starlite_adl` by booting Windows 11 installation medium.
Prior to this patch, it would flag that the security requirements
were not met - it now happily installs.
Change-Id: I5d0d062502af99104690f9a9affec09f42b5bc71
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84663
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
This pin is used by the DisplayPort connector for Hot Plug.
Change-Id: I3c63e2e3e168a915daee81afd6a9084a3f01b986
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84662
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Override the PL4 to the maximum power the battery can provide
without a charger connected to prevent drawing too much power.
Change-Id: I2945e1ed0f33ab6692631e327c1457980b353c06
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84660
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The wrong definition was used, so the code had no effect.
The ID for the processor used is `b06e0`.
Change-Id: I36e13074a77b93871c1d86664e35a33afe39a402
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84659
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Some boards use hubs for devices, so correct the ACPI configuration
for these ports. Also, add more information to the comments for the
ports.
Change-Id: I8472130aba8e777557cf68280fa0058dbeb77df9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Change-Id: I6fb228bab06b050ac1a51de46ffe5c0d3d80adfb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Make the I2C speed user configurable from CMOS. Both the touchscreen
and accelerometer support running at 100MHz or 400MHz. They perform
better at 400MHz but use more power - this patch lets the user choose.
Change-Id: Ia1b08d7ec6212418bb95d0a52077f01c930f8830
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Change-Id: Ibe47f242ce12fc4906baeee89393a34a56eaca76
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83881
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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None of these boards support or use S0ix so c6dram isn't needed, so
disable it.
Change-Id: I8124899a1f7ce20442f28919f7315ee7e52355e5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84632
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is only 1 Type-C port, the rest are Type-A.
Tested on Linux by verified the correct names are shown in dmesg.
Change-Id: Iaf5a29f3d25f299658116fa61ae488775e2b70a2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84642
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Port 2 is a hub, used for the internal keyboard and the card reader.
Adjust this to a hub.
Change-Id: I3a9b9e6803934291b46fb502ff1b3b088c047703
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
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Change-Id: I8ea01c21ec03c11e9599684dbe51d103c07c172a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84640
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The existing GPIO configuration was IRQ heavy; tweak this to reduce
the number of interrupts.
Change-Id: I6d23bea5ec12e86a3606186edb29636540283fa3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84639
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A debug configuration was left in the patch when it was uploaded,
remove this.
Change-Id: I3ab8137d3841dfa200750a97969af5dca477d7e2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
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The wireless GPIOs don't need to be configured in the bootblock,
so set them up in ramstage.
Change-Id: Iab399884edde29891e66ffc097cf6f3dff71c351
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84637
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add options to disable the card reader and fingerprint reader.
Change-Id: Iee985aa2db3da5c2d393b8dc2dc722e990c43272
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84631
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1.Add WFC fw_config setting.
2.Used USB2 Port7 for WFC.
BUG=b:365184481
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ie5dcf5ed8f72a4bdf4c2c7fc63bf94dc7b869eef
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84685
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change updates the EC event parameters for Ovis, a Chromebox.
As a result, several existing parameters like LID, battery, and AC
connect/disconnect are no longer applicable to the Chromebox design.
TEST=Successfully built and booted google/ovis.
Change-Id: I2b9a6970a07624e16b4483907b8d2b77c04d535c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84671
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 8cfe1b3302ff (mb/google/brox/jubilant: Modify FP IRQ pin to GPP_D13): CB:84124, changes the fingerprint IRQ pin from GPP_F15 to GPP_D13, but forgot to update the pin in the array fp_disable_pads.
Hence update fp_disable_pads configuration to include that GPIO.
BUG=None
TEST= build firmware
$ emerge-brox coreboot
Change-Id: Iee4c3d3f000f884ca8a77ae8c72ccbeebfeb865f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84545
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
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These aren't used so remove them.
Change-Id: I0e8ef5e3c992f8ff51e4755b80379acfe0361e99
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84630
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per commit 865173153760 ("sconfig: Move config_of_soc from device.h
to static.h"), sources that require access to the devicetree should
directly include static.h so that it can be removed from device.h,
eliminating unnecessary dependencies on static.h for files that only
need the types and function declarations in device.h.
Change-Id: Ia793666fda47678764fd33891fddb4aecf207bd4
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch adds "fatcatnuvo" and "fatcatite" boards to the fatcat
Kconfig.
BUG=b:369728249
TEST=Able to build fatcat/fatcatnuvo/fatcatite and verify the correct
configs selected in coreboot.config
Change-Id: Ice3f1d711426cb356c399de6390fef6f0e6bc748
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84648
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1.Add AUDIO fw_config setting.
2.Add audio codec ALC5650 related settings for Gallida360 project.
BUG=b:364798053
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I3761ca6d4cad18c74f5e1a056f0cb465dc4ac3ea
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The new names include the `AUDIO_` prefix to clearly indicate that
they are audio-related options.
TEST=Able to build google/fatcat w/o any functional impact.
Change-Id: Ia651c19f02423ee214a31168e2bd809e097ce8c2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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use TOUCHSCREEN_THC_I2C instead of TOUCHSCREEN_THC0_I2C
BUG=b:348678529
TEST=Able to build google/fatcat
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I689dd72a925c76ca6c2c9a941f4857daae20c943
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84652
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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BUG=b:348678529
TEST=Boot google fatcat board till FSP memory training
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d52
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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BUG=b:348678529
TEST=Able to build google/fatcat.
Change-Id: I4061b9b4c1e515e8c078c67f30f29eee87b84a66
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84645
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Add FP enable/disable based on SKU ID for Dratini. This is meant
to resolve a UMA issue with Dratini devices that had the FPMCU
populated on non-fp devices. Since the FPMCU is present, and the
firmware enables the power GPIO's based on variant, not SKU, the
devices were reporting data on fingerprint errantly.
BUG=b:354769653
BUG=b:200825114
TEST=Flash to Dratini, test FP.
Disable test SKU, flash on Dratini, test FP.
To test, run `ectool --name=cros_fp version` in the shell
When enabled, the fpmcu fw version should be displayed.
When disabled, an error should be displayed because the fpmcu
is inaccessible.
Change-Id: Ifc450f51b00b9c3b62268ce94884f5749a3e18c0
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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This isn't required by these boards as they both use PTT.
Change-Id: I66b3f614914e51116f3cabe457205fb6b3528387
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84629
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on 24.04, disabling Turbo Boost increases power consumption
which doesn't align with the aim of the Power Saver profile.
Change-Id: I19e8189ee6c44d19bf222c921429284ed1e1aa2a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84628
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I68b285ff098127b7becf4aa8736e66fd6b2c4a32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: Ibb92d76f15be71ecb1e2187c7e235235585f8793
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I5beda22208fe17338d4136f9d38fd50e55054b01
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I140d597750001ad22e2bb1b6971011d2b3bb2bbc
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84272
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Tested on Ubuntu 24.04 by verifying dmesg output and that USB
2.0 and 3.0 devices are registered correctly.
Change-Id: I803a23007f49ea45abc68421e867535081e31b3f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84271
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPTF is not used on this platform so disable the
PCI device.
Change-Id: I763ab948a79e3a020c1b89c69c714dd0d8f54812
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84270
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These aren't used so remove them.
Change-Id: I6fd33c5242adb93b1251af9c5b11be3734a7aceb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I6bab0a316ea7d0f7dfbf599e5c08517cee559635
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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MAINBOARD_HAS_TPM2 should only be selected for the boards
that have memory mapped TPMs. The ones that use Intel PTT
don't need it.
Change-Id: I02b5b0912afbd7c4634c208bb17db16d0ac7ba99
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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DPTF is not used on this platform so disable the
PCI device.
Change-Id: I7fa01936568108dd7707a3c2ea7041a1198533b5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84266
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These aren't used so remove them.
Change-Id: I6b9cf29843047bff9a37f82b899ff1d10b206888
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 24.04
No known issues.
https://starlabs.systems/pages/starfighter-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I046e70845a5201d6f6ab062aee91fa8be9728737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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- This patch update the original google/fatcat support added
with Meteor Lake support as a workaround.
- Add initial support to build google/fatcat for Panther Lake SOC
- Add soc acpi file entry in mainboard dsdt.asl
BUG=b:348678529
TEST=Build google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I063062d875be61875da136228db06a39bc434833
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The LTE module RW101R-GL provide a hardware pin to enable/disable
WWAN RF function.The function is disabled in default and is
controlled by the AT command.Therefore,set the WWAN_RF_DISABLE
Pin to NC, and it has been pull-high by hardware desgin.
BUG=b:368450447
BRANCH=None
TEST= Build firmware and verify the WWAN on/off function in OS.
Change-Id: I47a28342f67f99c5787077c48a01ddbaa77b5967
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
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The platform uses eSPI so these are not needed.
Change-Id: I507aa59fcf2540ae6170896a51aa952f5e73eee8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83691
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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