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2022-02-28mb/amd/chausie/Kconfig: Add EC FW to RO_REGION_ONLYFred Reitberger
Include chausie EC and EFS only in the RO region when building with vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B regions. Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28mb/google/brya/var/kano: add enable_off_delay_ms to 30David Wu
Kano changes load switch of touch screen to TPS22914C (is not with discharge) on DVT board, EE suggests to add enable_off_delay_ms to 30ms to fix DUT can't enter S0ix issue. BUG=b:220811619 TEST=Boot kano to OS and run S0iX test 2500 cycles. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I7ea5693d457c5f60246348d2d8fa1f4130b7d4c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2022-02-28mb/google/skyrim: Enable PCIe devices in devicetreeJon Murphy
BUG=b:214414301 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I6b12950843f3ee3b5abe4ef9c6bd5aba528cc4ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/62164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28mb/google/skyrim: Enable AP <-> D2 communicationJon Murphy
Configure D2 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for D2 device and enable the required config items. BUG=b:214414776 TEST=Build Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I57b6d0e9da9935596e54b8eab400440e518b4523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28mb/google/skyrim: Add eSPI configurationJon Murphy
BUG=b:214413613 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If1177dda705738222ce7f6f42dceafb14d37c98c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28mb/google/skyrim: Add initial fch irq routingJon Murphy
BUG=b:214417045 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I6de1e4877323e18ec9d95f182c7d3fccd51d4998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28mb/google/skyrim: Add initial I2C configurationJon Murphy
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. BUG=b:214414677 TEST=Build Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I06e564cf6eca844101d70ff865f3074b45a55d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28mb/google/skyrim: Log mainboard events to elogJon Murphy
BUG=b:214414851 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic427f88fee7739b064a8836e07841c80c99212a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28mb/google/skyrim: Add ACPI configuration for USB portsJon Murphy
The USB port configuration was derived from the PPR and schematics. This board has 6(some multi-purpose) ports. Primary functions are: 2 USB-C ports 1 USB SS+ type A port 2 Cameras 1 Bluetooth transceiver BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28mb/google/brya/var/kano: Add wifi sar tableDavid Wu
1. Add wifi sar table for kano 2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG BUG=b:214393458 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Icddd583e5ee31e08b615df6fb2f4ceeb7f0c8131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-02-28mb/google/dedede/var/pirika: Add Wifi SAR for pasaraFrank Chu
Add wifi sar for pasara BUG=b:216411442 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ida475307c8448c5c2758c289da7708484bcb89e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26mb/google/skyrim: Enable USB controllers in devicetreeJon Murphy
BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable internal graphicsJon Murphy
BUG=b:214416935 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-26mb/google/skyrim: Enable console UARTJon Murphy
BUG=b:214414501 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26mb/google/skyrim: Set up FW_CONFIGJon Murphy
BUG=b:214415048 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ida8d226f84726f2eb03b07618907b0ce3928bec5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62146 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable eSPI SCI eventsJon Murphy
Enable ESPI SCI events BUG=b:214416630 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If47ba561f140eb474cad30e24b0a7c85cdd76203 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62149 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Add smihandlerJon Murphy
BUG=b:214415408 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable Chrome ECJon Murphy
BUG=b:214413613 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable variants for SkyrimJon Murphy
BUG=b:214414033 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I034ab8a06842bee12060103b4a1bc4e3db69e42a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26mb/google/skyrim: CONFIG_CHROMEOSJon Murphy
BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I045f76c366a1a72814536a2be984b7ad5a438a5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62043 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable ACPI tablesJon Murphy
Add GPIO initialization and ACPI generation for tables BUG=b:214415303 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/google/brask: Update PCH power cycle related durationsZhuohao Lee
The power rails discharge time of brask has been measured, the longest discharge time of the power rails are smaller than 150ms so it is safe to set the pwr_cyc_dur to 1 second. Since the brask is derived from the brya, we could apply the same setting from the brya. The setting is copied from commit dee834aa. BUG=b:214454454 BRANCH=firmware-brya-14505.B TEST=`test_that firmware_ECPowerButton` passed. Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25mb, soc: change mainboard_memory_init_params prototypeZhuohao Lee
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the input which make the board has no chance to modify data in the FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on its requirement. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25mb/intel/adlrvp: Add support for MAX98373 codecUsha P
- Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-25cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic numberFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25arch/x86: consolidate HPET base address definitionsFelix Held
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/google/guybrush: enable coreboot to request spl fuseJason Glenesk
Enable guybrush based platforms to send fuse spl command to PSP when required. BUG=b:180701885 TEST=On a platform that supports SPL fusing. Confirm that PSP indicates fusing is required, and confirm coreboot sends command. Fusing is required when the image is built with an SPL table requiring newer minimum versions. A message indicating fusing was requested will appear in the serial log. "PSP: Fuse SPL requested" Change-Id: I7bce01513af4e613f546e491d9577c92f50cb85c Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-02-25mb/google/volteer/var/collis: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:192535692 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I30fa886a39bd7082442a3a2b95fdf2d2b84ddd1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-25herobrine: Add Villager variantShelley Chen
BUG=b:218415722 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_VILLAGER -x -a -B Change-Id: I84935ea280023cb0df1dd51fcd2a83d80db17710 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-25mb/google/skyrim: First pass GPIO configuriation for SkyrimJon Murphy
BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I60b3b3cd50eea1253df2ae3e0aea83bb89e54702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62042 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/amd/chausie/devicetree: add i2c_scl_resetFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23ec6bcb6a2b3627866165972fd6ba1c75367533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62188 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/amd/chausie/devicetree: enable I2C controllersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f37c45ffe945e6bb071c8205343943edc524ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61871 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24mb/google/brya/var/taeko: Add GL9750 SD card reader supportKevin Chang
Add GL9750 SD card reader support. BUG=b:220987566 TEST=Build FW and check device function normally. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I8f6ca45a320d34dfd820ef0b6e0d3163fab26027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24mb/google/skyrim: Add stubs to configure GPIOsJon Murphy
BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ieeda9aa0c18b5befea67d2849bd4114da0c348a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62041 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24mb/google/brya: Add SPD configs for CrotaTerry Chen
Add a mem_parts_used.txt for Crota, containing the memory parts used in proto builds. Generate Makefile.inc and dram_id.generated.txt using part_id_gen. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 1 (0001) H9JCNNNCP3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 2 (0010) BUG=b:215443524 TEST=emerge-brya coreboot Change-Id: I0ff6ffea4b879b6e1287e1e3cb9fd36a80f52ed6 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-24mb/google/brya/var/vell: Corrects ACPI _PLD macro settingRobert Chen
This patch is to denote the correct side of ACPI _PLD usb C ports. +-------------------------+ | LCD | | | | | +-------------------------+ PORT_C2 | | PORT_C1 PORT_C3 | DB MB | PORT_C0 | | +-------------------------+ BUG=b:220634230 TEST=emerge-brya coreboot Change-Id: I84515f98b6cdab5768df75690b0f5ca1bb9ad96d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24mb/google/brya/var/anahera{4es}: Add MT53E2G32D4NQ-046 WT:C supportWisley Chen
Add new memory MT53E2G32D4NQ-046 WT:C support BUG=b:220821471 TEST=emerge-brya coreboot Change-Id: I4c21254213c2107d015adebb510612e0256ffb5c Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24mb/google/brya/var/redrix{4es}: Add MT53E2G32D4NQ-046 WT:CWisley Chen
Add new memory MT53E2G32D4NQ-046 WT:C support. BUG=b:220804962 TEST=emerge-brya coreboot Change-Id: I3353d7c119798ebb0b5ee1ea32161e54b4eec826 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-22mb/gizmosphere/gizmo/OptionsIds.h: Remove extra empty lineElyes Haouas
Change-Id: I8ad968da1771004f7f5869e5434473a498edeaa2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22mb/lenovo/g505s/acpi/ec.asl: Correct the path to "mainboard.h"Elyes Haouas
Change-Id: I273e29a26cf1c1ba34b95eb11bcb59a1360371e1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22mb/lenovo/g505s: Format codeElyes Haouas
Change-Id: I9cce00e1634d62a63b3563d54a7a0c56058d0e39 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22mb/gizmosphere/gizmo/acpi/gpe.asl: Remove extra blank lineElyes Haouas
Change-Id: I0d9b07183b06915799f221390406e930ca253a0d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22mb/gizmosphere/gizmo/devicetree.cb: Fix typo on 'pci'Elyes Haouas
While on it, use tab for indent. Change-Id: I6cb0b4183db819d721f4882ab2168d22bcd664e3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22mb/starlabs/labtop: Reconfigure GPIOsSean Rhodes
Reconfigure the GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I27ecf066685f2a81ac884a9f276c518544449443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Reconfigure CNVi GPIOsSean Rhodes
Reconfigure the CNVi GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Update trackpad GPIO configurationSean Rhodes
Update trackpad GPIO to avoid IRQ Storm, that causes high power consumption when idling or in S3. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ieee27bd9079617ab95f4f1e27ef98b49e89e5b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Configure TPM_IRQ GPIO for TGLSean Rhodes
Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the hardware TPM can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756 Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22mb/starlabs/labtop: Don't configure ESPI GPIOsSean Rhodes
Don't configure ESPI GPIOs as the default values are correct. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-22payloads/tianocore: Rework MakefileSean Rhodes
Rework edkii makefile so that the various build options are unified between CorebootPayloadPkg, uefipayload_202107 and upstream. This sets the project directory based on the git repository name i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit ID without a branch. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-22mb/siemens/mc_apl2: Enable PCI device for I2C bus 0Werner Zeh
On mc_apl2 the external RTC is connected to I2C bus 3. All other I2C bus devices (16.0, 16.1 and 16.2) have been disabled as they are not used. While coreboot can handle the case where a PCI device does not have function 0 enabled but a later one (here function 3), Linux seems to check for function 0 first and ignores the rest if function 0 is missing. So enable PCI device 16.0 in order to let Linux use 16.3 again. Test=Boot into Linux and make sure that PCI device 16.0 and 16.3 are visible and I2C attached RTC works properly. Change-Id: I55a748b6de8128f4b26b908118feff9f06d3fb7c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21mb/google/volteer/var/drobit: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:204517112 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic37e7e6757476f1d30bea31fcde4deebebd488a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21mb/google/volteer/var/delbin: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:204523176 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I36e35522aba2463124b7e6e7046b1a56758b534d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21mb/google/volteer/var/copano: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:218245715 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I30a1fe2ef8d750616f6907f86a5329f035920504 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUDZheng Bao
Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21mb/google/brya: Enable eMMC HS400 mode for nissaReka Norman
Based on the nivviks and nereid schematics, nissa is using eMMC HS400 mode, so enable this in devicetree. BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21mb/amd/chausie/chromeos.fmd: resize EC size in FMAP to 4kByteFelix Held
Only the info about the location of the EC firmware will be stored right at the beginning of the flash, so the size can be reduced to 4kByte which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE file itself is smaller than this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21mb/google/brya/variants/felwinter: Adjust I2Cs CLK to be around 400 kHzJohn Su
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for audio, TPM, touchscreen, and touchpad. Audio CLK: 385 kHz TPM CLK: 380.5 kHz Touch Screen CLK: 373.3 kHz Touch Pad CLK: 372.7 kHz BUG=b:218577918 BRANCH=master TEST=emerge-brya coreboot chromeos-bootimage measure by scope with felwinter. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I3e5cc10d6605f9cc41fa6b31da07a81364b72fe0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-21mb/amd/chausie/Kconfig: Move EC firmware image in CBFSFred Reitberger
Move the EC to a location that does not conflict with where the main CBFS is in the chromeos FMAP Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21mb/intel/adlrvp_n: Update devicetreeKrishna Prasad Bhat
Update devicetree according to schematics. TEST=Build and boot Alder Lake N RVP. Change-Id: I9faee1cb3539a0246fc6a87e15b3150533de1ee5 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-19mb/amd/chausie: increase RW_MRC_CACHE size in FMAPFelix Held
On Sabrina SoCs the size of the APOB has increased, so the size of the RW_MRC_CACHE FMAP sections needs to be increased in order for the data to still fit in the corresponding FMAP partition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya: remove the delay from for WWAN _ON method.Cliff Huang
Remove unecessary delay in RTD3 _ON Method after PERST# dessartion. TEST: 2022-02-10T18:22:53.204391Z INFO kernel: [ 0.190287] ACPI: Power Resource [RTD3] (on) 2022-02-10T18:22:53.204395Z INFO kernel: [ 0.194252] ACPI: Power Resource [RTD3] (off) Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I9bc36af6e6c944fcd3de23b7d49640ad9d25642d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-02-18mb/google/brya/redrix{4es}: Disable unused USB2/TCSS portsWisley Chen
Disable unused USB2/TCSS Ports. BUG=b:217238553 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I1cdee5b6dc56accb52ba1bf636bdf753a7bfd199 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18mb/google/brya/var/{redrix, redrix4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I61f8f39ce7651d499756f4975840f32f89b04ca7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18mb/google/brya/var/felwinter: Update DPTF parameters for FelwinterJohn Su
Follow thermal team design to remove TSR3 sensor and update thermal table for next build. The DPTF parameters were verified by thermal team. BUG=b:219690502 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I0e34fabe546b6eabb3d3adad583668a15a1d908b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18mb/google/brya/var/vell: Correct MIPI camera infoShon Wang
The CIO2 port was incorrectly set to 2, while the correct port is 1 BUG=b:210801553 TEST=Build and boot on vell, camera works correctly now Change-Id: I53d8448ed0e12777456af9b0bc65a04595b47e37 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61946 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/volmar: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1e0b51ee4db73bdff79365d4954a3245a430f140 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62051 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/vell: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e4837489d90c2edd7deaa2af0533085f1ff5ae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62049 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/taniks: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id44213c7dd4d0df97a6c57d7f1b9d950baaf0e1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62047 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{taeko, taeko4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie304b08b0b1bbad5547a0169ea8056d703141391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61830 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{primus, primus4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1a4bc1aae8e815b882a607432e40caf1066453b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61828 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/kano: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I07cef3b619991afb6337c38a631ee159677d30a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61826 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{gimble, gimble4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0274f03926d97fc543b98f3fb961580283202806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61825 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/felwinter: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I33e4501fd689d642682891c7f5bc9cb7ca5e331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61824 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{brya0, brya4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1940246fd88db29054f85c43672adc97dc90fa04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61823 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{anahera, anahera4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3d8a8a7e2b1e490726986139014cdfcf1271c64b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61805 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/agah: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idb8f30b2d1069aea1d5ce7c5dda7f99de33a7c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61803 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/volmar: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iddf0727a538f2063cfabbec1f900c488331f33c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/vell: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib0d1be34775c5eacf6cd9b0ec400bd42a93c59e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/taniks: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia9bc235c257abce2a3cd63cfd1b17ac356267d8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/taeko4es: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic3fbf307bfa42bd377c8f23c1837a6d15cb378e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/{redrix, redrix4es}: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I80d9038d1f41d65201d6bfdb808708f997d71faf Reviewed-on: https://review.coreboot.org/c/coreboot/+/62031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/{primus, primus4es}: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic97d48633ef1f246c181046ec32ab81614ba5ceb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18mb/google/brya/var/kano: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I78734f685672347b06783f834643347a35c59e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/{gimble, gimble4es}: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4e051b21ca55d25c6fc6cfb529078b18adaab2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62028 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{anahera, anahera4es}: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0c72a5c5306d63c5fce24bf727704d212d0ad0f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18mb/google/brya/var/agah: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9cef57bbaf3e3519b7f6a7e3d86979722b598ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17mb/google/guybrush: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSPJan Dabros
Guybrush platforms have I2C3 controller which is shared between PSP and X86. In order to enable cooperation, PSP acts as an arbitrator. Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is binded on the OS side. With this change in place it is important to use correct kernel version which has I2C-amdpsp driver [1] enabled. Otherwise, we won't have I2C3 available and thus TPM device available in OS, what may end up as a serious error - guybrush refuses to boot without access to TPM. BUG=b:204508404 BRANCH=guybrush TEST=Build proper kernel and firmware. Run on guybrush and verify TPM functionality. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I9dd94e47e1a02e790427b67adff84de3eb3ee387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61965 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17mb/amd/chausie: Add EC blob into CBFSFred Reitberger
Add chausie EC blob into CBFS at specified location Change-Id: I48de08a18054efbda655e1563a539ff2ba7a38a6 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-17mb/google/herobrine: Disable fingerprint sensor on CRD devicesRavi Kumar Bokka
Qualcomm CRD devices do not have a fingerprint sensor so removing the QUP configuration for it. This QUP also coincidentally is the same as the one used for the TPM, so this initially was also causing TPM communication issues during bootup as the QUP was being reconfigured during the later stages after QcLib execution. BUG=b:206581077 BRANCH=None TEST=Boot to kernel without any CR50 communication errors Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I8d13b67796b70b0b7e9a4721cca0b8a54b2b27c1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61716 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17mb/google/brya/var/vell: Add Wifi SAR for vellRobert Chen
Add wifi sar for vell BUG=b:218992598 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I74fddd1dbcb7019fd5fe394da291f125f0d4960f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-17mb/google/brya/var/vell: Correct the DQ mappingGaggery Tsai
This patch corrects the DQ mapping and enable ECT. In Vell design, the DQS is swapped in Mc0.ch1, Mc0.ch3, Mc1.ch0, Mc1.ch1 and Mc1.ch2 but the DQ mappings are not swapped and that causes ECT training failure. BUT=b:208719081 TEST=emerge-brya coreboot chromeos-bootimage && ensure the system passes ECT training and all the way booting to the OS. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Idd2ad16151f0b2b93b00295b75a66ba65cba23cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16mb/google/herobrine: Add Gigadevice SPI PartShelley Chen
BUG=b:182963902 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I73dc695afb7aa2b32aa966070eb057c828073d47 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16mb/google/herobrine: Alphabetize SPI_FLASH configsShelley Chen
BUG=b:182963902 BRANCH=None TEST=None Change-Id: Ia73460d335e859644511b7e9ca80111a919baf2c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16Use the fallthrough statement in switch loopsArthur Heymans
Clang does not seem to work with 'fall through' in comments. Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16mb/google/brya/var/agah: Select PCIEXP_SUPPORT_RESIZABLE_BARSTim Wawrzynczak
The google/agah variant will use a peripheral that will require the use of the PCIe Resizable BAR feature from the PCIe spec. Thus, select the new Kconfig option to enable it. The appropriate Resizable BAR size will be updated later. BUG=b:214443809 TEST=build Change-Id: I9cf86ba3160ae5018655b5d366e89f4273b30b94 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-16mb/google/brya/var/agah: Change ELAN touchpad driver for eKT3744Tony Huang
Change to use i2c/generic to match ELAN FW update script. BUG=b:210970640 TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ib416da6000d9e99f9c37cf497fb1c43e3fca0220 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16payloads/external: add skiboot (for QEMU/Power9)Sergii Dmytruk
Add an option to build skiboot as a payload. This makes QEMU Power9 board simpler to use as skiboot is necessary anyway. Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-16mb/google/brya: Update memory DQ mapEric Lai
Follow latest schematic to update the DQ map. BUG=b:218939997 TEST=boot into OS without issue. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If29cc22b1749fb5d602d3ce64bcc1182593d673f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-15mb/starlabs/labtop: Disconnect unused GPIO'sSean Rhodes
Disconnect all GPIO's that aren't connected to anything. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2050da62f73c0f99fbfef013c22e35225cc480c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-15mb/starlabs/labtop: Add comments for GPIOsSean Rhodes
Add comment for each GPIO details its endpoint based on the schematic. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia3678274dcd52285019fb3cf8ccd22617268ce1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 18:34:43 +0000