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2021-09-17mb/google/brya/primus: add NVMe power and reset pin to early_gpio_tableMalik_Hsu
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that primus can successfully boot into OS with non-serial coreboot. BUG=b:199967106 TEST=USE="project_primus" emerge-brya coreboot and verify it builds without error. Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I9c66efe96515347502d059556052c764c1be5d09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17mb/google/dedede/var/cappy2: Update DPTF parametersSunwei Li
Update DPTF parameters from internal thermal team. BUG=b:197546694 BRANCH=dedede TEST=emerge-keeby coreboot Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I71a76a4d94a704aef7b3cefa2fca3009eb765bb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57693 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-17mb/scaleway/tagada/bmcinfo: replace stdbool.h include with types.hFelix Held
Apart from the u8, u16 and u32 types, the bool type is used in this file so include types.h instead of stdint.h to have bool defined too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95f037deb0fe11b717586df655065bfbb33b0d23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17broadwell boards: Reflow USB2 parameter statementsAngel Pons
These statements fit on a single line. Reflow them to ease future works. Change-Id: Ie18e9a00f67b999fdcedcab3c28b68e34bc93da4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-17mb/google/brya/var/redrix: Enable USB4 PCIe resourcesWisley Chen
Enable USB4 PCIe resources for redrix BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I759618055b1282653d8a05fa66e8cdab0c43e3a6 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17mb/google/brya: Add WWAN poweroff sequenceEric Lai
Follow FIBOCOM_L850-GL Hardware User Manual_V1.0.8. BUG=b:180166408,b:187691798 TEST=measure WWAN power off by scope is meeting the spec. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I6b2725cd61d5b54bc7fd70a9daffd29e7b43690b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17mb/system76/gaze15: Correct CMOS type for debug_levelTim Crawford
When the century byte was reserved, the debug_level was accidentally converted from an enum to a hidden value. Change it back to an enum. Fixes: f05bd8830de ("mb/system76/*: cmos.layout: Reserve century byte") Change-Id: Id88a7aed7b2fc793fd003db5b45f3f201b1a7630 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-17skylake DDR4 boards: Set `CaVrefConfig` to 2Angel Pons
The `CaVrefConfig` FSP-M UPD describes how the on-die Vref generators are connected to the DRAM. With the exception of an early Skylake RVP board (which doesn't have coreboot support), mainboards using DDR3 or LPDDR3 memory should set `CaVrefConfig` to 0, whereas mainboards with DDR4 should set `CaVrefConfig` to 2. MRC uses this information during memory training, so it is important to use the correct value to avoid any issues, such as increased power usage, system instability or even boot failures. However, several Skylake DDR4 mainboards don't set `CaVrefConfig` to 2. Although they can boot successfully, it's not optimal. For boards that set `DIMM_SPD_SIZE` to 512 (DDR4 SPD size), set `CaVrefConfig` to 2. Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-16vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen
vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/guybrush: Reorganize bootblock_mainboard_early_init()Martin Roth
This now skips all of the pieces done by PSP_verstage. BUG=None TEST=Boot Guybrush with & without PSP_verstage Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5a6b8e2284e232c30c9f36ea7c6ab044e2644f7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16mb/google/guybrush: Initialize WWAN GPIOs the same for PCI vs USBMartin Roth
Since the PCIE training for the USB WWAN card is no longer being run, we can initialize the GPIOs the same for all WWAN cards. BUG=b:193036827 TEST=Boot and reboot with fibocom FM350-GL & L850GL modules Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idc9a7cb883fc8dd6bbc6077b8ea99182f17f888b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57317 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/guybrush: If not using PCIe WWAN, disable the portMartin Roth
Check to see if the PCIe slot needs to be activated for the WWAN card. If it doesn't, leave it unused so it will be powered off and not do the PCIe training. BUG=b:193036827 TEST=Boot & Reboot guybrush with both PCIe & USB WWAN cards. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I79c32e4814672c03ee0821786d5be1c77fd1b410 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16mb/google/brya/variants/gimble: Add fw_config probe for ALC5682-VD/ALC5682-VSMark Hsieh
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:200009010 TEST=ALC5682-VD/ALC5682-VS audio codec can work Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I09c7830fff6b318cf1a1f4a44ee0a819691f7c58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57673 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/brya/variants/kano: Add MIPI camera supportDavid Wu
Add MIPI camera support for OVTI2740 BUG=b:196937374 b:194926283 TEST=Build and boot on Kano Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I248c64b9460c898f9faa5f7ac8cf339a9c814013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16mb/google/brya/var/redrix: Add fw_config probe for eKT3764/eKT3644Wisley Chen
Report different ACPI device depending on TP_SOURCE field of fw config (SSFC-bit8~bit9) for elan touchpad. BUG=b:199503876 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I15781c2d942d81e11c296ea2f2586ba82f67e4a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16mb/google/brya/var/redrix: Select camera module based on SSFC valueArec Kao
This patch has changes to support multiple camera modules, base on the value set in the SSFC_CONFIG. BUG=b:198235323 TEST=tested the changes with redrix 5MP(ov5675/hi556) camera. Change-Id: I71c8355617171ec7d08862759b87d4bf12ce2924 Signed-off-by: Arec Kao <arec.kao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57272 Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/brya: Fix brya0 WWAN poweron sequencingTim Wawrzynczak
The PCIe WWAN module used on brya0 requires control over 4 signals to successfully power it on. It is desirable to do this before passing control to the payload, because the modem requires a ~10 seconds initialization phase before it can be used. The corrected sequence looks like: 1) Drive device into full reset and enable power in bootblock 2) Deassert FCPO in romstage, after power rails stabilize 3) Deassert WLAN_RST#, then WLAN_PERST# in ramstage BUG=b:187691798 Change-Id: I10f15a4dcfd86216c334fb24b4693ea250d35ee4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-16mb/google/brya: Update state of BB_RT_FORCE_PWR gpiosTim Wawrzynczak
This GPIO is used to force the USB retimers on Type-C ports to stay in a powered state and can be used e.g., during a firmware update to the retimer to force power on even when no device may be connected to the port. However, its power rail is controlled elsewhere and coreboot is not applying a FW update, so this GPIO should be driven low instead. BUG=b:193402306 TEST=compile Change-Id: I976a0b8252b31aacef476d5ee4bcf6b1ef2e79de Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-09-16mb/system76/darp7: Add System76 Darter Pro 7Tim Crawford
https://tech-docs.system76.com/models/darp7/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - M.2 SATA SSD - MicroSD card reader - All USB ports - USB-PD - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DP over USB-C output - Internal microphone - Internal speakers - Combined 3.5mm headphone/microphone jack - S0ix suspend* - Booting to Ubuntu Linux 21.04 and Windows 10 - Flashing with flashrom Not working: - S0ix when a device is attached to the TBT port Not tested: - Thunderbolt functionality Change-Id: I80e5c5375f9d3881fc89a45a91ba68ed2e104a93 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52349 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mainboard/google: Update the TLMM registers for sdhcShaik Sajida Bhanu
Update the TLMM register values for eMMC and SD card on Trogdor, Herobrine and Mistral boards. BUG=b:196936525 TEST=Validated on qualcomm sc7280 and sc7180 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/trogdor: Add mipi panel for wormdinglerZanxi Chen
Add mipi panel support for wormdingler - Add the following panel for wormdingler: INX P110ZZD-DF0 BOE TV110C9M-LL0 - Use panel_id to distinguish which mipi panel to use. - Setup panel orientation BUG=b:195898400,b:198548221 BRANCH=none TEST=emerge-strongbad coreboot Change-Id: I8cd28e024ecbfdcd473bc39efb529eb4aca1b5d0 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-16mb/google/dedede/var/magolor: Generate SPD ID for supported partsTyler Wang
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 BUG=b:199032134 TEST=emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: If8b75f9ed4d789d6c9c4365c517358df8d6e55c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-16mb/google/dedede/var/cappy2: Enable PIXA touchpadSunwei Li
Add PIXA touchpad into devicetree for cappy2. BUG=b:193099842 BRANCH=dedede TEST=built cappy2 firmware and verified touchpad function Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I840a3ffbaaaac39eaf13bf77e203f6dffdddd3f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16mb/google/dedede/var/cappy2: Add USB2 PHY parametersSunwei Li
This change adds fine-tuned USB2 PHY parameters for cappy2. BUG=b:199485217 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I2aac29e8bba0bf3eff91898ded7561b6211af789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16mb/google/dedede/var/cappy2: Configure I2C times for tp & codecSunwei Li
Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: touchpad:390kHz codec:395.8kHz BUG=b:199481261 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ifadc3d19eb57fe6f67504be154c30df7bc0fee71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16mb/google: Unify all variants to start with "-> "Martin Roth
All variants originally had been changed to start with an arrow with two spaces following it to line up with the platform name. A number of recent platforms were added only using a single space. This change updates them all to have two spaces so they line up again. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iab9e6207fff5a7d2f6d76e5ca33eeaca721a224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-16soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_TCSS at SoC levelSubrata Banik
This patch selects SOC_INTEL_COMMON_BLOCK_TCSS from Alder Lake SoC Kconfig and drops SOC_INTEL_COMMON_BLOCK_TCSS Kconfig selection from specific mainboard (brya) to ensure all Alder Lake mainboards can make use of common TCSS block. BUG=b:187385592 TEST=Type-C pendrive/Gen-2 SSD detected as Super speed. Change-Id: I85f6a967eb34ea760418131a9586bfdeb13c9b5d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-16mb/intel/adlrvp: Override Type-C IOM GPIO Pads based on Board IDSubrata Banik
This patch allows ADL-RVP mainboards to set AUX GPIO PADs based on the board id value. Various ADL-P and ADL-M RVPs SKUs demand different GPIO AUX programming hence, this patch implements a helper function inside `adlrvp` mainboard to override devicetree chip config. Note: Different ADL-P/M SKUs (LP4/LP5/DDR4/DDR5) don't have dedicated devicetree for overrides hence, board id is being used for unique SKU identification. Additionally, skip AUX GPIO PAD filling up for Windows SKUs. TEST=Able to override AUX GPIO PADs based on ADL-P RVP board id. Change-Id: I2f0a37c7a8bd69af715551df2a93e6eed89e954a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16soc/qualcomm/common/qup: Add support for QUP common driverRavi Kumar Bokka
copy existing QUP driver from /soc/qualcomm/sc7180 to common folder. This QUP common driver provide QUP configurations, GPI and SE firmware loading and initializations. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I95a0fcf97b3b3a6ed26e62b3084feb4a2369cdc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16mb/google/herobrine: Increase the ROM size to 64 MBShaik Sajida Bhanu
SPI NOR size should match with coreboot ROM size. On QCOM Piglin board SPI NOR size is 64MB and the default coreboot ROM size is 8MB. So, update the coreboot ROM size to match with SPI NOR size. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board and checked basic boot up. Change-Id: I78f3f402b383bbad303f26c31d3d973c5f20d172 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16mb/google/dedede: Override panel orientation for buggzyTim Wawrzynczak
Buggzy's panel is oriented with its "right" side facing upwards, therefore the firmware screens in depthcharge were incorrectly rotated. This patch changes the orientation of the framebuffer provided by the FSP. BUG=b:194967458 BRANCH=dedede Change-Id: I4a5fbfcfc1c362da1bddd23c7d132416db3691c9 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16mb/google/brya/var/redrix: Add privacy screenWisley Chen
Add privacy screen support. BUG=b:198188272 TEST=build and check SSDT Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ied9d9138f68ba45c4d746aed1cd3f828d4ab7fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/57289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-15google/trogdor: Fix Mrbland panels to point LEFT_UPJulius Werner
CB:57324 moved panel orientation from panel_serializable_data to the responsibility of the mainboard, but in parallel to that patch we landed support for some new panels on the Trogdor mainboard that should be pointing LEFT_UP. This patch fixes up the panel orientation for those. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I416b6c8804a88b36f723c4690ed78aff928a0f8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2021-09-15mb/google/brya/variants/gimble: update fw_config for next build phaseMark Hsieh
Update audio FW config based on the schematic carbine_adl-p_evt_20210901.pdf BUG=b:199180746 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4f8ee1a97dd92c7aa0131cd0a77b05f851a26b05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57529 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15mb/google/brya/var/felwinter: Add R4/R5 for dmicEric Lai
Based on latest schematic (0903) update the GPIO table. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie79ba14859f7fa4ea66a0f0d58287f4515d01baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/57636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-15mb/system76/galp5: Add System76 Galago Pro 5Tim Crawford
https://tech-docs.system76.com/models/galp5/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - Internal microphone - Internal speakers - Combined 3.5mm headphone/microphone jack - S0ix suspend* - Booting to Pop!_OS Linux 21.04 and Windows 10 - Flashing with flashrom Not working: - Discrete/Hybrid graphics - S0ix when a device is attached to the TBT port Change-Id: I0d9052c0b064d4d43812ad837578d4a097149cc8 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15mb/system76/lemp10: Add System76 Lemur Pro 10Tim Crawford
https://tech-docs.system76.com/models/lemp10/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - DIMM slot and onboard RAM - Both M.2 NVMe SSDs - MicroSD card reader - All USB ports - USB-PD - Webcam - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DP over USB-C output - Internal microphone - Internal speakers - Combined 3.5mm headphone/microphone jack - S0ix suspend* - Booting to Pop!_OS Linux 21.04 and Windows 10 - Flashing with flashrom Not working: - S0ix when a device is attached to the TBT port Change-Id: I15f7a3b6e9af07fcfde9a71d3f4a84ed625159b7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15mb/google/brya: Add support for romstage GPIO tableTim Wawrzynczak
Some variants may require more complex power sequencing than can be accomodated with just 2 GPIO tables, therefore introduce one in romstage as well. BUG=b:187691798 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7a63a2ee2cd036b9ae5822be9c87d8a026a54922 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-15mb/google/brya: Enable USB4 PCIe resources for kanoDavid Wu
Enable USB4 PCIe resources for kano BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iec914db6914116ebc914a2ba9ff67344b202926b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-15brya/gimble: add `get_wifi_sar_cbfs_filename()` in variant.cMark Hsieh
gimble only uses one WiFi SAR table, contained in a file named wifi_sar_0.hex BUG=b:189068477 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ied030b79183cc6f962674260e7a82a7261b317ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/57616 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15google/trogdor: add new variant kingoftownKevin Chiu
This patch adds a new variant called kingoftown. it's clamshell only, no FPR, eDP panel. BUG=b:198365759 BRANCH=master TEST=make Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I648664c50dfad11530a854f574f39264158b44e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-14mb/intel/adlrvp_p: Enable TCSS USB ports device pathMeera Ravindranath
TEST=Boot RVP, ensure Type C ports operate correctly. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: Iadc0df2e6e29a5afbcbb7db1ae0be6546dbcdc1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-09-14mb/up/squared: Undo set primary GPU via FSP optionMaxim Polyakov
This is no longer needed, since now this parameter is already set using the ONBOARD_VGA_IS_PRIMARY config [1]. [1] commit 1a4496e79f21bef12efc8c6748264a8770266a27 Change-Id: I368fa5d13615dc4ee37db596cb6a5eef993fc220 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-14kontron/mal10: Undo set primary GPU via FSP optionMaxim Polyakov
This is no longer needed, since now this parameter is already set using the ONBOARD_VGA_IS_PRIMARY config [1]. [1] commit 1a4496e79f21bef12efc8c6748264a8770266a27 Change-Id: Ie1bd62ecba2155af5c94f043ea7531f32989588f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-13mb/google/trogdor: Add PANEL_ID to SKU_IDZanxi Chen
In order to distinguish which mipi panel to use, it need to read the PANEL_ID, and combine the PANEL_ID and SKU_ID into a new SKU_ID. BUG=b:197708579,b:191574572,b:198548221 TEST=PANEL_ID should be set correctly. BRANCH=none Change-Id: I018b3f460f9d084d1a3f0dac026f1cd9dde284e2 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-13mb/intel/tglrvp: Enable USB4 resources using SoC KconfigFurquan Shaikh
This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES` Kconfig to enable USB4 resources and drops the configuration in mainboard. Change-Id: I707c5d63ea8c58e72126fe0d319ba81a99221ba5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-13mb/google/volteer: Enable USB4 resources using SoC KconfigFurquan Shaikh
This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES` Kconfig to enable USB4 resources and drops the configuration in mainboard. Change-Id: Id0951937cab8bf5432fc902ba7af21f56fe98087 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-13mb/adlrvp: Add new ADL P board variant for MCHP1727Brandon Breitenstein
Add new board variant to enable MCHP1727 Modular EC Card on RVP BUG=b:179214042 BRANCH=none TEST=emerge brya and verify that adlrvp_p_mchp images boot Change-Id: I9dc96ad5c5db21fedbe480d19fcae8434d3bd169 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56839 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13mb/google/dedede/var/bugzzy: Generate SPD ID for K4U6E3S4AA-MGCRSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. K4U6E3S4AA-MGCR (Samsung) BUG=b:192521391 BRANCH=dedede TEST=Build and boot bugzzy board Change-Id: Ic0b02559c671845a73a71bd57cd7237850c76645 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13mb/prodrive/hermes: Hook up P2SB and PMC in devicetreePatrick Rudolph
Fixes commit bd5b4aa683a634a73a6a63d1f197e2bb74b6a80e "soc/intel/cannonlake: Switch PMC to use device callbacks" as it requires the PCI device 1f.2 to be present in the devicetree. It was missing for this mainboard and caused a boot failure. Change-Id: Iaf508b2d955578efa2a266af50c568f5c0a47aaf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-09-11mb/google/brya: Replace white space with tabSubrata Banik
This patch unifies line indentation. Change-Id: Ieeb580057d8abb20afe3a5d73f5f835e6d31c899 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-11mb/google/asurada: fine tune the data lane trail for ANX7625Hung-Te Lin
The ANX7625 display bridge requires customized hs_da_trail time. This patch is based on CB:51433 (commit 6482b16, "mb/google/kukui: fine tune the data lane trail") BUG=b:198558237 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Hung-Te Lin <hungte@chromium.org> Change-Id: I0eedb8fa6a1b3dfd9619c7cbf755c9c4071a8484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-09-11mb/google/trogdor: Add mipi panel for mrblandZanxi Chen
Add mipi panel support for mrbland - Setup gpio and modify LCD sequence. - Use the following panel for mrbland: AUO B101UAN08.3 BOE TV101WUM-N53 - Use panel_id to distinguish which mipi panel to use. BUG=b:195516474,b:197300875,b:197300876 BRANCH=none TEST=emerge-strongbad coreboot Change-Id: Ib7cd2da429b114bf6bad5af312044a0f01319b46 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57336 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10mb/google/guybrush: Invert USB descriptions in devicetreeRob Barnes
The USB descriptions are flipped. Fix by inverting the USB descriptions in devicetree. BUG=None TEST=Build BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I4b33f4de137536c5f3592380da15f6b3a3633bf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57538 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10mb/google/guybrush: Document USB mapping in devicetreeRob Barnes
Add a short documenting comment to each usb entry in devicetree so it is clear which function each usb port maps to. BUG=None TEST=Build BRANCH=None Change-Id: I14cbb6af021bb27c89aa82456722f21aa09617be Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56725 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10cannonlake mainboards: Set PMC as hidden in devicetreeTim Wawrzynczak
FSP-S hides the PMC from the PCI bus when it runs, but there are still initialization steps coreboot programs for the PMC. Therefore, change all of the cannonlake mainboards to set the PMC as hidden in the devicetree, which means the device will be skipped during enumeration, but device callbacks are still issued as if the device were enabled. TEST=Ran full patch train on google/dratini, disassembled SSDT and the PEPD device matches what is in pep.asl. Also verified via dmesg that the INT33A1 device is still initialized by the kernel. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-10mb/google/asurada: enable MIPI_DSI_MODE_LINE_END to fix display issuesHung-Te Lin
The ANX7625 needs explicit LINE_END to output proper display data. This patch is based on CB:51435 (commit b923931, "mb/google/kukui: Add flag for MIPI_DSI_MODE_LINE_END ANX7625") BUG=b:198558237 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Id5666fa1bcf96002725509d7436ea1ff5febef93 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57486 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10mb/google/asurada: power on panel after DSI is readyHung-Te Lin
Some bridge chips or panels require DSI signal output before the DSI receiver is ready to work. This patch is based on CB:47380 (commit b32e4d6, "mb/google/kukui: Add panel api after dsi start") BUG=b:198558237 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Id72560caee9352f88db2de7269b1472f56ac1bdf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57485 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-09mb/google/guybrush/var/nipperkin: Add ELAN TS supportKevin Chiu
ELAN TS: eKT3644 BUG=b:194961444 TEST=emerge-guybrush coreboot chromeos-bootimage TS is functional Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Id1601efbbe419bb28233a2678fdde005a55da671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09mb/google/dedede/var/gooey: Add fw_config probe for ALC5682-VD & VSStanley Wu
ALC5682-VD/ALC5682-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define SSFC bit 9-11 in coreboot for codec within ec. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:193694180 TEST=ALC5682-VD/ALC5682-VS audio codec can work Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Ib458cf47909a2d7a65f086c5f30f85a16f78d589 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09mb/google/brya/variants/kano: Update GPIOs config for kanoDavid Wu
Update the GPIO configuration to match the latest schematic. BUG=b:192370253 BRANCH=None TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I96be95a127f42b005d97a3c02650af13419524a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09mb/google/brya/variants/primus: update for next build phaseMalik_Hsu
According to the schematic diagram of version C14_MB_20210902A_SB, modify the settings of GPIO and fw_config. BUG=b:197700276 BRANCH=none TEST=emerge-brya coreboot Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I14907faeb631193715b1e0e451e427fb79a68279 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09mb/google/brya/variants/taeko: Add initial fw config for taekoJoey Peng
According to config.star fw mask definition, add initial FW_CONFIG id. BUG=b:194649740 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Cq-Depend: chrome-internal:4072654 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ifef750338d777b76e9710d6bca9a166120db6a0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09mb/ocp: Remove superfluous FSP header CPP inclusionArthur Heymans
This is already done in drivers/intel/fsp2_0/Makefile.inc. Change-Id: Idfd15d0a9d2cb15e613881f80bb25c18bd7454bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-08mb/google/dedede/var/magolor: Generate SPD ID for supported partTyler Wang
Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. MT53E512M32D1NP-046 WT:B BUG=b:199032134 TEST=emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ic9ccee7c0957119a69ee179854cf13d30db40621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-08mb/google/dedede/var/cret: Update DPTF parametersDtrain Hsu
Update DPTF parameters from internal thermal team and Intel suggestion. BUG=b:198249129 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I25d3909144d6e38d7a6eb859d33585c319a84b04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-08soc/amd/cezanne/fsp_m_params: set usb_phy version and length.Julian Schroeder
Setting the usb_phy version and length in the soc code instead of devicetree. That way the devicetree code does not have to reapeat it for different AMD Cezanne based systems. Tested on guybrush by changing phy settings in devicetree and then checking the usb phy register. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-08mb/google/guybrush/variants/baseboard/devicetree: update usb_phy versionJulian Schroeder
The AMD Cezanne FSP expects a usb phy config structure ID of 0xd 0x6. If the ID does not match, the FSP USB will not set up the phy. Tested on guybrush by changing phy settings in devicetree and then checking the usb phy register. Cq-Depend: chrome-internal:4087511 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I4fdb5af1cbc3c70cc113ef6f0fd9332e1a27f142 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-08mb/google/brya/var/redrix: Enable SaGv supportWisley Chen
Enable SaGv support for redrix BUG=b:198536984 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I54402dfde5db4106a4e0d891c19592fda39a1099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-08mb/google/dedede/var/cappy2: Add fw_config probe for ALC5682I-VSSunwei Li
Based on commit b9c22e09 (util/sconfig: Compare probe conditions for override device match), add fw_config probe for ALC5682I-VS headphone Audio Codec. BUG=b:197546020 BRANCH=dedede TEST=ALC5682I-VD/VS and CS42l42 work normally according fw_config Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Iac09663b095e758f1bc0cfaf7adb6e84d203788a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57105 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/system76/whl-u: Add missing device nodeNico Huber
All `chip` entries need a device node below them to actually get hooked up. Add a dummy generic device like other instances of this driver use. Change-Id: Ifbb5c9a6b389a2c809ce654d584d5197af764893 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57475 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/lenovo/x60: Fix devicetree hierarchyNico Huber
The Ricoh bridge device is actually on the external PCI bus. To make the driver configuration usable, also add a PCI device below it. Change-Id: I58a25da9d676a19b47e8b88438152bc247c024b4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57474 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/lenovo/x200: Fix X301 override treeNico Huber
`chip` entries always need a device node below them to actually get hooked up. Change-Id: Ib9e6019b6f316c1b176da1592514dcdcaf8c505a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57473 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/lenovo/x220: Fix override treesNico Huber
`chip` entries always need a device node below them to actually get hooked up. Change-Id: Ia5c573e582dab542b2a2a969c17581b0da6ed74e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57472 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/lenovo/t530: Fix override treesNico Huber
`chip` entries always need a device node below them to actually get hooked up. Change-Id: I91c98f66951de5301f72754a24a92168862820a2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57471 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/lenovo/t520: Fix T520 override treeNico Huber
`chip` entries always need a device node below them to actually get hooked up. Change-Id: I4781d6afdcd92f21872f3059b417483107129bf4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57470 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/lenovo/t430s: Fix override treesNico Huber
`chip` entries always need a device node below them to actually get hooked up. Change-Id: I244cd5d91af9413b338de0e8ee2480d9744ea077 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57469 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/lenovo/t400: Fix R500 override treeNico Huber
`chip` entries always need a device node below them to actually get hooked up. Change-Id: Ie84694f586351ce327c8df9338e96377825ad7c7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57468 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/kontron/bsl6: Fix overridden hwmon settingsNico Huber
Add missing device nodes as the `chip` entry needs one to actually get hooked up. Change-Id: If34f4919a5499b3148c7e4408cc753fbd909693a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57467 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/google/slippy: Fix overridden southbridge settingsNico Huber
To take any effect, a `chip` entry in a devicetree or overridetree always needs a `device` node. Change-Id: I158459e28dc8c63df4f1d58b30017868a57e5602 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57466 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08ec/acpi: Remove empty "chip" driverNico Huber
There was no code attached to this driver and hence one couldn't hook it up to any device. Even if mentioned in the `devicetree.cb` it was still dead code. Change-Id: I12415ea9e0120b1d00524f8f39f9b2d02f46ba05 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-08mb/google/guybrush: update the telemetry settingIvy Jian
Update the telemetry setting for guybrush vddcrvddfull_scale_current : 94648 #mA ddcrvddoffset : 785 vddcrsocfull_scale_current : 30314 #mA vddcrsocoffset : 560 BUG=b:189157660 TEST=Build Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I19ba3d69be63d0f8491d15ee48ce9ba468a46fdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/57193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-08mb/google/volteer/var/chronicler: change GPP_A8 pin defineSheng-Liang Pan
Set GPIO GPP_A8 as high to enable EN_PP3300_TOUCHSCREEN. also reduce enable delay time for meet panel power sequence. BUG=b:197668845 BRANCH=volteer TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage Verify no corruption is seen on the screen panel power sequence meet spec Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I9a0c1d0afafb2c446fcb3d18e1a67573218614e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57103 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/google/zork/var/vilboz: update device generic id for 10EC1015 AMP driverFrank Wu
Update generic id to generate the SSDT1 acpi table successfully BUG=b:196866470 BRANCH=firmware-zork-13434.B TEST=generate SSDT1 acpi table by command "iasl -d SSDT1" Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I09c9adc2db08e8e3905d9ba800948252230e4d54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-08mb/google/cherry: Fix incorrect timestamps in eventlogChen-Tsung Hsieh
The eventlog requires RTC to provide correct timestamps, so we have to turn on the config and add the common drivers. BUG=b:199003609 TEST=check timestamp in 'mosys eventlog list' BRANCH=none Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org> Change-Id: Ia382cd023fcbfdf2c1efeb7b32c0b99feb71effa Reviewed-on: https://review.coreboot.org/c/coreboot/+/57403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-09-08mb/amd/{bilby,mandolin}: Turn empty `chip` entry into commentNico Huber
A chip entry in the devicetree is not hooked up without a device beneath it. It seems the intention was to leave these superio drivers unconfigured, so there should be no harm to turn the entries into comments. Change-Id: I6b606f35eba089b74c562084772d95be41cac39c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-08soc/amd/common/include/acpimmio: reduce visibility of GPIO MMIO accessFelix Held
Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers while only allowing GPIO accesses through the GPIO API on the SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-07mb/google/brya/variants/gimble: update fw_config.c for next build phaseMark Hsieh
Update fw_config.c based on the schematic carbine_adl-p_evt_20210901.pdf BUG=b:190688567 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I240c0cd777d215e46a0a661aaac63a187311019d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-07mb/google/brya/variants/gimble: add GPP_B4 and GPP_D11 to early_gpio_tableMark Hsieh
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that gimble can successfully boot into OS with non-serial coreboot. BUG=b:198405404 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ib76965db2a6cd0c19be4043fec73af297a619c7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57359 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-07mb/google/brya/variants/gimble: Enable SaGv supportMark Hsieh
This patch enables SaGv support for gimble. BUG=b:198531517 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I29887418827614afb10558c6958c9c5e9667079e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marx Wang <marx.wang@intel.com>
2021-09-07mb/google: Add board name comments for each boardMartin Roth
Roughly half the boards had a "title" comment for the board. This adds it for the rest of the boards to make everything consistent. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ib941318842136212727f56fc6130381c5c9cd55b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-07mb/google/guybrush/nipperkin: update nipperkin configKevin Chiu
copy config from guybrush reference board. remove wwan & speaker amp due to the different solution is used on nipperkin. BUG=b:194031783 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I58a9b8393a965a9c793802d3e660829863b74375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-07mb/asrock/e350m1: Enable USB on mPCIeSebastian 'Swift Geek' Grzywna
Verified by running following on vendor and observing mPCIe USB device (dis)appearing: echo 1 > /sys/bus/pci/devices/0000:00:16.0/remove echo 1 > /sys/bus/pci/devices/0000:00:16.2/remove echo 1 > /sys/bus/pci/devices/0000:00:00.0/rescan Change-Id: I6ee7e3679c9cd87b81f955c68ec89db1dda30aec Signed-off-by: Sebastian 'Swift Geek' Grzywna <swiftgeek@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-07kontron/mal10: Set up GPIOs in CPLD/ECMaxim Polyakov
The COMe module connector implements 8 GPIO lines from the CPLD/EC pins. Use the Kempld GPIO driver[1] to configure these pins in accordance with the COM Express Module Base Specification [2]. TEST = Set different logic states for the pin configured as outputs and check them with an oscilloscope. [1] CB:47595 , Change-Id: Id767aa451fbf2ca1c0dccfc9aa2c024c6f37c1bb [2] page 79-81, PICMG (R) COM.0 Revision 3.0 COM Express (R) Base Specification - March 31, 2017. Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54380 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06mb/intel/shadowmountain: Enable SaGv supportV Sowmya
Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I15203920546363466eef567136821b59dda763b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06mb/lenovo: Use pci_and_config32Peter Lemenkov
Change-Id: I082d31d59660c48065f9390975817d3ed553da2d Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-06mb/intel: Drop unused `GPIO_MEM_CONFIG_.` definesAngel Pons
These defines are copy-paste leftovers from Kunimitsu. However, neither Saddle Brook nor KBLRVP use memory-down, so drop the unneeded defines. Change-Id: I396aeaa634f619be7be0ee97c0cab1c682f53ff2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-06mb/intel/kblrvp: Drop redundant overridetree lineAngel Pons
The I2C #5 device is already disabled in the devicetree. Change-Id: Ia4970dc07ef57e8184bce395a446974a22eddb08 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-06mb/intel/kblrvp: Mark disabled SerialIO devices as `off`Angel Pons
Disable devicetree devices disabled in the `SerialIoDevMode` array. These devices get disabled by FSP-S, and coreboot doesn't see them. Change-Id: I8dbb45c96eae5188e5999df9a458f06f6b196adf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-06mb/intel/kblrvp: Do not use Legacy mode for UART #2Angel Pons
All KBLRVP variants select the `INTEL_LPSS_UART_FOR_CONSOLE` Kconfig option and set `UART_FOR_CONSOLE` to `2`, so that UART #2 is used as coreboot console. However, the LPSS console driver requires the LPSS UART to be memory-mapped (and not I/O-mapped, like Super I/O UARTs). KBLRVP variant RVP8 uses `PchSerialIoLegacyUart` for UART #2, which makes FSP-S configure UART #2 in legacy, I/O-mapped mode. This most likely results in the UART console not working after FSP-S has run. This change updates RVP8 to use `PchSerialIoSkipInit` for UART #2, like the other KBLRVP variants do. Change-Id: Ic5c78f5895fe1dd5e7be6ef7aec3de6940dd2475 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 03:31:25 +0000