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2020-08-05baytrail mainboards: Clean up mainboard.cArthur Heymans
This cleans up some unneeded no-ops in the mainboard.c files of baytrail boards. Change-Id: I7662f6e860d672a99b211488122bec073cc78acf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-05mb/google/zork: update DRAM SPD table for dirinbozKevin Chiu
DRAM support list 0x00 HYNIX HMA851S6CJR6N-VK 0x01 HYNIX H5ANAG6NCMR-VKC 0x02 Samsung K4A8G165WC-BCTD 0x03 Samsung K4AAG165WB-MCTD 0x04 Samsung K4A8G165WC-BCWE 0x05 HYNIX H5AN8G6NDJR-XNC 0x06 HYNIX H5ANAG6NCMR-XNC 0x07 Micron MT40A512M16TB-062E:J 0x08 Micron MT40A1G16KD-062E:E 0x09 Samsung K4AAG165WA-BCTD 0x0A Samsung K4AAG165WA-BCWE BUG=b:161579679 BRANCH=master TEST=build Change-Id: Ib9fa5ae98568d659326d431a4006174a343fa299 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-04mb/google/zork/var/vilboz: Enable support for garaged stylusFurquan Shaikh
This change adds support for pen insert/eject operations in S0 and wake on pen eject from S3 for vilboz. BUG=b:157628650 Change-Id: I7ba0881b67dfb67c032667d591f7d1806a50af22 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-04mb/kontron/bsl6: Add new Skylake COMe moduleNico Huber
Add Kontron/bSL6 together with Siemens/Boxer26, a baseboard for the bSL6. The plain bSL6 variant received little testing and only during early development. The Boxer26 variant is actively used and fully tested. The latest rebase was boot tested with FILO and Linux 4.19. Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29480 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04soc/intel/baytrail: Factor out `acpi_fill_madt()`Angel Pons
It is the same for the two Bay Trail boards in the tree. Change-Id: I5110cfa8807406232e4f7f1fe79dfe9c3ae4dac4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
2020-08-04mb/supermicro/x11ssh-tf: Drop `PcieRpClkReqSupport` linesAngel Pons
They default to zero already, so we might as well drop them. Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I3c04240b270f51d584f879e1344301679f133fdb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43928 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03mb/gizmosphere/gizmo/mainboard.c: Remove white space after 'mdelay'Elyes HAOUAS
Change-Id: Ib7c6ab0a2e5a03f30b70c4bbb1091fa9c689c23b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44094 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/google/zork: Pass oscout system clk to rt5682Akshu Agrawal
In kernel clk for AMD SoCs we expose a generic clk by the name oscclk1. This oscclk1 is a fixed 48Mhz frequency clk in RV. In Zork oscout system clock is linked to rt5682 mclk. Setting mclk-name to oscclk1 tells rt5682 driver its mclk is oscclk1. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> BUG=b:158906189 TEST=rt5682 driver get the correct clk and tested audio playback Change-Id: Ic565e8e0573e085e5759b2d3688cc0a4533b67fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/44010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-03mb/bostentech: Add GBYT4 portMate Kukri
- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an IT8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch CB:43133) - Booting from SATA works with GRUB2, SATA works in Linux - Patch CB:44088 fixes SATA in SeaBIOS - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything Used rambi as an example, but almost everything is modified as the two boards are very different. Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03mb/asrock/h110m: Relocate devicetree settingsAngel Pons
Some settings are suspicious, and have been annotated with FIXMEs. Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I7755867cb92745f542a4261db5dd118ca905612b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Drop `D0F0_` prefix from register namesAngel Pons
Only some registers have such a prefix. Drop it for consistency. Change-Id: I1ef7307d10a06db8f3c1a05bd9184f21fceb9d90 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03mb/google/dedede: Update CPU critical temperatureSumeet R Pawnikar
Observed thermal shutdown initiated by DPTF due to CPU temperature reaching critical temperature trip value. During stress testing with heavy workload like WebGL Aquarium, sometime CPU temperature spikes till 99 degree Celsius and DPTF initiates system shutdown. This updates CPU critical temperature trip value to 105 degree Celsius to avoid system shutdown. BUG=b:161993459 BRANCH=None TEST=Built and tested on dedede system Change-Id: If15a873a997aa80f20940f27bbafd4498908c091 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44054 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/google/kukui: Add Micron 8GB discrete LPDDR4X DDR supportHuayang Duan
Support 8GB MT53E2G32D4NQ-046 discrete DDR bootup. BUG=b:159301679 BRANCH=kukui TEST=Boots correctly on Kukui. Change-Id: Ide01f029c5ebd6c3ae6350f73f3c60b818d51353 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-03mb/intel/cedarisland: Remove duplicated codeMaxim Polyakov
Some UPD options are already set in `xeon_sp/cpx/romstage.c`. Remove them from the board configuration to avoid duplicating this code. Change-Id: Ic79245103c33427e06c7ea881be778e3d219c45f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43924 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/intel/cedarisland: Use FSP_M_CONFIG structure to set UPDMaxim Polyakov
According to src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h, use FSP_M_CONFIG structure fields to configure UPD options for FSP-M in romstage instead of raw offsets. Change-Id: Idb25d8954b09805b496ab97b341a8ef1ac38bb6a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03mb/google/dedede/var/madoo: Add discrete WiFi configurationDtrain Hsu
Add RTL8822CE support for Madoo. BUG=b:162390420 BRANCH=None TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage, build successful Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I6e471be2b2856977e6f728d5a2ca78942725bea6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-03mb/google/dedede/var/madoo: Support Elan touchpad and configure I2C portsDtrain Hsu
1. Add Elan touchpad support. 2. Follow schematic to disable I2C1 and I2C3. BUG=b:160869188,b:161407664 BRANCH=NONE TEST=emerge-dedede coreboot chromeos-bootimage", build successful Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I154a1ff2597968d200d1d0693718f90cd2744616 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-03mb/google/dedede/var/madoo: Enable Goodix touchscreenIan Feng
Add Goodix touchscreen support. BUG=b:160868197 BRANCH=None TEST=emerge-dedede coreboot chromeos-bootimage", build successful Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I9bf27d69d0895cb4ea8620a6da49e98d25e05c23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44012 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/up/squared/gpio: 3/3 Convert bit field macros to PAD_CFGMaxim Polyakov
Converts bit fields macro to target PAD_CFG_*() macros, which were hidden in the comments. To do this, the following command was used: ./intelp2m -n -t 1 -p apl -file ./test/up-gpio.h This is part of the patch set "mb/up/squared: Rewrite pad config using intelp2m": CB:42608 - 1/3 Decode raw register values CB:42915 - 2/3 Exclude fields that are not in PAD_CFG* CB:39765 - 3/3 Converts bit field macros to PAD_CFG Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I266ec6fa10a9691a7b7d3cd6f2792624e8bd53d5 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03mb/up/squared/gpio: 2/3 Exclude fields that are not in PAD_CFG*Maxim Polyakov
This patch excludes bit fields that must be ignored in order to convert current macros to target PAD_CFG_*() macros. The following commands were used for this: ./intelp2m -ii -fld cb -ign -t 1 -p apl -file ./up-gpio.h This is part of the patch set "mb/up/squared: Rewrite pad config using intelp2m": CB:42608 - 1/3 Decode raw register values CB:42915 - 2/3 Exclude fields that are not in PAD_CFG* CB:39765 - 3/3 Converts bit field macros to PAD_CFG Change-Id: Ic9b6e63c1b84b97726886bef35c434dd9153eb78 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-03mb/up/squared/gpio: 1/3 Decode raw register valuesMaxim Polyakov
Use the intelp2m utility [1] with -fld=cb options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to generate the target macro in the comments, so that it is easier to understand what result we should get: ./intelp2m -ii -fld cb -t 1 -p apl -file ./up-gpio.h This is part of the patch set "mb/up/squared: Rewrite pad config using intelp2m": CB:42608 - 1/3 Decode raw register values CB:42915 - 2/3 Exclude fields that are not in PAD_CFG* CB:39765 - 3/3 Converts bit field macros to PAD_CFG [1] https://review.coreboot.org/c/coreboot/+/35643 Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I2523439af8842365c7de901bdfad85ad16d25dcf Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03mb/google/volteer: Change wake to be triggered on a raising edgeAlex Levin
ACPI_GPIO_IRQ_EDGE_BOTH sets both edges as wake. The desired behavior is wake on rising edge, change to ACPI_GPIO_INPUT_ACTIVE_LOW. Fixing for both Volteer and Volteer2 variants. BUG=b:146083964 BRANCH=None TEST=tested on a Volteer Change-Id: I2d3339151bf4e2cbae60aaf97ba1bd7909a2b9a9 Signed-off-by: Alex Levin <levinale@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-03mb/emulation/qemu-armv7: Fix boardPatrick Rudolph
Fix multiple issues allowing to boot until "Payload not loaded": * The FMAP_CACHE was placed in memory mapped flash - Place the FMAP_CACHE in DRAM. * The FMAP_CACHE was overlapping the BOOTBLOCK, which has a default size of 128KiB. - Increase the bootblock size in memlayout to 128KiB to match the FMAP. * The heap in bootblock wasn't usable. - Add a linking check in armv7 common bootblock to relocate itself to the linked address. * A FIT payload couldn't be compiled in as the POSTRAM_CBFS_CACHE was missing. - Add the POSTRAM_CBFS_CACHE to memlayout. * The coreboot log is spammed with missing timestamp table error messages - Add TIMESTAMP table to memlayout. Tested on QEMU armv7 vexpress. Change-Id: Ib9357a5c059ca179826c5a7e7616a5c688ec2e95 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03mb/google/kukui: indent config names for burnet and escheHung-Te Lin
The 'burnet' and 'esche' in Kconfig.name should have two spaces after the arrow. BUG=None TEST=make menuconfig BRANCH=kukui Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43986 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/google/volteer/var/todor: Support ELAN i2c-hid touchpadDavid Wu
Update ELAN i2c-hid touchpad configuration BUG=b:160741785 BRANCH=None TEST=Verify touchpad is working fine. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2549048766d0707666910bd86c46ac9201bf3905 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43998 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/google/zork: Add Samsung K4AAG165WA-BCTD SPDKevin Chiu
For dirinboz DRAMID 0x9: K4AAG165WA-BCTD BUG=b:161579679 BRANCH=master TEST=build Change-Id: I28c0d23f96c5b9c975ffead3a1cac66cbda8c293 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-07-31mb/ocp/deltalake: configure DIMM_MAXJonathan Zhang
DeltaLake is a single socket server. Its platform design has 1 DIMM slot per channel. There are 6 DIMM slots. Configure DIMM_MAX to overwrite SOC default. Change-Id: I47ecc81452fe59ed59fd3a239ffe329cbc031d7a Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44048 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31drivers/ipmi/ocp: Add function to support OCP specific ipmi commandTim Chu
Add driver for OCP specific ipmi commands. With this driver, OCP specific ipmi command can be used after implementing functions here. TEST=Build with CB:42242 on Delta Lake, select Kconfig option: IPMI_OCP and add device in devicetree to open this function. Use ipmi-util in OpenBMC to dump raw data and check if this function work. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I2efa85978ec4ad3d75f2bd93b4139ef8059127ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/43996 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31mb/ocp/deltalake: Update SMBIOS type 4 -- Processor InformationMorgan Jang
TEST=Execute "dmidecode -t 4" to check if the processor information is correct for Deltalake platform Change-Id: I5d075bb297f2e71a2545ab6ad82304a825ed7d19 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-30mb/intel/tglrvp/Kconfig: Drop unnecessary choice nameAngel Pons
The only reason to use a named choice statement is if you plan on having the choice statement in multiple places. Since the `TGL_EC` name is not used anywhere else, we might as well get rid of it. Change-Id: Ic0bddefd007ef961bbff61fd656475cae78148e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30mb/amd,google/mandolin,zork: Set EFS SPI platform configMatt Papageorge
Set platform defaults for SPI settings in Kconfig for EFS. BUG=b:158755102 TEST=Build and boot test on Tremblye and Morphius. Verify values in output image in a hex editor. Measure 1st x86 timestamp, perf improves by over a second. Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30mb/google/zork: remove indirection for dxio lane configurationAaron Durbin
There was a mix of open coding DXIO logical lane numbers and clkreq pins. And there are separate macros depending on the baseboard as well as processor type. Remove the indirection and supply the values directly in the descriptors. BUG=b:162423378 Change-Id: I779cb0a514e3b668265e6039d6e7e7bd0f3d49ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-30mb/google/zork/var/ezkinil: Configure boot media for new SKUsLucas Chen
Configure the correct eMMC present flag for Ezkinil new added sku_id. 0x5A020015 NVME present 0x5A020016 eMMC present 0x5A020017 eMMC present BUG=b:159761042 TEST:none Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: I1b89cc4568283d5dbebf0ab7ac578368d3a3637e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43753 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30mb/google/zork: add USB over-current pin mapping to devicetreeFelix Held
BUG=b:162010077 Change-Id: Iba3e3ec62cdfd818077017abd28fa754c2ae7797 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-30mb/ocp/tiogapass: Add SMBIOS type8 data tableBryantOu
According to MP MB to port SMBIOS type8 data. Tested=Use "dmidecode -t 8" to dump SMBIOS data, and check if type8 tables are implemented. Change-Id: I356e645774d78c623c1398c8b1473562e1529cf2 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-30mb/ocp/deltalake: Add VPD variable for FRB2 timer actionJohnny Lin
Tested on OCP Delta Lake, the timer action can be set correctly. Change-Id: I1013169e12455e01214d089c9398c78143af4df8 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44019 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30mb/google/dedede: Add Goodix touchscreenEvan Green
Add overridetree info for the touchscreen. BUG=b:160129126 TEST=cros flash-ap -b dedede Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I55fc0749b824a0bf4b615d02bd8bc39bcdd589e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-29mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configurationJohn Zhao
It is expected both of TCSS D3Hot and D3Cold are enabled by default. BUG=None TEST=Verified both of TCSS D3Hot and D3Cold configuration on TGLRVP. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Id569d8191f82f12379b57a9c50aec31776220bb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-29mb/google/volteer: Update TCSS D3Hot and D3Cold configurationJohn Zhao
It is expected TCSS D3Hot is enabled. D3Cold configuration is through SoC stepping determination. D3Cold is disabled on pre-QS platform and enabled on QS platform. BUG=None TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/skylake: Enable HDA depending on devicetree configurationFelix Singer
Currently HDA gets enabled by the option EnableAzalia, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HDA controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableAzalia setting. Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/skylake: Enable HECI3 depending on devicetree configurationFelix Singer
Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HECI3 controller. I checked all corresponding mainboards if the devicetree configuration matches the Heci3Enabled setting. Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/skylake: Enable eMMC depending on devicetree configurationFelix Singer
Currently eMMC gets enabled by the option ScsEmmcEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the eMMC controller. I checked all corresponding mainboards if the devicetree configuration matches the ScsEmmcEnabled setting. Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-29soc/intel/skylake: Enable TraceHub depending on devicetree configurationFelix Singer
Currently TraceHub gets enabled by the option EnableTraceHub, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the TraceHub controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableTraceHub setting. Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/skylake: Enable SMBus depending on devicetree configurationFelix Singer
Currently SMBus gets enabled by the option SmbusEnable, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SMBus controller. I checked all corresponding mainboards if the devicetree configuration matches the SmbusEnable setting. Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-29soc/intel/skylake: Enable LAN depending on devicetree configurationFelix Singer
Currently LAN gets enabled by the option EnableLan, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableLan setting. Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-29soc/intel/skylake: Enable SATA depending on devicetree configurationFelix Singer
Currently SATA gets enabled by the option EnableSata, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SATA controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableSata setting. Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-29mb/google/zork: update stapm parameter for berknipKevin Chiu
sustained_power_limit = 12w fast_ppt_limit = 24w slow_ppt_limit = 20w BUG=b:162377903 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Change-Id: I9baf9990e26edbbadfba85bc16b380c46684033d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-29mb/intel/tglrvp: Add support for USB Type-C connector device propertiesJohn Zhao
This change updates TGLRVP configuration to have USB Type-C connector device properties filled into ACPI SSDT. TEST=Built and booted to kernel on tglrvp boards. Verified the USBC scope under LPCB.EC0.CREC with required connector device properties. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-29mb/google/dedede/var/magalor: Generate SPD ID for supported partsKarthikeyan Ramasubramanian
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory part being added is: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR BUG=None TEST=Build the magalor board. Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-29mb/supermicro/x11-lga1151-series: correct superio interruptsMichael Niewöhner
Add interrupts for all enabled superio devices to quiet the warning about missing interrupts in devicetree. Vendor uses interrupt 0x00 for all devices except SUART* and KBC, so let's do that, too. This also changes SWC from 0x0b to 0x00. Verified with superiotool on X11SSM-F. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I7a6dc7345f020e53415a7d0d104ce93ab4b194fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonas Löffelholz Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-29mb/ocp/tiogapass: Configure IPMI FRB2 watchdog timer via VPD variablesJohnny Lin
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value in romstage. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Add RO_VPD and RW_VPD sections. Tested on OCP Tioga Pass. Change-Id: I53b69c3c5d22c022130fd812ef26097898d913d0 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-28mb/google/zork: Add Bluetooth reset gpios to devicetreeRob Barnes
Add bluetooth reset gpio 143 to dalboz baseboard devicetree Add bluetooth reset gpio 14 to trembyle baseboard devicetree Remove bluetooth reset_gpio when not supported on a specific board variant. BUG=b:157580724 TEST=Boot Ezkinil with Realtek 8822CE, observe log [ 12.240720] Bluetooth: af_bluetooth.c:bt_init() HCI device and connection manager initialized [ 12.249272] Bluetooth: hci_sock.c:hci_sock_init() HCI socket layer initialized [ 12.256520] Bluetooth: l2cap_sock.c:l2cap_init_sockets() L2CAP socket layer initialized [ 12.264575] Bluetooth: sco.c:sco_init() SCO socket layer initialized [ 12.273700] usb 3-2: GPIO lookup for consumer reset [ 12.273702] usb 3-2: using ACPI for GPIO lookup [ 12.273705] acpi device:18: GPIO: looking up reset-gpios [ 12.273707] acpi device:18: GPIO: looking up reset-gpio [ 12.273711] acpi device:18: GPIO: _DSD returned device:18 0 0 0 [ 12.273737] gpio gpiochip0: Persistence not supported for GPIO 14 [ 12.273960] usbcore: registered new interface driver btusb Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-28mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4John Zhao
Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux. TEST=Built image-tglrvp-up4.bin successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I8423ddbb5bc189899a9e19e7da6e2ee7b7fecc18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-28mb/lenovo/{l520,t430}/acpi/platform.asl: Rearrange codePeter Lemenkov
Rearrange code to unify with the rest of xx20/xx30 boards. No functional changes - just smaller diff output. Change-Id: I5867b2a90b2e53a3a9dd919701f1e185cb39cf78 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-28mb/lenovo/*/acpi/superio.asl: Replace with GPLv2+ equivalentPeter Lemenkov
Replace functionally identical files with t440p/acpi/superio.asl which is licensed under more flexible terms (GPL-2.0-only or no licensing terms vs. GPL-2.0-or-later). Apart from licensing terms these files are identical. This makes diff between boards smaller. Change-Id: I1cd4a85b65ceaa0a383416e7276ad41a41783cb7 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43685 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/dedede/var/madoo: Generate SPD ID for supported partsDtrain Hsu
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: H9HCNNNBKMMLXR-NEE MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR BUG=b:161215903 BRANCH=NONE TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib61af2399541c4caf4a310a34e778e0ba1cbd3ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/43802 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/dedede/var/madoo: Add audio support (ALC5682, MX98360A)Dtrain Hsu
Select the drivers for ALC5682 codec and MX98360A spk amp BUG=b:161407664 BRANCH=NONE TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ibe3d878b1058bfae4143d96be854884e61394ad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-28mb/google/dedede/var/madoo: Configure USB port setting for MadooDtrain Hsu
Follow schematic to modify USB port setting and clean up I2C clock tuning. USB2 [0]: USB Type C Port 0 USB2 [1]: USB Type C Port 1 USB2 [2]: None USB2 [3]: USB Type A Port 1 USB2 [4]: None USB2 [5]: Camera USB2 [6]: None USB2 [7]: WLAN module - BlueTooth USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: USB Type C Port 1 (Sub/B side) USB3 [2]: None USB3 [3]: USB Type A Port 1 USB3 [4]: None USB3 [5]: None BUG=b:161407664 BRANCH=NONE TEST=Build the coreboot image on madoo board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ia73593f52adee3806e725127891f084a08bf1360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43750 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/dedede/var/madoo: Configure GPIO for MadooDtrain Hsu
Follow schematic to modify some GPIO pins. GPP_D12 - NC Pin GPP_D13 - NC Pin GPP_D14 - NC Pin GPP_D15 - NC Pin GPP_E0 - NC Pin GPP_E2 - NC Pin GPP_H6 - NC Pin GPP_H7 - NC Pin GPP_S02 - NC Pin GPP_S03 - NC Pin BUG=b:161407664 BRANCH=NONE TEST=Build the coreboot image on madoo board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I85aadfb0d020055eec921c7646c16ae6c95a606f Reviewed-on: https://review.coreboot.org/c/coreboot/+/43745 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/volteer/var/voxel: Add memory configurationSheng-Liang Pan
Update dq/dqs mappings based on voxel schematics. BUG=b:155062561 BRANCH=none TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ida248094a1477fe457026e18f313385082ee71f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/volteer/var/volteer: I2C5 trackpad bus freq 400 kHz Johnny Li
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If59502aec7c3ab55864a518d626cde52aee18373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43746 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/volteer2: Add support for passive USB-C daughterboardCaveh Jalali
This copies over the USB daughterboard device tree config from volteer to volteer2. These two boards are basically identical in this area so the config should also be identical. BUG=b:158673460 TEST=none Change-Id: If8a82bc18b36d92a1c851b49612edfbefa18ec54 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-28mb/google/dedede/var/waddledee: Add discrete WiFi configurationKarthikeyan Ramasubramanian
BUG=b:161734657 TEST=Ensure that the discrete WiFi information is built into ACPI table. Scope (\_SB.PCI0.RP01) { Device (WF00) { Name (_UID, 0x923ACF1C) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x43, 0x03 }) } } Change-Id: I9a9259e167fc213291b89e151729553ec4649eaf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43769 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/amd/mandolin: remove ACPI_FADT_RESET_REGISTER from fadt_flagsFelix Held
This applies what commit 79572e4f32f844f60338d1aafdba6b94f4111a5c does to the devicetree settings of amd/mandolin. Change-Id: I6cc0a2b60b13a809016225caf3c89f730deb4ce0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-28mb/prodrive/hermes: Relocate device enable optionsFelix Singer
Since there aren't any other variants, we can move things between the devicetree and the overridetree. Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change. Change-Id: I54aac67237a3850dbf11f58bd41aba87505214f3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43927 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/prodrive/hermes: Add ME interface numbers to commentsFelix Singer
Change-Id: Ief8d53b79918d4d68bf10650ff796a27b67d862b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/system76/lemp9: Relocate device enable optionsFelix Singer
Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change. Change-Id: I655bc7576e8ff48258a2a19387e01372f4bbea3d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-28mb/google/volteer: sync'ing todor with terradorYH Lin
Todor is created to take the place of terrador therefore copying terrador content into todor's setup. BUG=b:162110806 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TODOR Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I63151728a04f2252ca8a77158a2656ad8b1e1b51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-07-28mb/google/volteer: Create todor variantYH Lin
Create the todor variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). In addition, * sort the variant names in alphabetical order. * todor uses the same config options as terrador. BUG=b:162110806 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TODOR Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I7aa7acf1f3c3cc14b92ded05d5868818a627a432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-28mb/ocp/deltalake: use common driver to configure GPIOBryant Ou
Use the common driver to configure the GPIOs on the Delta Lake platform as done for Tioga Pass in commit 89d2aa0. The GPIO settings are dumped by inteltool with original UEFI firmware, then use intelp2m to generate header file. TEST=Dump GPIO settings by Intel ITP and check if match gpio.h. Change-Id: I8005d4caa2d87b6831099bfec3a40246224f3cb5 Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-28broadwell: Factor out PIRQ routing from devicetreeAngel Pons
All boards disable PIRQs, except purism/librem_bdw. Since IRQ0 is invalid and modern OSes don't use PIRQ routing, disable the PIRQs. Change-Id: I93b074474c3c6d4329903cab928dc41e1d3a3fb3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-28lynxpoint: Factor out PIRQ routing from devicetreeAngel Pons
All boards disable PIRQs. They aren't used on modern OSes anyway. Change-Id: I1351fd4a3910e8cf2e9afe51dc2e82c7464de403 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-28volteer: Create eldrid variantMiceLin
Create the eldrid variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:162115131 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_ELDRID Signed-off-by: MiceLin <mice_lin@wistron.corp-partner.google.com> Change-Id: I1cd07ee7a87335e1e0b51d65c26bffc3bc46037c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-27mb/amd/mandolin: add USB over-current pin mapping to devicetreeFelix Held
The over-current pin mapping matches the board schematics. Change-Id: I23fd208680dcb52f5adaa144f00cb46bc7a21b91 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27mb/google/hatch: Add smart battery I2C passthrough for DratiniTim Wawrzynczak
Some smart battery patches have been backported to the ChromeOS 4.19 kernel, and userspace can now access smart battery data from sysfs instead of using the hacky ectool instead. Also change all space indents into tab indents while we're here. BUG=chromium:1047277 TEST=confirmed a /sys/class/power_supply/sbs-i2c device shows up Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I43687e63e4c1a7756c117129ced20749afc1b9e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-27mb/google/kukui: Add discrete LPDDR4X DDR table support for burnet/escheKevin Chiu
LPDDR4x DRAM table for burnet/esche: [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB" [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB" [3] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB" [4] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB" BUG=b:161768221,b:159301679 BRANCH=master TEST=emerge-jacuzzi coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ida7ab877c3f7e10a67680b69a1d724ec734d2928 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-27mb/google/volteer: Add gpio-keys ACPI node for PENHAlex Levin
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. Removal and insertion (both edges) triggers IRQ and only removal is a wake event (rising edge). Adding for both Volteer and Volteer2 variants. BUG=b:146083964 BRANCH=None TEST=tested on a Volteer Change-Id: Ida3217a5b156320856ce3302c2623eba2230f28d Signed-off-by: Alex Levin <levinale@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43764 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-27mb/google/volteer: Modify Delbin variantKane Chen
Update delbin configuration include GPIO, memory SPD table, I2C devices and USB type C. BUG=b:158797761 BRANCH=None TEST=emerge-volteer coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I59ce4720e0ffeeeb2c9440bb300686def80211ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/42301 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-27mb/google/dedede: Remove Rcomp resistor and target valuesMeera Ravindranath
MRC automatically detects the DDR type and sets Rcomp resistor and target values for JSL and does not require explicit programming. Change-Id: Ia130765e2cb91d6a39ad00ebbab20e7e87fa42d1 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27dedede: Create magolor variantRen Kuo
Create the magolor variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:58540772 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_MAGOLOR Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I3e39e650b82a0aa629a48a00227700b058effb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-26mb/intel/cedarisland/Makefile: Add missing ramstage.cMaxim Polyakov
Fixes a bug in Makefile.inc, which did not allow building ROM image with ramstage.c from motherboard configuration. Change-Id: I70d8a2e1f53e2fa56d514361116a55f175407753 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43457 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/*/*/devicetree.cb: Normalize disabled PIRQ valuesAngel Pons
If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use PIRQ routing, so we might as well zero the other bits for consistency. Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots. Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/lenovo: Prepend EC event number with 0x to denote hex notationPaul Menzel
Currently, the message below is printed, suggesting it’s decimal notation: coreboot-4.12-1530-g7acbd5fc45 Sun Jul 19 07:47:58 UTC 2020 smm starting (log level: 7)... EC event 48 GPI (mask 1000) Prepend 0x, so it’s clear it’s hexadecimal notation. EC event 0x48 Use the command below change all places: git grep -l 'EC event %02x' | xargs sed -i 's/EC event %02x/EC event %#02x/' Change-Id: I8d1e6434a0e550c5a19576f9f7fea05e7a812e49 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26mb/asrock/h110m: undo set trig and bufdis for NF padsMaxim Polyakov
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set this fields to 0. [1] Intel document #549921 [2] Intel document #336067-007US This is part of the patch set "src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ": CB:43455 - cedarisland: undo set trig and bufdis for NF pads CB:43454 - tiogapass: undo set trig and bufdis for NF pads CB:43561 - h110m: undo set trig and bufdis for NF pads CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG Change-Id: I6a6b745bdaacb1c4fbf032e4ce54cb25a72d790a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43561 Reviewed-by: Michael Niewöhner Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF padsMaxim Polyakov
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set these fields to 0. [1] Intel document #549921 [2] Intel document #336067-007US This is part of the patch set "src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ": CB:43455 - cedarisland: undo set trig and bufdis for NF pads CB:43454 - tiogapass: undo set trig and bufdis for NF pads CB:43561 - h110m: undo set trig and bufdis for NF pads CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43454 Reviewed-by: Michael Niewöhner Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/google/volteer/var/terrador: Support ELAN i2c-hid touchpadDavid Wu
Update ELAN i2c-hid touchpad configuration BUG=b:160741785 BRANCH=None TEST=Verify touchpad is working fine. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I098d8a305c6e04af1562a545ff4af6383665798b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-26mb/purism/librem_skl: Disable CLKREQ for NVMeMatt DeVillier
This effectively reverts commit 5086ccef (mb/purism/librem_skl: Fix CLKREQ for 15v3 NVMe). Some Librem 15v3/v4 boards are showing issues with NVMe detection or booting via SeaBIOS, so revert this until a proper fix can be found. Test: build / successfully boot Librem 15v4 with problematic NVMe drive. Change-Id: I0659f77bbe693f3d3b192a28ff3ef013658930cc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43490 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/google/kukui: send SKU ID to EC for device-specific configurationHung-Te Lin
For devices sharing same firmware, there may be few customization based on SKU ID - for example being clamshell or form factor. On Kukui and Jacuzzi platforms the SKU ID is defined on AP SOC, so we have to send the information to EC. BUG=b:161767717 TEST=make -j # builds and boots on Juniper BRANCH=kukui Change-Id: I8ffdd9fd1e609c1dd4b0e22dc7aab560ccdc842e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43788 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/mainboard/dedede: update GPIO table for Botenyan.liu
Adjust GPIO setting to match boten design BUG=b:160741777 BRANCH=NONE TEST=Add gpio.c for boten Signed-off-by: Yan Liu <yan.liu@bitland.corp-partner.google.com> Change-Id: I4eafee608f657f8ec5a06caf6e99b08b3330512b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43277 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/google/dedede: Change HDMI DDC GPIOs to native functionMaulik V Vaghela
HDMI DDC GPIOs were configured as NC till now in waddledoo. This may cause HDMI i2c transfer to break and EDID read will fail due to wrong configuration Configuring these GPIOs as NF in coreboot to fix the issue. BUG=b:160324327 BRANCH=None TEST=HDMI works on DDI2 onn Type-C port Change-Id: If02f062132d7c3b01b07ea9401e81f451df35c3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43294 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/google/vilboz: Tune I2C bus 3 clockpeichao.wang
Tune I2C bus3 frequency and insure it meets I2C spec. BUG=b:161650117 TEST=flash coreboot to the DUT and actual measured I2C bus3 make sure it meet Spec. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ifa9f0bce723f55a12fd2313788c995f8326e3e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26mb/emulation/qemu-i440fx/northbridge.c: Use SMBIOS macrosElyes HAOUAS
Change-Id: I0297c8c4008d9e448793c38a3758dced9ede0d7e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26mb/intel/tglrvp: Update MAINBOARD_PART_NUMBERAnil Kumar
- Update MAINBOARD_PART_NUMBER for TGL variants - MAINBOARD_PART_NUMBER is reported as FRID on acpi - This is required for cros_config to differentiate across TGL variants. - Mosys uses cros_config to identify TGL variants using data read from FRID Bug=none Test=build and boot coreboot on TGLRVP UP3 hardware Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I11d4ab2a5b6ade6c50988a9fec4d9866fe79d7b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-07-26mb/asus/p2b: Enable hardware monitor access via I/O on ISA busKeith Hui
Set up a 8-byte I/O range at 0x290-0x297 as PIIX4's generic device 9, which activates a chip select when this range is accessed. On the P2B family it connects to the W83781D hardware monitor, allowing access to it over the ISA bus, just like vendor firmware. Apparently this does not work on p3b-f, but no ill effects observed either. TEST=On p2b-ls lm-sensors can detect chip and get readings over ISA. Change-Id: Iaed1df7230359e94c580c305f4769c8bb4f5fce0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove unneeded space in license headerElyes HAOUAS
Change-Id: Iac0f0c3d102a9a900ac168f8be907349d9a3dd42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43565 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/google/dedede/var/drawcia: Add G2Touch touchscreen supportWisley Chen
BUG=b:155002684 TEST=build drawcia, and check touchscreen can work Change-Id: I29a891e07bb3c1d8ebe17666c18bfcf3bc1c361d Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-26Kconfig: Remove unnecessary choice namesMartin Roth
The only reason to use a named choice statement is if you plan on having the choice statement in multiple places. Since none of these are used in multiple places, we can get rid of the names. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie5f84e9dc38050234976bd193ac5fbf649e564f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26mb/asus/p2b: Drop select SMPKyösti Mälkki
Variants that select BASE_ASUS_P2B_D will also get MAX_CPUS==2 below, so this was redundant. Change-Id: I9048a4821f19d90e1489b09e294d2551941abf10 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43809 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>