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Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:266696987
BRANCH=None
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I9b50ab3c0bcef192ef89f173852cda222f1533c7
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
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Enable the HPD GPIO so that the USB-C port can be used for
DisplayPort.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If93d08f64cf7b09bb47622bdc7f22280b8a48174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72431
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables CNVi_BT Core and Wifi for mtlrvp based on mtlrvp
schematics.
1. Enable CNVi BT Core in device tree
2. Enable CNVi Wifi (pci 14.3) device in device tree
BUG=b:224325352
BRANCH=None
TEST=Able to observe corresponding UPD configuration with FSP dump and
able to boot mtlrvp (LP5/DDR5) to ChromeOS.
CNVi Mode = 1
Wi-Fi Core = 1
BT Core = 1
BT Audio Offload = 0
BT Interface = 1
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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The patch disables Tccold Handshake to prevent possible display
flicker issue for skolas board. Please refer to Intel doc#723158
for more information.
BUG=b:221461379
BRANCH=firmware-brya-14505.B
TEST=Boot to OS on Skolas, verify upd setting.
Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68636
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ADL-N 15W CPU thermal settings.
BUG=b:265101768
TEST=emerge-nissa coreboot
Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71860
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Removed workaround since the latest schematics fixed.
Power Sequencing of ELAN6918 (in ACPI) after this patch
`POWER enabled -> RESET deasserted -> Report EN enabled`
BUG=b:247029304
TEST=Verified ELAN touch panel is working as expected after booting
Google/rex device to ChromeOS.
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I19629262776f7e0cccbdebb2285890d177a8a8a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72725
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Create overridetree and GPIO config based on latest schematic:
1. Update PCIe ports
2. Update USB ports
3. Remove unused I2Cs
4. Remove unused peripherals (SD card, eDP, speakers)
5. Add LAN
6. Thermal policy for updated temp sensors
BUG=b:260934185, b:260934719
BRANCH=dedede
TEST=build
Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe
Signed-off-by: Liam Flaherty <liamflaherty@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71882
Reviewed-by: Adam Mills <adamjmills@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Contents of the EDID are passed by a reference to an array
of length 0x80, for which the macro 'PTN_EDID_LEN' has already
been around.
This patch makes use of this macro within the driver and mainboard
implementation utilizing it.
BUG=none
TEST=A successful build of mc_apl{1,4,5,7} and mc_ehl3 mainboards.
Change-Id: If7d254aaf45d717133bb426bd08f8f9fe5c05962
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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This is regarding issues observed on multiple Brya and Nissa
variant such as Skolas and Nivviks. Issue is that once coreboot
sets GPE_EN bit for the GPIO pin and locks it, kernel is not able
to change the control bit. Hence kernel is not able to control the
IRQ on the pin when required.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Ref: commit 38b8bf02d820
("intelblocks: Add function to program GPE_EN before GPIO locking")
This patch skips the locking for GPP_F14 to allow kernel to
configure it later during reboot or shutdown as required.
BUG=b:254064671
BRANCH=None
TEST=Shutdown works on Skolas and Brya board with the patch.
Signed-off-by: Maulik Vaghela <maulikvaghela@google.com>
Change-Id: I7e4a6ac4668028bcd5fa400b9aa8eccf36a79620
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72648
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is an existing issue for skolas boards where board wakes up
from shutdown immediately due to touchpad wake signal.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking")
Later issue was found to be with GPP_F14 configuration for skolas
boards. While shutting down, kernel is not able to disable IRQ for
touchpad due to GPE_EN register getting locked and it is preventing
shutdown of the board.
This patch skips the locking for GPP_F14 to allow kernel to
configure it later.
BUG=b:254064671
BRANCH=None
TEST=Shutdown works on Skolas board with the patch.
Nissa Bug: 234097956
Signed-off-by: Maulik Vaghela <maulikvaghela@google.com>
Change-Id: I09cf1af1f5ab11b06073755374ee8a306984d557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72426
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure the rcomp, dqs and dq tables based on the schematic.
BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I82ca8aa9c3535983d5c506c15dbc69e7be926fa0
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Marx Wang <marx.wang@intel.com>
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This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Omnigul variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
BUG=b:263846075
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I90ae116ccccde48792aeafaa683c7420a95c9886
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After powering on the device, we need to pull USB3_HUB_RST_L up to
enable USB3 Hub.
TEST=boot kernel from USB ok
BUG=b:264841530
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Change-Id: I8df35efb78e90a5b3314840fe2eae81d6e501242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72594
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently there is a problem, where two Displayports are not working. To
be precise: TCP0 and TCP1 (Type-C Port 0/1) are not working.
Setting the lane count of the TCP0 and TCP1 to x1 works fine.
Setting the lane count of the TCP0 and TCP1 to x2 does not work.
Setting the lane count of the TCP0 and TCP1 to x4 does not work.
The reason for that is currently unknown.
This change sets the lane count of the TCP0 and TCP1 Port to x1 length
in the VBT binary.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I182b528275152bf5adcb01a56816afd65674aed3
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72610
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates the print message to start with uppercase, 'board'
to 'Board'.
BUG=b:224325352
BRANCH=None
TEST=Able to observe proper print message when invalid board id is
configured.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ie82df940cbd1eba9c5d485b48648c2bc8f234aae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72638
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow thermal team's request on b/248086651 comment#27. Update the
thermal table setting for each mode and the conditions of temperature
switching.
BUG=b:248086651
TEST=emerge-skyrim coreboot
Change-Id: Ida10d9b10c33dea11440879afda07c04c1eccb9f
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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<gpio.h> chain-include <soc/gpio.h>.
Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Since the PSE GBE0 MAC has been disabled on this board in
commit 343644006f89 ("mb/siemens/mc_ehl3/devicetree.cb:
Remove TSN GbE 0"), therefore disable the corresponding
GPIOs as well.
BUG=none
TEST=Test link detection and IP assignment on the remaining
ports (PSE GBE1 and PCH GBE0) of mc_ehl3.
Change-Id: Ifa055f58894688471d68b9b93fcb994fdcb2a568
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72449
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch adds initial romstage code and spd data for LP5 memory
parts for MTL-RVP. This also configures memory based on the board id.
Memory - x32 LPDDR5
Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B
Board ID -
0b0000 - Empty spd hex file
0b0001 - DDR5 (Empty spd hex file)
0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B)
BUG=b:224325352
TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Change-Id: I15b352eb246aed23da273e56490c7094eae9d176
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Marasov variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
Note: Enabling this config would introduce an additional warm reset
during the cold-reset scenarios due to the function disabling of the
UFS controller as results we are expecting ~300ms higher boot time
(which might not be user visible because `cbmem -t` can't include
impacted boot time due to in-between resets).
BUG=b:264838335
TEST=Able to enter S0ix on Marasov NVMe sku after disabling UFS
during boot path.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie8b8814cdb5e0d97a382cebfe82868ada5762341
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The current CMOS option causes Linux to not boot, as the GRUB EFI
loader will report an incorrect parameter.
Update the CMOS option so that the corresponding UPD is changed when
the wireless is set to disable, so that the root port for the wireless
is also disabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I607d700319d6a58618ec95b3440e695c82dff196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71896
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change the Type-C USB 2.0 interface to a standard port, as the
Type-C macro will not work in Linux (dmesg says the cable is
faulty),
This makes the port work reliably in Linux, tested with:
* Manjaro 21
* Ubuntu 22.04
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6dbf31b6e4603685297e9e5203b0db6ac1b9e24a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72387
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Return generic coreboot error codes from the mb_adjust_cfg
callback used in mainboards instead of '-1' constant and
a driver-specific success-indicating define.
BUG=none
TEST=Boards siemens/mc_apl{1,4,5,7} and siemens/mc_ehl3
build correctly.
Change-Id: I5e0d4e67703db518ed239a845f43047f569b94ec
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Enable early POST code display on this variant using
the common mc_apl1 baseboard functionality.
BUG=none
TEST=Boot on mc_apl5 and observe that POST codes are
displayed before DRAM training.
Change-Id: I390e0ab09ca830637e7a991db77e994d6c358e75
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72386
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CLKREQ Pins are intentionally not configured, because there seems to be
a current Issue with FSP, that causes pci devices to not work if CLKREQ
Pins are configured by coreboot. The msi/ms7d25 mainboard seems to have
a similar issue and the cause is also documented in it's gpio.c file.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iba35076af194de0e85de60ebc93d62fda24e9c24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Change-Id: I5f91ae1b5904405edd797b57fbeb46609301295c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72434
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop the `hyper_threading` CMOS option from most boards, as it's most
likely not working properly and causing problems. The main reasons to
remove the option are:
* The used enum is backwards (0 ---> Enable, 1 ---> Disable)
* Platform/SoC code does not honor the `hyper_threading` option
Also, remove the now-unused enum used by the `hyper_threading` option.
Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69523
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Enable pin 0x18 which is used for the 3.5mm combo jack microphone
detection.
Also, disable 0x17 as it is not used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I05856627c073acaff49ea1ddc048a49a74b6268f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71718
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6a5c54ac46840fc1e03eb15b9ae2ddc34172ec08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72011
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Before, the Intel HDA PCIe device was showing up in the lspci tool, but
Audio wasn't working.
This patch enables the corresponding FSP-M settings to make it work.
Tested on Prodrive Atlas with Themis carrier board on Windows 10 and
Linux 6.1.0-rc3.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I144618c453c1e6a3e759afc7532a4ac4a71814c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Customer needs SaGv to be disabled by default.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8454c267dcc12d2ef7de7bd23296a17294f058a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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The mp2 PCI device is still present when no mp2 firmware is loaded. When
this device isn't explicitly enabled in the mainboard's devicetree, the
chipset devicetree default of the device being disabled is used. This
results in coreboot's resource allocator not allocating resources to the
device and since the bridge doesn't have enough MMIO space reserved, the
Linux kernel can't assign resources to it. To fix this problem, enable
the mp2 device in the mainboard's devicetree so that it gets its
resources assigned by coreboot. An equivalent change was verified on
Chausie.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1076ccacc6f51bf195b8280a6df5ad1849771519
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72196
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The mp2 PCI device is still present when no mp2 firmware is loaded. When
this device isn't explicitly enabled in the mainboard's devicetree, the
chipset devicetree default of the device being disabled is used. This
results in coreboot's resource allocator not allocating resources to the
device and since the bridge doesn't have enough MMIO space reserved, the
Linux kernel can't assign resources to it. To fix this problem, enable
the mp2 device in the mainboard's devicetree so that it gets its
resources assigned by coreboot.
TEST=Fixes the resource allocation for the mp2 PCI device.
dmesg output before the patch:
[ 0.210616] pci 0000:04:00.7: [1022:164a] type 00 class 0x118000
[ 0.210631] pci 0000:04:00.7: reg 0x18: [mem 0x00000000-0x000fffff]
[ 0.210641] pci 0000:04:00.7: reg 0x24: [mem 0x00000000-0x00001fff]
[ 0.210649] pci 0000:04:00.7: enabling Extended Tags
[ 0.240570] pci 0000:04:00.7: BAR 2: no space for [mem size 0x00100000]
[ 0.240572] pci 0000:04:00.7: BAR 2: failed to assign [mem size 0x00100000]
[ 0.240574] pci 0000:04:00.7: BAR 5: assigned [mem 0xd05c6000-0xd05c7fff]
dmesg output after the patch:
[ 0.210483] pci 0000:04:00.7: [1022:164a] type 00 class 0x118000
[ 0.210501] pci 0000:04:00.7: reg 0x18: [mem 0xd0500000-0xd05fffff]
[ 0.210515] pci 0000:04:00.7: reg 0x24: [mem 0xd06c6000-0xd06c7fff]
[ 0.210524] pci 0000:04:00.7: enabling Extended Tags
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I680ef9798f2f0e7e0646f0fd30bef58398b7bf19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72197
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be
able to train memory (DIMM) at different frequencies.
On all latest Intel based platforms SaGv is expected to be enabled
to support dynamic switching of memory operating frequency.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7cf52b966c1355c1f2bd4ae7c256fa4252a90666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Because the EFS is now fixed at 0xff020000, the ChromeOS RO region needs
to be moved to the bottom of the ROM area to cover that space.
The RO Region 6MiB, but you can't actually set 6MiB as RO - it's either
4 or 8MiB, so that's adjusted. To leave some room for the RW_LEGACY
region, the two RW regions are adjusted to 3MiB each, which should be
plenty.
The GBB region had to be moved from the front of the WP_RO region to the
end to avoid conflicting with the EFS, which needs to be inside the
coreboot cbfs area.
Also get rid of AMD_FWM_POSITION_INDEX. The FWM position is no longer
needed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I683155ec0f4e6a62d862b9e2fa76af45f4cd5493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Update the mem_parts_used.txt, generate Makefile.inc and
dram_id.generated.txt for this part.
DRAM Part Name ID to assign
MT62F1G32D2DS-026 WT:B 4 (0100)
K3KL8L80CM-MGCT 4 (0100)
H58G56BK7BX068 4 (0100)
BUG=b:259467147
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I204e871129a1b15d7c373d579e10a7b9ab6deabe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71906
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This reverts commit 197d550d069f918698fa7cd8dda73e09fbfda30c.
Reason for revert: breaks TBT and TypeC display on Brya0
Bug=265375098
Branch=firmware-brya-14505.B
Test=Build and boot Skolas board with Brya0 image. Test TBT
and TypeC display functionality.
Change-Id: Ia0283b023949476e90edff7151d605fa36331bfd
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72081
Reviewed-by: Prashant Malani <pmalani@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Enable early POST code display on this variant using
the common mc_apl1 baseboard functionality.
BUG=none
TEST=Boot on mc_apl6 and observe that POST codes are
displayed before DRAM training.
Change-Id: I2a52c241c383f8ebcf05052e9bc0ba13e63e3728
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
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Move logic previously used only in the mc_apl2 variant to
the mainboard level so that other variants can also make
use of it without code duplication.
This functionality on the mc_apl6 variant will be enabled
in a follow-up patch.
BUG=none
TEST=Boot on siemens/mc_apl2 and observe that the POST
codes are displayed before DRAM training.
Change-Id: I762e328ad06c047d911ce1fc40f12a66cbd14e11
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
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1) Update location of TGP (MAGA) to Params2[15:0]
2) Add TPPA (value of 25W)
Package:
...
Case (0x02)
{
Local0 = Buffer (0x31)
{
0x22, 0x05, 0x10, 0x1C, 0x01
}
CreateWordField (Local0, 0x1D, MAGA)
CreateWordField (Local0, 0x19, TPPA)
CreateDWordField (Local0, 0x15, CEO0)
MAGA = 0x50
TPPA = 0xC8
CEO0 = 0x0200
Return (Local0)
}
...
BUG=b:214581372
TEST=build and verify DSDT on device
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I69b80f4af2ecef6cf91034fc15fb6e8715eeca4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69639
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update setting for touchpad I2C frequency and hold time to meet touchpad
i2c SPEC.
- Frequency: 380 ~ 400 kHz
- hold time : 0.3 ~ 0.9 us
BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies: I2C0 (Touchpad): 393.7 kHz
Hold time = 0.604 us
Change-Id: Iecf4960a12aa56ac307fb9022e47c4e94a2551c1
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72114
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
With the addition of the mc_ehl3 board variant, a few
points about commenting the code arose either from the
review or during the implementation itself.
This patch unifies structure of these files, which
have a similar structure across more Siemens boards
utilizing the PTN3460 eDP-to-LVDS bridge.
BUG=none
TEST=Check that images for the affected boards can be
built.
Change-Id: I59820362e1f87e296c5548b9c3cecba4d2710fe7
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72068
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This board contains in addition to its base variant, mc_ehl2,
an LCD panel driven through the PTN3460 eDP-to-LVDS bridge.
This patch enables the PTN3460 support by adding the device to
devicetree.cb and board-specific configuration parameters in
lcd_panel.c, based upon a similar implementation in siemens/mc_apl7.
BUG=none
TEST=Boot with the LCD panel attached and observe whether
the picture is stable and free of artifacts coming from wrong
resolution, timing etc.
Change-Id: Ib8a1a6f47053406e42554c2dd33684165d54be08
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
1. Enable multiple GPIOs to support the touch panel.
2. Add I2C setting for touch panel.
BUG=b:260818082, b:264812909
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot
Change-Id: I2b805d1960f8b4e3e27f1af02f9c4d31f973288f
Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Change-Id: I7bd29bab2c77da2ffe86167d54e87c9941355ea7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
The {read,write}{16,32}() functions used in this file come from the
mmio.h header, so include it directly.
BUG=none
TEST=Read out the SD card controller (device 1a.1) PCI registers
in Linux and check whether the values reflect the ones defined
in this file.
Change-Id: Iff7b55ef2bf98371b7d7d9114ccf3ebed64772a2
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72009
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to
control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
This new option is hooked with `SkipMbpHob` UPD and is always
disabled for ChromeOS platforms.
This made skip_mbp_hob SOC chip config variable redundant
which is also removed as part of this change.
BUG=none
TEST=Build and boot to Google/Rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Turn on the dxio_tx_vboost_enable for frostflow in coreboot.
It needs to confirm the PCIe Signal Integrity after enabled.
BUG=b:259007881, b:248221908
BRANCH=none
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iaac331737c83ac7a4a1261c32151359e126a009e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Intel Ice Lake is unmaintained and the only user of this platform ever
was the Intel CRB (Customer Reference Board). As it looks like, it was
never ready for production as only engineering sample CPUIDs are
supported.
As announced in the 4.19 release notes, remove support for Intel
Icelake code and move any maintenance on the 4.19 branch.
This affects the following components and their related code:
* Intel Ice Lake SoC
* Intel Ice Lake CRB mainboard
* Documentation
Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Turn on the dxio_tx_vboost_enable for markarth in coreboot.
It needs to confirm the PCIe Signal Integrity after enabled.
BUG=b:263534907, b:263216451
BRANCH=none
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I0798c1d9788e1911c2643bf387722b072aa79045
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
|
|
Change MAINBOARD_PART_NUMBER Kconfig value for mc_ehl3
from "MC_EHL3" to "MC EHL3".
Change-Id: Ie548607c5fb62faaed4921af714bc9b912e558a8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71775
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Wlan power enable pin is changed from EN_PP3300_WLAN to SLP_SUS_L.
Remove unused RTD3 driver.
BUG=b:263448873
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I22448a8cb28ddadb93b114c096e364980feab6fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71693
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Skyrim doesn't use the firmware TPM, so remove the binary from the
image.
Note that because this was not used, removing it doesn't change the boot
time.
BUG=None
TEST=Boot
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia627b128c3346a2556c5306de7506519d1f2d70c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
Winterhold runs with the SPI fast read speed set to 100MHz. This
decreases boot time by roughly 100ms.
BUG=None
TEST=Examine boot times.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I879e17fb0212910c7f90ba0e78ee16bea8b7cffa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
This change skips the MBP HOB creation since coreboot doesn't
use it and also helps to reduce the boot time by ~10msec.
Boot time data:
Before:
* 955:returning from FspSiliconInit 897,278 (33,603)
After:
* 955:returning from FspSiliconInit 864,543 (21,273)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia97cca560869fcfd55e65c2e1719cceec6f3ab7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71873
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace old style declaration "const static" with "static const".
This to enable "Wold-style-declaration" command option.
Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4a3f871f2418438ef8e780a39935dfa2f86d8dbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71895
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
The newer AMD SoCs define ACPI_SCI_IRQ in the SoC's acpi.h header file
and use this definition in the mainboard code, so port this back to
Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib569747aa388d7953e79de747905fb52c2a05e74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
This reverts commit 0e945a3426782e3c054a920ff8be3cd865f697ba.
Reason for revert: Breaks build. Need to be merged after https://review.coreboot.org/c/coreboot/+/71715 which adds the
register that this patch enables
Signed-off-by: Martin L Roth <gaumless@gmail.com>
Change-Id: I0ac3fb1a44e23e19c9711287f3a6a8402a6ffd79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71283
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id53c9a6495d584c374e89b76d1fd4258654b6f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
|
|
The Bostentech mainboard appears out of order - this can be fixed either
by renaming the mainboard to start with S, or by the simpler method
used here by putting the mainboard directory name as the main name, then
noting that the full name is "Shenzhen Bostrontium Teng Technology".
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I31b4c663b68cdcde2d175f080f011f2998e56074
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
Update USB port Type-A Port A0 setting.
BUG=b:261650602
TEST=emerge-skyrim coreboot. Ensure that USB-A port is enumerated correctly in the output of lusub command.
Change-Id: I9563f7b141c34b613cf896f1ce92178617a62c93
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71854
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
|
|
Follow hardware design to correct aux setting on USB-C ports to
fix DP monitor can not output data through type-C port 0
USB-C port 0 did not have retimer.
USB-C port 1 have retimer.
USB-C port 0 AUX_DC_P connect to GPP_E22.
USB-C port 0 AUX_DC_N connect to GPP_E23.
BUG=b:263212450
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
DP monitor display normally
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3af7522f7b6477edcd88004ce1d5f86aeebe3393
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71222
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Update settings for touchpad I2C frequency and data hold time.
I2C frequency and data hold time need to meet touchpad spec.
- I2C frequency: 380kHz - 400kHz
- Data hold time: 0.3us - 0.9us
BUG=b:262320419
TEST=On winterhold, touchpad i2c measurement from vendor,
Frequencies: 395 kHz, Data hold time: 0.66 us
Change-Id: I40fa6f9e88656d4ec02a4120f75a2a9413b5abaa
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.
Previously, we flagged as an error any device which set the
'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.'
There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.
BUG=b:265055477
TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only
listed under PRx, not under _CRS.
Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Morthal has been overcome by events.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ice46f4c7400772dbf51eb9d20b61af277daa8513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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If a discoverable device (e.g. a PCI device) does not appear in the
devicetree (typically because it is removable), coreboot enables it
by default. Disable the SATA2 (device for SATA ports 4 and 5, which
is not used in AHCI mode) and Thermal devices on W520 as well. Both
devices were only disabled on the T520.
Tested, this change fixes a long boot time when using MrChromebox's
edk2 payload on the W520, likely related to the following errors:
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 0
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 1
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 2
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 3
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 4
Change-Id: I0b0483aae05fa84d97987a93db634b740f830e18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71857
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per Kendo3-WS schematics, the conventional PCI bridge is not used.
Change-Id: Ic3aa11cc3a3028c31b06ad8f74875db8c5626a89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71856
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<gpio.h> chain-include <soc/gpio.h>.
Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Tested with the following drives:
- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E)
- WD Blue SN580 (WDS500G2B0C)
- WD Green SN350 (WDS240G2G0C)
Test:
- Drive is functional and has no unrecoverable errors on boot
- Drive is functional and has no unrecoverable errors after S0ix
Change-Id: I51492c97c48f760d4aa9e4a2b2e57b0f1a06d090
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Tested with the following drives:
- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E)
- WD Blue SN580 (WDS500G2B0C)
- WD Green SN350 (WDS240G2G0C)
Test:
- System still asserts `SLP_S0#` during suspend (power LED blinks)
- `slp_s0_residency_usec` still increases after suspend
Change-Id: I919d75cb2a88c0d623c46e44c506ec2d85567995
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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The DDR5 board is almost identical to the DDR4 one. The only major
difference is the board's DDR5 memory design.
TEST=Boot MSI PRO Z690-A board successfully to Ubuntu 22.04. Memory:
Crucial CT8G48C40U5.M4A1 in all 4 slots.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I652a879d1616df4708fe4690797ad98384897f53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Configure GPIOs based from EE.
BUG=b:263060849
BRANCH=None
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I5cfaa8fce6df7f09b744fb3e0b7b1d5b6acdc79b
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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Fix:
cc1: error: src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I5fee0053ab0281b713c33dbc5862c1d4587e854e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Fix:
cc1: error: src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/include: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I1c6f6d99cfb3bc08966d662282c023e22e111f90
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Update devicetree based on the schematic_20230105.
BUG=b:263534907, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Change-Id: I437425ac4a7cdb883dc213f5f6bb5f8a33a5577b
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71714
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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Now that the next generation of APUs is officially announced, we can
unmask morgana.
The chip formerly known as Morgana is actually Phoenix.
Surprise!
This patch just changes the name across the entire codebase.
Note that the fw.cfg file will stay pointing to the
3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is
updated.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=On-screen text message seen during MRC training on skolas
with a few extra patches
Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b514
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71696
|
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TEST=Able to build and boot Google/Tanik and Skolas to OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a21122dbc324d3a396e8934e21d42f471cdb0bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Enable the real-time tuning to improve performance in the real-time
environment for this mainboard.
Change-Id: I91ad7ca58add92b5cc66148aff8378890ee217eb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71234
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We will use BOE_TV110C9M_LL0 for geralt proto board, so update the
panel setting.
BUG=none
TEST=emerge-geralt coreboot;
see panel-BOE_TV110C9M_LL0 in coreboot.rom
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I28e9dd87350b55fdc609dd2c562c5a2ad578187c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71786
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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We should keep booting even failed to get the MIPI panel.
BUG=none
TEST=emerge-geralt coreboot;
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I39d9e04e5908f669ae2a1a8ce8858b93cae20654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71785
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update setting for touchpad I2C frequency.
And meet touchpad i2c SPEC (380 ~ 400 kHz).
BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies: I2C0 (Touchpad): 389 kHz
Change-Id: Ie9efd4e597e2701c98064185e5b39a6e256a5f1c
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71772
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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This patch adds OC configuration of USB devices for MTL-RVP
as per MTL-RVP design specification,
USB 2.0
usb2_ports0 -> OC0
usb2_ports1 -> OC0
usb2_ports2 -> OC0
usb2_ports3 -> OC0
usb2_ports4 -> OC0
usb2_ports5 -> OC0
usb2_ports6 -> OC_SKIP
usb2_ports7 -> OC_SKIP
usb2_ports8 -> OC_SKIP
usb2_ports9 -> OC_SKIP
USB 3.2 Gen 2x1
usb3_ports0 -> OC0
usb3_ports1 -> OC0
TCPx
tcss_ports0 -> OC0
tcss_ports1 -> OC0
tcss_ports2 -> OC0
tcss_ports3 -> OC0
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to chromeOS
(on top of CB: 66190).
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: If1a0c31b7bf0f3fc06f039ad76b0cdd41f7cdd90
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:263920313
TEST=Boot to OS on craask eMMC and NVMe SKUs with both unprovisioned
fw_config and fw_config set correctly.
Change-Id: I4167ee4d00b9ae8fe074c6f5e7a2d5a7382bfe6d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:251055188
TEST=Boot to OS on yaviks eMMC and UFS SKUs with both unprovisioned
fw_config and fw_config set correctly.
On UFS SKU with fw_config set, eMMC no longer shows up in lspci.
(On eMMC SKU, UFS and ISH were already disabled by the coreboot PCI scan
so there's no change in behaviour.)
Change-Id: I31402cb49cffefd98b6fed971f249528448b1d0d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) Samsung K3KL8L80CM-MGCT
2) Hynix H58G56BK7BX068
3) Micron MT62F1G32D2DS-026 WT:B
4) Micron MT62F512M32D2DR-031 WT:B
BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I699070596a77c975254660a1ba74b0f40026186d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch adds initial romstage code and spd data for DDR5 memory
parts for MTL-RVP. This also configures memory based on the board id.
Memory - x32 DDR5 SBS SODIMM 1DPC
Vendor/Model - SK-Hynix/HMCG66MEBSA092N
BUG=b:224325352
TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.
BUG=b:260934724, b:255447299
BRANCH=dedede
TEST=build
Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc
Signed-off-by: Liam Flaherty <liamflaherty@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71710
Reviewed-by: Adam Mills <adamjmills@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add the first version DPTF parameters.
BUG=b:264217345
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I55a3066ef61ce461f40b425a6549d083c29256e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71634
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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|
When AP boots up after Cr50 firmware update and reboot, AP finds
that Cr50 reset is required for Cr50 to pick the new firmware so
it trigger Cr50 reset and power off the system, AP expects system
will power on automatically after Cr50 reset. However this is not
the case for Chromebox, Chromebox EC set AP_IDLE flag when system
is shutting down, when AP_IDLE flag is set in EC, the system stays
at S5/G3 and wait for power button presssend. It cause an issue in
factory that the operator needs to press power button to power on
the DUT after Cr50 firmware update.
This patch sends EC command to direct EC to clear AP_IDLE flag
after AP shutdown so AP can boot up when Cr50 reset.
BUG=b:261119366
BRANCH=firmware-brya-14505.B
TEST=DUT boots up after Cr50 firmware update in factory test flow
Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch introduces a new config named `DEFAULT_ADL_NEM` and
allows respective brya variants with Alder Lake ESx samples to
choose NEM over eNEM as eNEM was fuse disabled till ESx.
TEST=The boot flow related to eNEM and NEM behaviour remains the
same with and without this patch.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibbd492a3d210739120c7ad16415cb7912f5b70ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Disable touch panel power for non-touch sku by fw_config TOUCH field.
BUG=b:263452842
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I4736f94481512806377b733b26fdc7290046c555
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71691
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause
issues as the margin is not big enough. Limit SATA speed to Gen 2 to
achieve a more robust SATA connection.
Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.
BUG=b:121309055
TEST=build/boot Windows/linux on multiple dedede variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.
Change-Id: I91e03bd1d96a6b2f0c3813665910133db0d6c308
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: I212533ffdfb05f841e722c130b52c2976272e670
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
For touchscreens on dedede variants, drive the enable GPIO high
starting in romstage, then disable the reset GPIO in ramstage. This will
allow coreboot to detect the presence of i2c touchscreens during ACPI
SSDT generation (implemented in a subsequent commit).
Since the fast majority of dedede variants have a touchscreen option,
and those that do use the same GPIOs for enable/reset, set the GPIOs for
touchscreen operation in the baseboard and then override for the few (3)
variants that do not have a touchscreen.
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: Ib95e23545cc3e8589ddbd9e18cd0533bec9333e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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