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2023-07-04mb/google/nissa/var/joxer: Disable external fivrMark Hsieh
In next phase, joxer will remove external fivr. BUG=b:285477026 TEST=emerge-nissa coreboot and boot to OS, suspend/resume work normally. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I7fd7ad90e1544966170df402243604379f5790db Reviewed-on: https://review.coreboot.org/c/coreboot/+/76187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-03mb/system76/{adl,tgl}: Add FMD filesTim Crawford
Replace `CBFS_SIZE` with FMD files to declare regions and sizes. This will be used to lock BIOS region (except SMMSTORE) on boot. `CBFS_SIZE` was incorrectly set to 10 MiB, so this also corrects the BIOS region size to match the FIT values. Change-Id: I0f068f4d9b376f12b46faa5bb0c6a08e6cb744d8 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76155 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-03mb/system76: Add space for ramtop in CMOS layoutTim Crawford
Fixes building when `USE_OPTION_TABLE` is selected. Change-Id: I4fb017aa549b24eda6b9e0356bc1776d4044c95d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-03mb/system76: Select CBFS SMBIOS hooksTim Crawford
Multiple users have requested to have the DMI values for product UUID and serial number be populated. Enable the drivers so that we may set them when flashing or updating firmware. Change-Id: I710363d9df626d51756a265f0099f26ef28411c2 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-03mb/system76: Select TPM read delay on all boardsTim Crawford
The Infineon chip occasionally fails Startup or Resume. Adding the delay makes it work more reliably. Change-Id: I4a8f98633154888e2167a3d55192b86e13ffcb62 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76095 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/adl: Remove PL4 valuesTim Crawford
System76 EC since system76/ec@99dfbeaec3b8 sets PL4 values through PECI based on AC state for all boards. Remove the static PL4 values from coreboot since they won't be used. Ref: https://github.com/system76/ec/pull/353 Change-Id: I66bc547ef1b3419fc677fcbdd5ba5d8cc8e14189 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75333 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/rpl: Add Oryx Pro 11 as a variantJeremy Soller
The Oryx Pro 11 (oryp11) is a Raptor Lake-H board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots - Both M.2 NVMe SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Change-Id: I0d29e03cdde523a95ae6d174a9948f4c119cca6e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/tgl-u: Enable reporting CPU C10 state over eSPIJeremy Soller
This allows the EC to detect C10 using eSPI instead of a dedicated pin. Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/adl: Add Gazelle 17 as a variantJeremy Soller
The gaze17 comes in 2 variants due to differences in the discrete GPU and network controller used. - NVIDIA RTX 3050, using Realtek Ethernet Controller - NVIDIA RTX 3060, using onboard I219-V Ethernet Controller Tested with a custom TianoCore UefiPayloadPkg payload. Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - M.2 SATA SSD - MicroSD card reader - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S0ix suspend/resume - Booting to Pop!_OS Linux 22.04 with kernel 6.2.6 - Internal flashing with flashrom v1.2-703-g76118a7c10ed Not working: - Discrete/Hybrid graphics: Requires NVIDIA driver - mDP/HDMI displays on 3060 variant: Requires NVIDIA driver - Detection of devices in TBT slot on boot - S3 suspend: MP init eventually fails Not tested: - Thunderbolt devices Change-Id: Ib12ac47e8f34004f72e6234039823530511baea7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/tgl-h: Disable D3coldTim Crawford
Disable D3cold to prevent issues with Thunderbolt not working after S3 suspend. Change-Id: Ib4362783546aa01f0f8f5baaad817ee76be9c39c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-03mb/google/nissa/var/pujjo: Tune SX9324 register for pujjoteen5Leo Chou
Update SX9324 register settings based on tuning value from SEMTECH. BUG=b:279510275 TEST=Check i2c register settings on Pujjoteen5 and confirm P sensor function can work. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Idc9a2dc817e027551e209c0a26eeebad398f710c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75900 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0Jan Samek
It's been decided not to use any of the USB 3.0 ports on this board. This patch disables the remaining USB 3.0 port 0, after the port 1 has already been disabled in commit d0627c7595fe ("mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1"). BUG=none TEST=None of the USB 3.0 ports functional anymore after boot, the USB 2.0 ports continue working. Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75836 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/siemens/mc_apl1: Fix wrong register maskingMario Scheithauer
With the previous instruction the complete register was set to '0'. Correctly, only the bits 23:16 must be masked. Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76177 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-07-03mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0Mario Scheithauer
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. The appropriate value of 0.7 V was determined by using an oscilloscope. Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-03mb/siemens/mc_apl1: Rename macro 'TX_DWORD3' to 'TX_DWORD3_P1'Mario Scheithauer
The offset '0xa8c' for the High Speed I/O Transmit Control Register 3 refers to SATA port 1 only. To make this clear, change the name of the define from 'TX_DWORD3' to 'TX_DWORD3_P1'. Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76174 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-07-03mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 macroMario Scheithauer
A correction of Tx signal from SATA interface is not necessary on these boards currently. Therefore remove the define and the corresponding code on mc_apl5. Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-03mb/google/nissa/var/joxer: support for different WiFi SAR tablesMark Hsieh
Set the WIFI_SAR_ID field in FW_CONFIG to selcet the correct SAR table. BUG=b:285477026 TEST=emerge-nissa coreboot and check the SAR value Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ibea62c77ecad9b2c475452b706779e4cfc6b06d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76144 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/google/nissa/yaviks: Tune eMMC DLL value for boot issueChia-Ling Hou
Resolve boot issue by tuning RX HS50 and HS200. BUG=b:265611305 TEST=Reboot test 2500 times pass Change-Id: I8a2727dc0ce9dc86c6bfb6d85567afee1734db62 Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75812 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
2023-07-03mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:283245785 BRANCH=firmware-grunt-11031.B TEST=Observe kernel ec panic handler run when ec panics Change-Id: I8eeb5c0935d0531c21bcf4cd3d4fd9dc80b54f79 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-07-03mb/google/rex: Set AUX orientation at SoC to follow cable for kb8010Caveh Jalali
This configures the SoC to flip the orientation of the AUX pins to follow the orientation of the cable when using the kb8010 retimer. This is necessary when there is no external retimer/mux or the retimer/mux does not implement the flip. The kb8010 retimer does not support this feature, so let the SoC do the flip. BUG=b:267589112 TEST=verified DP-ALT mode works in both cable orientations on rex with reworked kb8010 DB by flykt@ Change-Id: Iad093e27617b80f8301008deb00b57fb9b3a48ba Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76137 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-03mb/google/kahlee: Enable Secure OSJon Murphy
Secure OS was disabled on Grunt devices since it isn't used. This reduces the attack surface and is meant to mitigate potential security risks. However, this prevents users from using an alternate OS. Enable Secure OS upstream to allows users to use Windows, and ensure that it is still disabled in the chromium repo. BUG=b:287630343 TEST=Builds with Secure OS included. Cq-Depend: chromium:4620881 Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-07-03mb/hp: Add new port for compaq_8300_elite_usdtRiku Viitanen
New port based on autoport. Autoport worked with minor tweaks, but fan speeds went almost immediately to the maximum. They are controlled by the NPCD379 Super I/O which isn't supported by coreboot. But coreboot already has code for NPCD378, which HP Compaq 8200 SFF makes use of. So SuperIO configuration was copied from the 8200 SFF port. It seems to work without any issues in "normal" use. Most importantly, fan speed control seems to work correctly. However this means that some of the SuperIO LDNs may be configured incorrectly. See the comments on Gerrit for more information. The following is tested and is working: * Native raminit with both DIMMs * Libgfxinit textmode and framebuffer on both DisplayPorts and VGA * External USB2 and USB3 ports: they all work * USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports) * Ethernet * Mini-PCIe WLAN * SATA: 2.5" SSD and optical drive bay * Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1 * GRUB (with Libreboot config) * PS/2 keyboard and mouse * S3 suspend and resume, wake using USB keyboard * Headphone output, line out, internal speaker * Wake on LAN * Rebooting * CMOS options & nvramcui Untested: * mSATA slot. The SATA port needs to be enabled on devicetree too, but I'm unable to test due to lack of hardware * Line in, mic input * MXM graphics card * EHCI debug Not working: * Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so maybe it just isn't present * PS/2 keyboard wake from S3 Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74906 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/google/dedede/var/taranza: Add more USB configurationSheng-Liang Pan
- remove usb2_ports[5] since taranza doesn't have PL2303. - add usb2_ports[6] and usb3_ports[1] for Type-A Port A4. BUG=b:288094807, b:278167978 TEST=emerge-dedede coreboot chromeos-bootimage verified all the USB port works Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7b411c21271497ba386143140aa8cfbb17a1a111 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76186 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Enable LAN0Subrata Banik
This patch performs below operations to enable LAN0. - Complete the LAN PEREST power sequencing - Program the SRC_CLKREQ (GPP_D20) with correctly. - Add overridetree.cb entry to configure the LAN0 device. BUG=b:289395519 TEST=Able to boot google/ovis with LAN0 being enabled. Change-Id: I91b0a76395ade4459cf8705c333728a71f95df14 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76213 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Enable LAN1Subrata Banik
This patch performs below operations to enable LAN1. - Add overridetree.cb entry to configure the LAN device. - Complete the LAN1/SD PEREST power sequencing BUG=b:289395519 TEST=Able to boot google/ovis with LAN1 being enabled. Change-Id: Ifb67cb8e6fc03e3ff14b1b3d8382322fd0b3aeff Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76212 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Configure GPP_V12 PADSubrata Banik
This patch configures GPP_V12 aka SOC_SLP_LAN_L properly as per the Ovis schematics dated June'23 to ensure LAN port is not in sleep. BUG=b:289395519 TEST=Able to measure SLP_LAN PIN and confirm it's deasserted. Change-Id: I1fe8715862823149c8a1f05e3e4463a615fbbbce Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76211 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Configure GPP_C10 PADSubrata Banik
This patch configures GPP_C10 aka EN_LAN_RAILS properly as per the Ovis schematics dated June'23 to ensure LAN ports having power. BUG=b:289395519 TEST=Able to measure LAN port power is enabled with this CL. Change-Id: I3f4d611313325dba66905e0c8ef391765a1fe7a7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-30mb/google/dedede/var/taranza: Disable EXT_VRSheng-Liang Pan
The taranza removed the APW8738BQBI and "disable_external_bypass_vr" should be set to "1" to disable. BUG=b:288978340 TEST=emerge-dedede coreboot Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I0a849fbfacba1d200c969c66bb058863d7ab3085 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-30mb/google/rex/var/ovis: Fix mux change as per schematicsSubrata Banik
This patch updates the mux connection to reflect the Ovis schematics dated June to ensure Type-C1 is able to work in DP-ALT mode. BUG=b:289300284 TEST=Able to get display over Type-C1 port. Change-Id: I223eb3a96e6a1b3abb4168fcf59c0df04c1b4498 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76149 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-29mb/google/nissa/var/gothrax: Add GPIO table for gothraxYunlong Jia
Configure GPIOs according to schematics. BUG=b:287563817 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: If852c7a30edb9fb778872414cb15dc3446aebc55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75872 Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-29mb/google/dedede/var/dibbi: Update power limitsChia-Ling Hou
Add ramstage.c in Makefile.inc and update Dibbi power limits in Dibbi ramstage.c. BUG=b:281479111 TEST=emerge-dedede coreboot and check psys and PLx value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75681 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-29mb/google/dedede: Support variant specific power limitsChia-Ling Hou
With newer dedede design, it's required to config corresponding psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kinds of adapter. BUG=b:281479111 TEST=emerge-dedede coreboot and check correct value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: I583c930379233322c41027805369f81d02000ee7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75680 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-06-28mb/google/skyrim/var/winterhold: Set system_configuration to 3 to avoid SMU callJason Glenesk
Update system_configuration to 3 for 15W. Specification "FT6 Infrastructure Roadmap #57316" incorrectly lists system config index of 4 for 15W. Setting to 4 will cause an additional call to the SMU that is not needed and will add boot delay. Both SMU and FSP interpret configs > 3 as 3. BUG=b:267294958 TEST=Confirm extra message "Service Request 0x5F" not in log. Change-Id: Ib12c73f95030625b52e26f86e932ee2aaa6ea522 Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-28mb/google/skyrim/: Set system_configuration to 3 to avoid SMU callJason Glenesk
Update system_configuration to 3 for 15W. Specification "FT6 Infrastructure Roadmap #57316" incorrectly lists system config index of 4 for 15W. Setting to 4 will cause an additional call to the SMU that is not needed and will add boot delay. Both SMU and FSP interpret configs > 3 as 3. BUG=b:267294958 TEST=Confirm extra message "Service Request 0x5F" not in log. Change-Id: I1f3e305c48801b4e499de56d06c0dcd3eeacc626 Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76091 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-06-28mb/google/rex/var/ovis: Enable crashlog and IOE dieJakub Czapiga
BUG=b:262501347 TEST=Boot on Ovis board. Change-Id: I43aac857e3ec7989c9ab5201cd8f24a7c877e76b Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-28mb/google/rex: Avoid boot hang due to missing SOC/IOE SRAM deviceSubrata Banik
The SOC/IOE SRAM device is used to store crash logs. Previously, the crashlog enablement was hardcoded in the baseboard.common module. This commit moves the crashlog enablement logic to the baseboard module, so that it can be enabled or disabled based on the specific baseboard. Additionally, the SOC/IOE SRAM is now enabled by default in the baseboard devicetree.cb file. This prevents the system from hanging if the SOC/IOE SRAM device is not present. BUG=b:262501347 TEST=Able to build and boot google/screebo with this patch. w/o this patch: [ERROR]  SOC SRAM device not found! [ERROR]  IOE SRAM base not valid Change-Id: I02d581e5b62cfa114a3761a9704ad9f24dead8aa Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-28mb/google/rex/var/ovis: Enable SaGvSubrata Banik
This patch enables SaGv with fixed frequency and gears for Ovis. Restrict memory speed to 6400 MTS as per board design. BUG=b:282164577 TEST=Verified the settings on google/ovis using debug FSP logs Change-Id: Ia9703344a8ae9d2ba44a16c62afab820fd8e2177 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76138 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-28mb/emulation: Enhance ROM_SIZEMaximilian Brune
Some payloads tend to need bigger space than what our current defaults allow. Linuxboot is a good example. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I7029ca3360d936b67ff9873fa13cf9cc60445e56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-28mb/google/rex: Set TCC to 90°CSumeet Pawnikar
Set tcc_offset value to 20 in devicetree for Thermal Control Circuit (TCC) activation feature for rex variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: I0567b6240fcb53f38158c381b700169475cf3795 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76110 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-28mb/google/dedede/var/pirika: Add new Codec ALC5650Daniel_Peng
1.Add Codec ALC5650 setings for drivers/i2c/generic 2.Add option value '3' to AUDIO_CODEC_SOURCE for SSFC BUG=b:284060672 BRANCH=master TEST=emerge-dedede coreboot chromeos-ec chromeos-bootimage Confirm the device is existed on system. Change-Id: I39703a950620c90aa3740b7313b7d32cc68eede4 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75918 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
2023-06-28mb/google/hades: Update SD controller from GL9750 to GL9755Eric Lai
Hades uses GL9755 not GL9750. Select the right driver for ASPM. BUG=b:283721798 TEST=check the coreboot log. GL9755: configure ASPM and LTR Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ia5b3b17d76f02d5114af24535f9a1eecc14358a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76118 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-28mb/bytedance: Add 2 SPR sockets server board bd_egsYiwei Tang
Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids Scalable Processor chipset. It's utilising: - 2 SPR sockets - Max 32 DIMMs - 33x CPU PCIe slots - AST2600 for VGA and BMC remote management Test: The board boots to Linux 5.10 with all 192 cores available. All PCIe devices and DIMMS are working. # sudo dmesg --level alert,crit,err,warn [ 46.636896] netlink: 'consul': attribute type 1 has an invalid length. Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Co-authored-by: Jinfeng Li <lijinfeng01@ieisystem.com> Co-authored-by: Long Cao <caolong01@inspur.com> Co-authored-by: Hao Wang <wanghao11@inspur.com> Co-authored-by: Chenyu Lan <lanchenyu@inspur.com> Co-authored-by: Lay Kong <lay.kong@intel.com> Co-authored-by: Kehong Chen <kehong.chen@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Dong Wei <weidong.wd@bytedance.com> Co-authored-by: Chenchen Li <lichenchen.carl@bytedance.com> Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com> Reviewed-by: Haitao Nie <niehaitao@bytedance.com> Reviewed-by: Shijian Ge <geshijian@bytedance.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-06-27mb/google/hades: select DUMP_SMBIOS_TYPE17Eric Lai
Hades uses DDR5 which can't read SPD from coreboot yet. Use smbios dump to print memory information. TEST=check the coreboot log. memory Channel-0-DIMM-0 type is DDR5 memory part number is MTC8C1084S1SC56BG1 memory max speed is 5600 MT/s memory speed is 5200 MT/s memory size is 16384 MiB Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ica44081228a3a1edc36e2110e84686582fbe8f33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-06-26mainboard/google/rex: Enable crashlogPratikkumar Prajapati
Enable crashlog for rex. Select config options SOC_INTEL_CRASHLOG, and SOC_INTEL_IOE_DIE_SUPPORT. Also enable ioe_shared_sram and pmc_shared_sram devices. BUG=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-26mb/google/brya/var/vell: update FW_config to sync config.starShon Wang
We have found inconsistencies in turn of FW_CONFIG settings/definitions, so sync setting to vell config.star BUG=b:282189358 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I676b719ecc711a6f59e76465a3566bf63924d90f Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75913 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-26mb/google/rex: Avoid LPDDR5/x hangSubrata Banik
This patch avoids random hang issue observed after booted to OS on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s. As per Intel doc 769410 the expected work around is to change SAGV point 0 from 2133 G4 to 3200 G4. BUG=b:287170545 TEST=Able to perform 500 power cycles on google/rex without any hang. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I02a9cadc075f396549703d7a008382e76268f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76076 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-26mb/qemu-aarch64: Move probing dram to read_resourcesArthur Heymans
While we are at it: - Don't use _kb version of declaring resources - Use cbmem_top instead of probing for memory again Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iaaee41aec7806287ef1881372ec8ec47a4cd57d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-23soc/intel/jasperlake: Add per-SKU power limitsChia-Ling Hou
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree. BUG=b:281479111 TEST=emerge-dedede coreboot and read correct value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679 Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Super Ni <super.ni@intel.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-06-23mb/google/rex: Configure ISH GPIO's based on FW_CONFIGBernardo Perez Priego
Configures ISH related GPIO's based on FW_CONFIG obtained from CBI. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled, loaded, and functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-23soc/intel/meteorlake: Rename shared SRAM aliasesPratikkumar Prajapati
Rename shared SRAM aliases for IOE and PMC to make them more readable. pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram. pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram. Rename them in SOC code as well as mainboard to make sure the patch builds for the relevant boards. BUG=b:262501347 TEST=Able to build. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I02a8cacc075f396549703d7a008382e76258f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23mb/google/rex: Keep CNVi PCI device enabled for OvisSubrata Banik
The CNVi PCI device is required for the system to boot properly. By ensuring that this device is enabled, we can prevent the below error message from appearing and ensure that the system boots successfully. BUG=b:274421383 TEST=Able to build and boot google/ovis without any error. w/o this patch: [ERROR] CNVi WiFi is enabled without CNVi being enabled [ERROR] CNVi BT is enabled without CNVi being enabled Change-Id: I4dbae14f0cfccf96a33437a0e2fdefb508209354 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-23mb/msi/ms7d25/vboot-rwab.fmd: Add 32KiB HSPHY cache regionMichał Żygowski
Add the HSPHY region required by INCLUDE_HSPHY_IN_FMAP option. It is needed in case CSME/HECI is disabled or not visible to keep the PCIe 5.0 root ports functional. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic4793fc9457f58e914ef3e18cce1294f230462bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68988 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-22mb/qemu/aarch64: Add PCI supportArthur Heymans
Run with "-device pci-bridge,chassis_nr=1" argument to add a bridge and see that it gets found and picked up by the resource allocator. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iad5d87731066a4009d2c4930a01bc15543d9447a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75925 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-22mb/google/brya/acpi: Set polling timing for DL23 and LD23 to 2msTarun Tuli
Reducing the polling time from 16ms to 2ms. Experimentally we have determined that the link state normally takes approximately 3.5ms to update and therefore we were waiting longer than necessary. TEST=build and confirm we are not waiting the extended period. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8fabb5ac46cae5c92d5b6f1dc0641a4d121c61dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76052 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-22mb/google/brya/acpi: Set power down delay to 2ms after PEXVDDTarun Tuli
Reduce the delay between PEXVDD and NVVDD from 3ms to 2ms during power down sequences. The hardware discharge is aggressive enough that we can safely optimize this. BUG=b:288267305 TEST=build and measured delay is acceptable Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I7c65301414044487e50bbbca618c4e602e571cfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/76051 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-22mb/google/brya/acpi: Don't wait for PG in GPU off sequencesTarun Tuli
When powering rails down, there is no value in waiting for the PG signal to de-assert. Instead, shut the rails off as quickly as possible while maintaining a controlled ordering. BUG=b:288266850 TEST=build and measured delays are gone Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: If31691a7d62b72661fcbacb34e90f3a6adec8134 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76050 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-22mb/google/rex: Disable TCSS config for pre-boot displayKapil Porwal
Pre-boot display is not POR for google/rex hence disable the config ENABLE_TCSS_DISPLAY_DETECTION. BUG=b:247670186 TEST=Build and boot to google/rex and make sure that display over TCSS works in the OS Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib55e251a4620c7a375ee2f27763154c39207236e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-22mb/google/nissa/var/joxer: Disable GPIOs for SD card readerTerry Chen
the board won’t have a SD card reader, so disable it. BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Change-Id: I6a55058b453771d264700a1364ef538f831148e4 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-22vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mappingFelix Held
For Phoenix the lane numbers in the DXIO descriptor match the ones in the schematic, so remove the corresponding text and the table from the comment on the fsp_dxio_descriptor struct. Since there's no logical to physical lane number remapping needed for the lanes in the Phoenix DXIO descriptors, drop the 'logical' from the start_logical_lane and end_logical_lane fields in the DXIO descriptor and rename those to start_lane and end_lane. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-21mb/google/rex/var/screebo: set HBR smbus pin as NCSimon Zhou
Since GPP_C03/GPP_04 are floating in HW design, we set HBR smbus pin as NC, in case it prevents ese and cse from entering suspend. BUG=b:283053968 TEST=Verified on screebo non-TBT SKU, suspend and resume works. Change-Id: I401db32f0286de61ce3ab6c61de9528ec76cb51d Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75643 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21mb/intel/adlrvp_rpl: Add initial code for adlrvp_rpl variantHarsha B R
This patch adds the initial code for adlrvp_rpl variant board which includes 1. Add overridetree.cb to corresponding variant directory 2. Update mainboard name in Kconfig and Kconfig.name 3. Add config option to select corresponding overridetree.cb BUG=b:286030718 BRANCH=firmware-brya-14505.B TEST=Able to build with the patch and boot the adlrvp_rpl platform to ChromeOS on Windows SKU. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ifb95ff705189863d23894769ff450f9528e73b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73962 Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-06-21mb/google/rex: Fix PLD for USB type-A portKapil Porwal
USB type-A port with same PLD.token information as USB type-C port, causes conflict while generating ACPI code for the EC CONN device. Use a different PLD.token number for type-A port to fix the issue. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. before patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS01 }, after patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS03 }, Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-21mb/google/rex/var/ovis: Select SOC_INTEL_METEORLAKE_U_HJakub Czapiga
Ovis uses MTL-H. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis TEST=cros build-packages --board ovis chromeos-bootimage Change-Id: I284c72b902490187d0b15e4fc81650af1cfa16d7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75887 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21meteorlake: Rename `SOC_INTEL_METEORLAKE_U_P` as per latest EDSSubrata Banik
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to `SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS version 1.3.1 (doc number: 640228). With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the same package. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-20mb/intel/mtlrvp: disable acpi timer for xtal shutdownSukumar Ghorai
acpi timer needs to be disabled for xtal shutdown, requirement for platform to enter deepest sleep state (s0i2.2). BUG=b:274744845 TEST=Able to boot and verify S0ix is working w/o this cl: > iotools mmio_read32 0xfe0018fc 0x0 > iotools mmio_read32 0xfe4018fc 0x0 w/ this cl: > iotools mmio_read32 0xfe0018fc 0x2 > iotools mmio_read32 0xfe4018fc 0x2 Change-Id: Ib87b7555217b6954fca98f95b86d03016cd9b783 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75898 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-20mb/google/hades: Update typeC usb PLDEric Lai
get_usb_port_references refer the PLD group. If the port assign cross ports like mux[0] use USB3 and mux[1] use USB1, then we need set USB3 to group 1. Update the PLD panel to back as well. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75912 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-20treewide,intel/skylake: Use boolean type for s0ix_enable dt optionFelix Singer
Using the boolean type and the true/false macros give the reader a better understanding about the option. Thus, use the bool type for the attribute and use the macros for assignments. Skylake mainboards which use that option were changed by the following command ran from the root directory. socs="SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" && \ option="s0ix_enable" && \ grep -Er "${socs}" src/mainboard | \ cut -d ':' -f 1 | \ awk -F '[/]' '{print $1"/"$2"/"$3"/"$4}' | \ xargs grep -r "${option}" | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/${option}\".*\=.*\"1\"/${option}\" \= true/g" Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75871 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-06-20mb/google/rex/var/rex0: Configure I2C timing for I2C devicesIvy Jian
Configure I2C0/1/3/4 timing in devicetree to ensure I2C devices meet timing requirement. Note that I2C5 timing will be updated separately when the tuning done BUG=b:280559903 TEST=Build and check I2C devices timing meet spec. | | I2C0-Codec | I2C0-WFC | I2C1 | I2C3 | I2C4 | |-------------|------------|----------|--------|-------|---------| | FSMB(KHz) | 347 | 343.2 | 389.3 | 393.7 | 381.9 | | TLOW(us) | 2.1 | 2.093 | 1.895 | 1.902 | 1.953 | | THIGH(us) | 0.647 | 0.628 | 0.602 | 0.62 | 0.612 | | THD:STA(us) | 0.633 | 0.64 | 0.601 | 0.6 | 0.601 | | TSU:STA(us) | 0.617 | 0.621 | 0.619 | 0.659 | 0.61 | | TSU:STO(us) | 0.656 | 0.647 | 0.667 | 0.727 | 0.634 | | TBUF(us) | 86.15 | >14.088 | >9.833 | >8 | >10.366 | Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I5421e4fe68e856bbe9f19544954a94670c895a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75150 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-20mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3Rui Zhou
Remove rp2 and add rp1/rp3 for screebo BUG=b:286187816 BRANCH=none TEST=emerge-rex coreboot and verify TBT works. Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75832 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19mb/google/nissa/var/joxer: enable ELAN and G2touch touchscreenMark Hsieh
Update overridetree to support ELAN and G2_G7500 touchscreen. BUG=b:285477026 TEST=emerge-nissa coreboot and check touchscreen function Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I236a2815f956929c6cd84c981cb15e9ab0f657b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75762 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableSataSalpSupportMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableSataSalpSupport'. Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for ModPhyIfValueMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableComplianceModeMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableComplianceMode'. Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-19soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrlMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'PmicPmcIpcCtrl'. Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75853 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-18mb/google/rex/variants/ovis: Add display configurationJakub Czapiga
Enable DDI on ports 1 to 4 for Type-C DisplayPort. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I40f967b12b11c10a1a9329bfb42ebec5a8d7738f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75579 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452Caveh Jalali
This configures the SoC to flip the orientation of the AUX pins to follow the orientation of the cable when using the anx7452 retimer. This is necessary when there is no external retimer/mux or the retimer/mux does not implement the flip. The anx7452 retimer does not appear to support this feature, so let the SoC do the flip. BUG=b:267589042,b:281006910 TEST=verified DP-ALT mode works on rex using both cable orientations Change-Id: Ibb9f442d2afd81fb5dde4bca97c15457837f9f4a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75827 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-17mb/google/myst: Update WWAN usb entryEric Lai
USB3 is used for both typeA and WWAN based on different DB. BUG=b:287159026 TEST=change FW config and check typeA and WWAN can work. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I5ad3973a9519350794a661ad00f71c0eb34edfba Reviewed-on: https://review.coreboot.org/c/coreboot/+/75819 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17mb/google/nissa/var/gothrax: Generate RAM IDs for new memory partsYunlong Jia
Add the support RAM parts for gothrax. Here is the ram part number list: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H58G56AK6BX069 1 (0001) K3LKBKB0BM-MGCP 2 (0010) BUG=b:284388714 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ib16846f7b2061ee254db674ac7bac66c9b9f4e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75834 Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-17soc/intel/meteorlake: Update tcss_usb3 aliasEric Lai
TCSS and TBT use the same lane on schematic. Update the port start from 0 to match the Intel schematic. You can better follow the it without convert the port number. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-16mb/google/nissa/var/joxer: Disable storage devices based on fw_configMark Hsieh
- Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this. (it disables all probed devices when fw_config is unprovisioned.). - Removed `bootblock-y += variant.c` from Makefile.inc based on CL:3841120.(The infrastructure for selecting an appropriate firmware image to use the right descriptor is now ready so runtime descriptor updates are no longer necessary.). BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I6920d88dfec86676ff6733146f748e06d4085c49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75743 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-16google/zork: Convert baseboard directory layoutKyösti Mälkki
There are two baseboards within the set of mainboards built here, with baseboard name appended in the filenames. Take the style and variable BASEBOARD_DIR from google/brya, then move and rename the supporting files under separate directories. Change-Id: I2046b6f82519540b8596ce925203bd60d1870c1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74471 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16mb/amd/birman/devicetree_phoenix: update USB PHY settingsFelix Held
Update the initial USB PHY tuning values that were a copy of the ones from the Chausie mainboard to the values used in the Birman UEFI firmware reference implementation. The USB3 PHY tuning values are still the same while some of the USB2 PHY tuning values are different. The last two USB2 PHYs that are used by the USB4 controllers have a different parameter set compared to the other USB2 PHYs. TEST=All USB ports on Birman function as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0ddfa2594d66b21582282ab8509c921a6e81a93f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75823 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16mb/google/myst: Add additional memory configurationsRob Barnes
Add additional ram parts and generate strapping ids. BUG=b:285216975 TEST=Build myst image Change-Id: I2b3b8c9ffcf81bbd2d6ecfad1b612fbf793857c8 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75821 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-15mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPDRen Kuo
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I3797de01629fdb5ace4c610943d88db525da112b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75826 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-06-15mb/google/rex: Enable audio BT offloadRavi Sarawadi
This patch enables BT offload feature on Rex over SSP1. BT mode is selected via FW_CONFIG and corresponding VGPIOs are programmed. BUG=b:275538390 TEST=Verified audio playback using BT speaker/headset in I2S mode on google/rex. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72881 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15mb/google/nissa/var/pujjo: Set GPIO of WWAN_SAR_DETECT to NCLeo Chou
Pujjo does not support GPIO based D-SAR, so set GPP_D15 and GPP_H23 to NC. BUG=b:275264095 TEST=boot on pujjo and no impact WWAN dynamic SAR function Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I4fe40b32a572a8d914e01e5cd7927766ccf17c02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75403 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15mb/google/myst: Add PSP verstage callbacksKarthikeyan Ramasubramanian
Lay the groundwork to prepare for enabling PSP verstage. This change adds PSP verstage callback to enable eSPI, TPM etc. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: Ifc800e8bb27cc4c3fbccc2ab9f51138a7c4b03a6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75585 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-15mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1Jan Samek
It's been decided not to use the USB 3.0 port 1 on this board anymore, so disable it also with the corresponding USB 2.0 lane. BUG=none TEST=USB 3.0 port 1 not functional anymore after boot, while others continue working. Change-Id: I2799e3d9d7232743c9480dd9611d94ed3249f53b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-15{driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version configSubrata Banik
This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config is clear. Any platform would like to fetch the currently running ISH firmware version should select this configuration. TEST=Able to build and boot google/marasov. Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-15mb/google/dedede/var/boxy: Update audio codec HID to use correct ALC5682I-VDKevin Yang
Boxy audio codec chip uses ALC5682I-VD, not ALC5682I-VS. It needs to modify codec HID to "10EC5682" in coreboot to fix audio no output sound issue. BUG=b:286970886 BRANCH=dedede TEST=confirm audio soundcard can be list by command "aplay -l" Change-Id: Icd69a9d757ba817b586a703a17375682db684224 Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-15mb/google/rex: add Elan HID over SPI ASL for Rex0Eran Mitrani
This patch enables adding variant specific ASL code TEST=Kernel driver is able to communicate with device Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I231482d56dd4afa150766c07cfde105158e5e124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/rex/var/rex0: add HID over SPI ACPI driverEran Mitrani
Add driver to support ELAN touchscreen using SPI for rex * See "HID Over SPI Protocol Specification" section 5.2 - ACPI enum * https://www.microsoft.com/en-us/download/details.aspx?id=103325 BUG=b:278783755 TEST=Kernel driver is able to communicate with device. Also tested S0ix, ran 'suspend_stress_test -c 1' - no issues in suspend/resume. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74885 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAMMatt DeVillier
One specific Hynix LPDDR5x DRAM part requires an ABL workaround to eliminate DRAM-related failures during a FAFT test, but due to the use of generic/common SPDs, there is no way for the ABL to determine the DRAM part # itself. Consequently, we will have coreboot check the DRAM part #, and set/clear a CMOS bit as appropriate, which the ABL will check in order to apply (or not apply) the workaround. The ABL already uses byte 0xD of the extended CMOS ports 72/73 for memory context related toggles, so we will use a spare bit there. BUG=b:270499009, b:281614369, b:286338775 BRANCH=skyrim TEST=run FAFT bios tests on frostflow, markarth, and whiterun without any failures. Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75698 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2023-06-14mb/google/nissa/var/joxer: Add DmaProperty for ISHMark Hsieh
On nissa, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on joxer. BUG=b:285477026 TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA-FQ After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I69b00f0281f4493db157783840d9cdcbb138017f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75758 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14mb/google/rex/variants/ovis: Add basic DTTJakub Czapiga
Add default Intel DPTF. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75580 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/rex/variants/ovis: Add USB and TCSS configurationJakub Czapiga
+-------------+----------------+------------+---------------------------------+ | PCH USB 2.0 | Connector Type | OC Mapping | Remarks | +-------------+----------------+------------+---------------------------------+ | 1 | Type-C | OC_0 | Type C port - TCP1 | | 2 | Type-C | OC_0 | Type C port - TCP0 | | 3 | Type-C | OC_0 | Type C port - TCP2 | | 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0| | 7 | Type-A | OC_3 | TAP1 | | 8 | Type-A | OC_3 | TAP2 | | 9 | Type-A | OC_3 | TAP3 | +-------------+----------------+------------+---------------------------------+ +---------------------+-------------------+------------+---------+ | PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks | +---------------------+-------------------+------------+---------+ | 1 | Type-A | OC_3 | TAP0 | | 2 | Type-A | OC_3 | TAP1 | +---------------------+-------------------+------------+---------+ +------+-------------------+------------+-----------------------------+ | TCPx | Connector Details | OC Mapping | Remarks | +------+-------------------+------------+-----------------------------+ | 1 | Type C port 0 | OC_0 | To onboard Type-C connector | | 2 | Type C port 1 | OC_0 | To onboard Type-C connector | | 3 | Type C port 2 | OC_0 | To onboard Type-C connector | +------+-------------------+------------+-----------------------------+ BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/nissa/var/joxer: Remove fw_config probe for storage devicesMark Hsieh
When fw_config is unprovisioned, devicetree will disable all probed devices. However, boot-critical devices such as storage devices need to be enabled. As a temporary workaround while adding devicetree support for this, remove the fw_config probe for storage devices so that all storage devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI scan, but keeping it enabled should have no functional impact, only a possible power impact. BUG=b:285477026 TEST=On joxer eMMC and UFS SKUs, boot to OS and `suspend_stress_test -c 10` Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I834bd81ce636a6f32d50434cbf07b1d572620492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75757 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-13mb/google/myst: Update PCIE_RST_L driveJon Murphy
PCIE_RST_L is attached to a pull down, change the init to NC. BUG=None TEST=Boot to OS Change-Id: I3f7a548a33eb18327139f033d7c0d6a1843f1639 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75700 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-13mb/google/myst: Update PCIe romstage gpiosJon Murphy
Update PCIe GPIOs during rom stage to properly initialize the PCIe devices and allow the NVMe/eMMC to be properly detected. BUG=b:284213391 TEST=Boot to OS Change-Id: I24ad6c1addedb414afade2512b6628022d000a47 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-13mb/google/brya/variants/hades: Set WP signal to GPP_E12Tarun Tuli
Move the WP signal to GPP_E12 from the current GPP_E15 to match the design. BUG=b:285084125 TEST=WP signal reports as we expect Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8772173fcdcabf78b0c7d605cd495ebe04b63242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 04:26:08 +0000