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This port was done via autoport and subsequent manual tweaking.
Thanks to Angel Pons for helping me with the misbehaving ASM1061 ASPM!
The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection via jumper and onboard Power and Reset switches.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- Libgfxinit
- HDMI-Out Port
- both RJ-45 Gigabit LAN Ports
- USB 2.0 Ports
- USB 3.1 Gen1 Ports
- both USB 3.1 Gen1 headers
- HD Audio Jack (audio output)
- all six SATA3 6.0 Gb/s connectors by Intel
- all four SATA3 6.0 Gb/s connectors by ASMedia ASM1061
- all three PCI Express 3.0 x16 slots
- PCI Express 2.0 x1 slot
- half mini-PCI Express slot
Working (board-specific)
- Power Switch with LED (functional, yet no LED)
- Reset Switch with LED (functional, yet no LED)
- BIOS Selection via jumper
not (yet) tested:
- IR header
- COM Port header
- DisplayPort
- eSATA connector
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- PCI slots
not (yet) working:
- Front panel audio connector
- Software fan control: While the Nuvoton chip is correctly discovered,
the numbering of the fan connectors is faulty, resulting in the wrong
fan being controlled.
- Dr. Debug: on vendor firmware, the LEDs turn off after successful
boot. On coreboot, the LED shows two bright zeros after boot.
Change-Id: Iae0b73d8e81be90ec3a2d5463df3ed170f603266
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Use FW_CONFIG to differentiate MAX98390 and TAS2563. Since config
GERALT_USE_MAX98390 is no longer needed after using FW_CONFIG,
we remove GERALT_USE_MAX98390 from Kconfig.
BUG=b:345629159
BRANCH=none
TEST=emerge-GERALT coreboot
TEST=Verify beep function through deploy in depthcharge successfully.
Change-Id: Ie9f0cbc30dd950b85581fc1924fa351efe1e0aab
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Add RAM ID for
K3KL9L90CM-MGCT 0 (0000)
BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST=Run part_id_gen tool without any errors
Change-Id: Icb84838a6964b9318ded0573ad58a4fd1221867f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83300
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Before:
I2C0 - 401kHz
I2C4 - 405kHz
After:
I2C0 - 392kHz
I2C4 - 395kHz
HW: Change R8409/R8411 to 33ohm.
BUG=b:349743464,b:349735055
TEST=emerge-brox sys-boot/coreboot
Test pass by EE
Change-Id: I985837b1b80e973f148529b446905580c0f95e98
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83290
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
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Working:
- Both DIMM slots
- All Rear USB 2.0 ports
- Integrated graphics (libgfxinit)
- Realtek RTL8111F GbE
- Flashing internally with flashrom (Note: Works from stock too
due to Gigabyte not following Intel recommendations,
confusing ME)
- SeaBIOS (1.16.3) to boot Arch Linux Installer
- EDK II (uefipayload_202309, MrChromebox) to boot Arch Linux Installer
- Audio output (green jack, rear)
- S3 suspend/resume
- VBT
Untested for now (i.e. should work, will eventually test):
- EHCI debug
- Front USB 2.0 ports
- The other audio jacks
- PCIe ports
- Non-Linux OSes
Untestable (i.e. cannot test due to unavailable hardware):
- PS/2 port
- Serial port
- SATA ports
Not working:
- USB 3.0 ports: The on-board VLI VL805 does not have a flash chip,
so its firmware needs to be loaded on each boot. However,
documentation about the (chip-specific) firmware loading procedure
is nowhere to be found.
- Super I/O automatic fan control: not yet implemented in coreboot.
To control fans, use software fan control methods in the meantime.
Change-Id: I106c195c890823f07227739c6b30133b996f6510
Signed-off-by: PugzAreCute <me@pugzarecute.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83267
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I3cb1f11beba61afdf2be6188bde9ff135f8ace50
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This port was done via autoport and subsequent manual tweaking.
Special thanks to Nicholas Chin! This port would have never succeeded
without his help.
The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection switch and onboard Power and Reset switches.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- Libgfxinit
- HDMI-Out Port
- USB 2.0 Ports
- Vertical Type A USB 2.0
- USB 3.1 Gen1 Ports
- HD Audio Jack (audio output)
- Front panel audio connector (audio output)
- RJ-45 Gigabit LAN Port
- SATA3 6.0 Gb/s connectors
- mSATA/mini-PCI Express slot
- half mini-PCI Express slot
- PCI Express 3.0 x16 slots (both)
- PCI Express 2.0 x4 slot
- PCI Express 2.0 x1 slot
Working (board-specific)
- Power Switch with LED (functional, yet no LED)
- Reset Switch with LED (functional, yet no LED)
- BIOS Selection Switch
- Slow Mode Switch (locks the CPU at 800MHz)
not (yet) tested:
- IR header
- COM Port header
- Power LED header
- eSATA connector
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- Optical SPDIF Out Port
not (yet) working:
- Software fan control: While the Nuvoton chip is correctly discovered,
the numbering of the fan connectors is faulty, resulting in the wrong
fan being controlled.
- Dr. Debug: on vendor firmware, the LEDs turn off after successful
boot. On coreboot, the LED shows two bright zeros after boot.
- Post Status Checker (PSC)
Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Add LCE_LMFBX101117480 MIPI panel for Wugtrio.
Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf
BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage
BRANCH=corsola
Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Configuring USB2_PORT_EMPTY is equal to just not setting it. So remove
it to clean up a bit.
Change-Id: I6854f4a0d3e7b51b242549556a5838d4183d3473
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I1992c20dcdc5e974143690d44ee199d7c3394cfd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Configuring them to 0 is equal to not configuring them at all. So remove
them to clean up a bit.
Change-Id: I9a9eb370e8e9e8874ad8b4b8ac0f43d61c1a4b9b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Configuring them to 0 is equal to not configuring them at all. So remove
them to clean up a bit.
Change-Id: I18134ac784fffb703e1fe513e5914f05faa749c9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83248
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also, remove superfluous comments from devices which repeat their name.
Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I8ce94c8bc7ed137eaace12d6cb0befa6c0d39a37
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82925
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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When CNVi based Wifi6 is disabled, CNVi based Bluetooth must be turned
off, based on fw_config. Otherwise, when device boots without the cbi
settings for wifi6, boot may fail with assertion error for line 817 &
819 of file 'src/soc/intel/alderlake/fsp_params.c'.
BUG=b:345596420
BRANCH=NONE
TEST=Dut boots fine with both Wifi6 & Wifi7 based cbi settings, along
with enumeration of corresponding BT device.
Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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PCIe based GPIOs of Wifi7 module are enabled based on firmware config.
BUG=b:345596420
BRANCH=NONE
TEST= Based on fw config configured, wifi6 or wifi7 along with
bluetooth ports are detected.
Change-Id: If0584e91b5143c6df742961657d242c046409b3a
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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PCIe based Bluetooth is on port8. This cl enables bluetooth for PCIe
based Wifi7 module.
BUG=b:345596420
BRANCH=NONE
TEST=With proper FW config enabled, BT gets detected on port8
Change-Id: I989cf6122f2555cc89f622e4ce5d21b574d0458e
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83076
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable pcie based, discreete wifi7 on root port4.
BUG=b:345596420
BRANCH=NONE
TEST=Verified Wifi7 module detection based on cbi settings
Change-Id: I8c2f4a750a1cb00c587bce21bc83ee583d0f4341
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83075
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new fw config field for wifi category as WIFI_6, which is CNVi
based and WIFI_7, which is PCIe based. Also, enable WIFI_6 for existing
CNVi based wifi port as well as bluetooth port.
BUG=b:345596420
BRANCH=NONE
TEST=Verified Wifi6 module detection
Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83074
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add wake configuration and set 'add_acpi_dma_property'=true for CNVi.
Also, add "set 'add_acpi_dma_property' to true to tell the OS to enforce DMA protection for this device.
BUG=b:345596420
BRANCH=NONE
TEST=SSDT dump showed below:
Scope (\_SB.PCI0.RP01.WF00)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x23,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
Change-Id: If04539fe8dceb5c2edfc06a324ede11147b78b6d
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83138
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures Serial IO UARTs mode as below.
UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design.
BUG=b:338917836
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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ALC257 does not supoort built-in digtal buzzer, So use external pwm
to PCBEEP for beep sound.
BUG=b:346956771
BRANCH=None
TEST=emerge-brox coreboot sys-boot/chromeos-bootimage
firmware-shell: devbeep -> can output beep normally.
Change-Id: If924f9f27f229420e78015f418a97b2d5daf62e5
Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch adds initial code block required to build google/fatcat
board with Intel Meteor Lake Silicon. Later after the initial board
power-on is successful, we shall switch to Panther Lake silicon to
build the google/fatcat reference design.
BUG=b:347669091
TEST=Able to build the google/fatcat and able to hit power-on reset
using Intel Meteor Lake SoC platform.
Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Follow nissa baseboard setting for storage field.
option STORAGE_EMMC 0
option STORAGE_NVME 1
option STORAGE_UFS 2
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I75b4b3037c245f7d517cb33d487f71da98f6c4e8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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The Fn key on Lotso emits a scancode of 94 (0x5e).
BUG=b:322721490
TEST=Flash Lotso, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I999627f0ea9db1d79376150a04920ac877a48447
Signed-off-by: Wen Zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83204
Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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On board version 1 and later, touchscreen is not stuffed. Hence
configure the relevant GPIOs as not connected, disable the concerned I2C
bus in the devicetree as well as SoC chip config for board version 1.
BUG=b:347333500
TEST=Build Brox BIOS image and boot to OS. Ensure that there are no
peripherals detected in I2C 1 bus through i2cdetect tool. Ensure that no
touchscreen devices are exported through ACPI SSDT table. Ensure that
other I2C peripherals - eg. Trackpad and Ti50 are functional. Ensure
that the device is able to suspend and resume for 25 cycles.
Change-Id: Ia0578b90b0e8158ae28bcc51add637844ba6acf6
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83199
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kernel need the default brightness steps. Otherwise following error
messages are observed in the kernel:
[Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS
ACPI BIOS Error (bug): Could not resolve symbol [^^XBCL], AE_NOT_FOUND
ACPI Error: Aborting method \_SB.PCI0.GFX0.LCD0._BCL due to previous
error (AE_NOT_FOUND)
BUG=b:346807006
TEST=Build Brox BIOS image and boot to OS. Ensure that the concerned
error messages are resolved. Ensure that the backlight controls are
functional.
Change-Id: Icd569b0efef31908edb1b7dc384e60a16fc5bd0c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I50706d7a077767d2295d6d5f209c30109d607277
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
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Update board type to BOARD_TYPE_ULT_ULX
BUG=b:348147663
BRANCH=none
TEST=Built and compare the results of
command 'dmidecode --type 17 | grep Speed'
[Before]
Speed: 8400 MT/s
Configured Memory Speed: 6400 MT/s
[After]
Speed: 8400 MT/s
Configured Memory Speed: 5200 MT/s
Change-Id: I049d7c19424f41e83480f4b80bafd6ef8b9e30f6
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
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Add FW_CONFIG for no port LTE skus, and probe LTE port in devicetree.
BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: I5235df33a36f3b9472ee8b615e4622f6ee3fb1a4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Fill in ec.h according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ie1edf655fd20c0c1baee01fa90ed03501e3fe161
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83154
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fill ec pins in gpio.h and configure GPE0 DW2 in overridetree according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83155
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Set PsysPL2 and PsysPL3 in addition to making adjustments
to PL2 and PL4 in order to prevent brownouts when we don't
have a battery or have an empty battery at boot time.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=flash
Able to successfully boot on a SKU1 with 45W, 60W+ adapters
and SKU2 with a 60W or higher type C adapter.
30W is still being worked on.
Change-Id: Ie36f16b2c938dce29cd2130a86fc8c08f5ba0902
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch creates a new tereid variant, which is a Twin Lake platform.
This variant uses Nereid board mounted with the Twin Lake SOC and
hence the plan is to reuse the existing nereid variant code.
BUG=b:346442939
TEST=Generate the Tereid firmware builds and verify with boot check.
Change-Id: I052c3ba93d00e2df7e205c3127210bacaa956ca0
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83145
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SATA controller is configured to AHCI mode by default. Drop the
setting from the devicetree.
Change-Id: I027b393300e2cbad827e176afddc197007314f10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: I572a9092633c61907794ecbbbe431066d889c5fb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Icdf58a85bbde0dcb4e555df68cd20eade241dde3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83176
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83174
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Configure GPP_R2 as input, no pull according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ic678b77e5489f56d8ff92b265a6ca5852c0f7e8d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I0b49ff8b6275fdde326c79ec21c34faa03094f9e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
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Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I990d74d9fff06b17ec8a6ee962955e4b0df8b907
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77970
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory part in mem_parts_used.txt, then generate.
H54G56CYRBX247
BUG=b:199645942
TEST=run part_id_gen to generate SPD id
Change-Id: I2169d71695d8d133d26cafe5c7be33b976dd8603
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83127
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure TSEG size by reading CONFIG_SMM_TSEG_SIZE in romstage.
The remaining Qemu code can already handle the bigger TSEG region.
TEST: Increased TSEG to 8MiB.
Change-Id: I1ae5ac93ecca83ae9c319c666aac844bbd5b259f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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According to the vendor spec, I2C1 hold time needs > 100ns.
System needs to adjust the I2C1 sda_hold value from 7 to 13,
the system will change the I2C1 hold time from 70ns to 126ns.
BUG=b:347157276
TEST=built bootleg and verified test result by EE team
Change-Id: I722ec93177b6debf6b4c99de2df68c942560a3ff
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83080
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Lotso's WIFI_BT is same design as brox, copy from brox.
BUG=b:339612353
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I030e306dc5d9d3fcb6314bc491dbf5c9ae60bcb7
Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83126
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
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Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings.
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: Ic9a7a9062f5c6e45c5bd9617f3b2a0634b8dc1db
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83051
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update verb table provided by Realtek on 20240614.
BUG=b:344471736
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Device list:
cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name
ALC257
cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name
Realtek
Headphone detection:
Event: time 1718633617.056092, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1
Event: time 1718633621.471708, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0
Event: time 1718633623.898046, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1
Event: time 1718633625.743663, type 1 (EV_KEY), code 115
(KEY_VOLUMEUP), value 1
Event: time 1718633625.743678, type 1 (EV_KEY), code 115
(KEY_VOLUMEUP), value 0
Change-Id: Idde8963de9302849f87b7c262f17d9c9d99b46dc
Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83109
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Disable LTE, stylus and WFC related GPIOs based on fw_config.
BUG=b:337169542
TEST=Local build successfully.
Change-Id: I91adc4e70d0d23b737d4fa6725cd96e63108f874
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test.
BUG=b:328147465
TEST=Build and check S0ix function and verify FAFT sleep funciton.
Change-Id: I53f704ed11a5c63b5c079c6e60ce2fa32bbd8b1a
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test.
BUG=b:335312655
TEST=Build and check S0ix function and verify FAFT sleep funciton.
Change-Id: I7918e26fe382d4d9992a0e2744a2f8894a070e36
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Adjust settings as recommended by thermal team.
Update DPTF parameters based on b:346930334
BUG=b:346930334
TEST= built bootleg and verified test result by thermal team
Change-Id: I363eaa72b5190212b014fe4e2c2fca10e2a3f408
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83079
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust settings as recommended by thermal team.
Update DPTF parameters based on b:346932306
BUG=b:346932306
TEST= built bootleg and verified test result by thermal team
Change-Id: I6a529365249a5372dd87ef28cb9ea8d540b9cac0
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83078
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This reverts commit 0e0bc618e3ed1888ac140010057dc7485443c3c2.
Reason for revert: Merged out of order, breaks tree
Change-Id: I22bd85a2008db471177257a8b779c06898b1010c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83105
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:337169542
TEST=Local build successfully.
Change-Id: I3d71a35e9c0a33b72720b093b5a05eb69d5bb9f8
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83060
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add initial override devicetree for riven based on
the latest schematic (Riven(ZDK)_MB_Proto_0601.pdf).
1. Add eMMC DLL tuning value (copy from craask)
2. Configure I2C frequency (copy from craask)
3. Add audio codec and speaker amp settings
4. Add Elan touchscreen settings (copy from craask)
5. Add WFC and usb settings (copy from craask)
6 Add Elan and Synaptics touchpad settings (copy from craask)
7. Add WIFI6(CNVI) and WIFI7(PCIE) configuration
8. Add LTE settings (copy from craask)
BUG=b:337169542
TEST=Local build successfully.
Change-Id: I1dda3557edb44dda9c3a1efaf98437352978561c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83059
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Elan touchpad driver in newer linux kernels (>= 5.15) no longer
explicitly configures the touchpad as a wakeup source for devices
not using device tree. It is now assumed this information should be
extracted from ACPI, therefore we need to update drallion's devicetree
so that the device regains its lost capability.
TEST=update drallion FW and verify touchpad can cause wake up from
suspend
Change-Id: Iff21afda144cc11a013cb72816064df1c9eb21ae
Signed-off-by: Angela Czubak <aczubak@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83070
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enables ACPI brightness controls to be generated, and display
brightness controls to be functional under Windows.
TEST=build/boot Win11 on google/brya (craaskin), verify display
brightness controls present and functional.
Change-Id: I821b912cf52b5b89c5c9d831a5a15566b1b31639
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Boards using the brya baseboard already generate ACPI brightness
controls via their use of the gfx/generic driver, but need the
default brightness steps in order for display brightness control
to be functional under Windows.
TEST= build/boot Windows 11 on banshee, verify brightness controls
functional.
Change-Id: I03bb7a7309476839c49d2e862a036d9e89800605
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70372
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Lotso's WIFI_BT is same design as brox, copy from brox.
BUG=b:339612353
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I3946297db7f10a31570f773bdc5665f9f472c9fe
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83053
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Configure GPIOs according to schematic_20240607.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I760a7a234df43db3a557b3be9e20ff7aa5f80b72
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS which intends to achieve a unified AP firmware image across UFS and non-UFS skus.
BUG=b:328580882
TEST=Local build successfully.
Change-Id: Ifcee68a3492ab4606819de0be41701f803151f66
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83061
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I3cb0a39c83d6c92d604f1190538db88d97a81693
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Also, remove superfluous comments from devices which repeat their name.
Change-Id: I26f7d5155f73bcf3cb3872f206c946da5029bda8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Also, remove superfluous comments from devices which repeat their name.
Change-Id: Ia4a9a5c5897fe78a1243e4c42a7d8753cfe039c0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I20aca1a63306b0f39f97fd0b85d61cd957cb2150
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83094
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also, remove superfluous comments from devices which repeat their name.
Change-Id: I00473e44fce9197f818f5a8d131e9be31e8b0f69
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6026498c2853f5951227ace57b7198579f342647
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83092
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As of commit ee12634872 (nb/sandybridge,sb/bd82x6x: Configure USB from
southbridge devicetree) and earlier commits, the USB port configuration
should be located in the devicetree instead of the mainboard_usb_ports
array, typically located in the boards early_init.c.
TEST=USB ports still function; and the USBIRx, USBPDO, USBOCM1, and
USBOCM2 RCBA registers in the inteltool dump did not change between
an E6430 build before and after the sb/intel/bd82x6x that moved the
usb config to the devicetree.
Change-Id: Ia5aa03a5894a8ef29e863470925a223f52e0ab70
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83006
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The components listed in the documentation work in this port.
The MXM structure of the vendor firmware is added, which is
used by the VGA option ROM with int15h functions.
Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Turn off camera power during s0ix to improve power consumption.
BUG=None
BRANCH=brya
TEST=built and verified GPP_A17 went to low during s0ix with a scope.
[Measurement of s0ix power consumption - 1 hour avg]
Before this: 301.4 mW
After this: 299.8 mW
Change-Id: Iae02d06e9f5a5988563b2b7ae36d153aecedb9d7
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83029
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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Trying to probe RAM space to figure out top of memory causes an
exception on RISC-V virtual machines with recent versions of QEMU, but
we temporarily enable exception handlers for that and use it to help
detect if a RAM address is usable or not. However, QEMU docs recommend
reading device information from the device-tree blob it provides us at
the start of RAM.
A previous commit adds a library function to parse device-tree blob that
QEMU provides us. Use it to determine top of memory in RISC-V QEMU
virtual machines, but still fall back to the RAM probing approach as a
last-ditch effort.
Change-Id: I9e4a95f49ad373675939329eef40d7423a4132ab
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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- Physical DP ports are DP2/DP3 (HDMI2/HDMI3 for DP++)
- VGA port is Analog
- DP1 is not connected
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I8ed79167d5445d607acbee491c3382ff2585583f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Add RAM region so that the payload can be placed in there without
coreboot complaining that the payload doesn't target a RAM region.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id07eae3560ce69cd8a6a695702fa0b4463c50855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81909
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enable the fixed boot mode option in the VBT and set it to 1920x1080,
so that drobit boards equipped with 4K screens are legible at boot.
TEST=build/boot drobit w/4K screen using edk2 payload, verify boot
resolution set to 1080p and UEFI menus readable without a magnifying
glass.
Change-Id: If1f9e36d9bbdc2955ba890e2832aa64af9ba8f73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Generate RAM IDs for
K3KL6L60GM-MGCT
H9JCNNNBK3MLYR-N6E
K3KL8L80DM-MGCU
MT62F1G32D2DS-023 WT:C
H58G56BK8BX068
BUG=b:333494257
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: I7a240a263816193b9f3d418385c1673e9d3f89db
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
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Based on lotso EVT schematics update gpio settings.
GSPI0_CS0_L -> NF7
GSPI0_MISO -> NF7
GSPI0_MISO -> NF7
GPP_F18 -> EDGE_SINGLE
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I12d84538566c4d51fe346eb5609e55d91ddafbea
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
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Pujjoga support EM060 WWAN, use wwan_power.asl to handle the
power off sequence.
BUG=b:346479638
TEST=Build and boot on pujjoga
Change-Id: I1273d09385c661835d741691b3c4af26e72a9f86
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83042
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, the P sensor does not work.
So add SX9324 registers settings based on tuning value from SEMTECH.
BUG=b:340749850
TEST=Check i2c register settings on Pujjoga and
confirm P sensor function can work by kernel 6.6 driver.
Change-Id: I205c1f5228d792afc763a06f74a8744918e2da75
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82689
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add AX211 wifi sar table for sundance wifi sar config.
Use fw_config to separate different wifi card settings.
WIFI_SAR_TABLE_AX211: 0
BUG=b:332978681
Test=emerge-nissa coreboot
Change-Id: Ide84996da567e4f866a2a1309a6976ed8df635a6
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83044
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add FW_CONFIG probe based on sundance boxster of below devices:
WWAN
Schematic version: NEC_SHIKIBU_ADL_N_MB_EVT_20240330
BUG=b:332978681
TEST=Boot to OS and verify the WWAN devices is set based on
fw_config.
Change-Id: I14339201d8ee21c85fefa96a49323e0c25cb8eca
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83041
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned.
BUG=b:345112878
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I1e5e49c1baa8d2b00134c26cc3b69aa15712b512
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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We use ALC256 as HDA codec on orisa. Add verb table and the
related device tree changes for HDA related registers.
BUG=b:338523452
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I92051886341bd317cce6061ece83439d156b0f90
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add override devicetree based on schematic_20240607.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Id3ceff41fdb8e4a57bd6dab6247b622a5d13587d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This commit adds the VBIOS table, extracted from Linux sysfs running on
the stock firmware version 8.02, to the coreboot tree, required for
some graphics backends.
Change-Id: I0d1c9795741e112154bfe6885eea744538373d5a
Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82460
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This commit defines the panel_cfg register for the Razer Blade Stealth
(Kaby Lake). This enables libgfxinit support. These values are derived
from the stock firmware. First, VBIOSes were extracted from the stock
firmware. Then, intelvbtool was used to extract the VBT from each of the
VBIOS tables. Finally, intel_vbt_decode from igt-gpu-tools was used to
extract the register values. Although there were multiple VBIOSes
present in the firmware, all VBIOSes across both firmwares (on version
1.50 for the H2U and 8.02 for the H3Q) had the same register values.
Change-Id: I4c8b26ffb7a70d08655986084a714206d9d0c96a
Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82458
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Icb9e72edf3a982a095dceee4da19f90c53fcddd0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Fill in memory config based on the the schematic_20240607.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I1456f7385e092b606fc0a35b25f3454600af8b23
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82662
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refer to the reference board of nivviks, and update GPIO settings
based on latest schematic (Riven(ZDK)_MB_Proto_0601.pdf).
BUG=b:337169542
TEST=Local build successfully.
Change-Id: Ic43c743fcc2ec89b5a9e2fbe1a87b833d59f1e74
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82973
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The H110M does not use memory down, and the spd directory doesn't exist
in the board's directory in the first place. This was probably just copy
and paste leftover from some existing Skylake board in the initial port.
TEST=Timeless build does not change.
Change-Id: I35744310b2bf8a14165dae9808c982e6dc274a74
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83010
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add coreboot support for qemu's sbsa-ref (Server Base System
Architecture) machine (-m sbsa-ref).
The qemu-sbsa coreboot port runs on EL2 and is the payload of the
EL3 firmware (Arm Trusted Firmware).
Note that, coreboot expects a pointer to the FDT in x0. Make sure
to configure TF-A to handoff the FDT pointer.
Example qemu commandline:
qemu-system-aarch64 -nographic -m 2048 -M sbsa-ref \
-pflash <path/to/TFA.fd> \
-pflash <path/to/coreboot.rom>
The Documentation can be found here:
Documentation/mainboard/emulation/qemu-sbsa.md
Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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