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2024-08-09mb/google/fatcat: Generate LP5 RAM ID for `H58G56BK7BX068`Subrata Banik
Add the support LP5 RAM parts for fatcat: DRAM Part Name ID to assign H58G56BK7BX068 0 (0000) BUG=b:347669091 TEST=emerge-fatcat coreboot Change-Id: Idcdbbcd42dc6b1c8b13a89b1ace5b2973dde6d2b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83824 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2024-08-09mb/google/brya: Enable storing ISH FW version for truloSubrata Banik
This change enables storing the ISH firmware version on the Trulo baseboard by selecting the `SOC_INTEL_STORE_ISH_FW_VERSION` config option. BUG=b:354607924 TEST=Able to dump ISH version on trulo. > cbmem -c | grep ISH [DEBUG] ISH version: 5.4.2.7780 Change-Id: I69a7fa19c53f435ef1f6306b259f703c7b196137 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83820 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-08mb/google/dedede/var/awasuki: Add Fn key scancodeWeimin Wu
The Fn key on awasuki emits a scancode of 94 (0x5e). BUG=b:355538142 TEST=Flash awasuki, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Ic7aa183bf314fed4901133dc70d848d84fab0784 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-08mb/google/dedede/var/awasuki: Enable ELAN touchscreen with fw_configWeimin Wu
1. Change driver form i2c/hid to i2c/generic. 2. Add fw_config for touchscreen. BUG=b:351968527 TEST=ectool cbi set 6 0x0x10200a0; touchscreen functions normally; Change-Id: Ifd6330be8924d4873f0efab3ce404168a62099eb Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83704 Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-08mb/google/brya/var/trulo: Update ISH GPIO's configurationVarun Upadhyay
This patch configures the GPIO pins to enable ISH on the Trulo device, in accordance with schematic_20240607. BUG=b:354607924 TEST=Builds successfully for google/trulo. Change-Id: I3af478762e0a0aa35a2698e0ed87a4d8c24362f0 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83781 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-08mb/google/brya/var/orisa: Update ISH GPIO's configurationVarun Upadhyay
This patch configures the GPIO pins to enable ISH on the Orisa device, in accordance with schematic_20240607. BUG=b:354607924 TEST=Builds successfully for google/orisa. Change-Id: I24745ba629c59c092ce676b29915e356a4d8d8af Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83656 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-08-07mb/google/brox: Tune Touchpad I2C parametersKarthikeyan Ramasubramanian
Adjust Touchpad I2C fall time configuration such that it meets the I2C fast mode specification(<= 400KHz). BUG=b:328670295 TEST=Build Brox firmware and boot to OS. Confirm the I2C bus frequency(375 KHz), rise(650 ns) and fall(330 ns) times meet the specification. Change-Id: I0006bfb9bb5839ffa1248d9f2ea055160ed0936e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83755 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2024-08-07mb/starlabs/starlite_adl: Remove has_cdm from devicetreeSean Rhodes
The property `has_cdm` only existed in an early patchset, the version that was merged only requires `cdm_index` so remove the former that was added in c6c75dfbaeff208c17bb47fdede855286e12d857. Change-Id: I62a9456e9a4f1571328ba6fd09ae383a8fd11767 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83796 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-07mb/apple/macbookair4_2/dt: Move iGPU settings into igd device scopeFelix Singer
Change-Id: I3161c7d99a2d94d6c85a6c9652b8e78d3f447252 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-07mb/apple/macbookair4_2: Clean up devicetreeFelix Singer
Clean up the devicetree by removing settings set to 0, which are initialized with 0 anyway, remove superfluous disabled devices and also remove comments duplicating the device alias names. Change-Id: I07005ae1db7d92fd50e72351031a5eb491768d3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83782 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06mb/starlabs/starbook/rpl: Nit GPIO changesSean Rhodes
Remove some unused GPIOs and configurations for GPIO's that aren't even connected. Change-Id: I5b4691a0b5e8b1348304d11c1d59aa60517041ec Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83626 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06mb/starlabs/starbook/rpl: Disconnect wireless GPIOsSean Rhodes
The GPIOs for WiFi and Bluetooth are also connected to the EC. They are controlled from there so remove the configuration here. Change-Id: I7aef1b821420daf5ea9f6ae107021e5d406a5ec3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-06mb/starlabs/starbook/rpl: Disconnect SCI/SMI GPIOsSean Rhodes
The platform uses eSPI so these are not needed. Change-Id: I81470658263f4b601c9964ff5bed86b22d24df3b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83624 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06mb/starlabs/starbook/rpl: Add USB ACPI to devicetreeSean Rhodes
Use the USB ACPI to add entries for the USB and TCSS ports. Change-Id: Iab8b6e03c8c05e459fb354bc008109c873a4846f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83623 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06mb/msi/ms7d25,ms7e06: Enable discrete TPM module supportMichał Żygowski
Now that multiple TPM drivers may be compiled in, it is possible to support switching between fTPM and dTPM. The patch adds: - Device tree entry for PC80 discrete TPM - TPM PIRQ# GPIO active low routed to IOAPIC for TPM interrupt - MEMORY_MAPPED_TPM option to board's Kconfig to enable PC80 TPM driver When the ME is disabled, e.g. via HECI command, chipset will route the TPM traffic to SPI automatically. When a SPI TPM is connected to the JTPM1 on the board, it will be probed successfully and initialized in place of inactive PTT/fTPM. Change-Id: Ie6e7026b6f1cec842bce4ef40b6db7feb75200e3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80456 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-06mb/starlabs/starlite_adl: Add Alder Lake N StarLite Mk VSean Rhodes
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 22.04 * Manjaro 22 No known issues. https://starlabs.systems/pages/starlite-specification Change-Id: I8724e578c21353032b844b20b868348580ff561b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-06mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flashKrystian Hebel
Depending on how firmware image was passed to QEMU, it may behave as: - ROM - memory mapped reads, writes are ignored (FW image mounted with '-bios'); - RAM - memory mapped reads and writes (FW image mounted with e.g. '-device loader'); - flash - memory mapped reads, write and erase possible through commands. Contrary to physical flash devices erase is not required before writing, but it also doesn't hurt. Flash may be split into read-only and read-write parts, like OVMF_CODE.fd and OVMF_VARS.fd. Combined size of system firmware must not exceed 8 MiB by default (FW image(s) mounted with '-drive if=pflash'). This function detects which of the above applies and fills region_device_ops accordingly. Tested by starting QEMU with firmware passed as '-drive if=pflash', '-drive if=pflash,readonly=on' and '-bios'. When started with firmware passed through '-device loader', coreboot complains about corrupted FMAP, but this is the same behavior as without this change: [ERROR] Invalid FMAP at 0x40000 [EMERG] Cannot locate primary CBFS Writable pflash support was added about 17 years ago, so it should be supported by all QEMU versions currently in use. Since QEMU 5.0.0 it is possible to change the limit of firmware size with `max-fw-size` machine configuration option, up to 16 MiB, as bigger sizes would overlap with default IO APIC memory range. Change-Id: I3ab9f22c6165064a769881d4be5eab13a0a2f519 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82555 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-08-06mb/google/brox/var/jubilant: Update WWAN and UsbCam SettingsRen Kuo
Update GPIOs for WWAN and USB Camera functions. BUG=b:341188351 TEST=Build and verify on jubilant Change-Id: I145aa994767ddc59be519b96017af71badf82734 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2024-08-06mb/google/trulo: Register Firmware name for ISHVarun Upadhyay
Define ISH main firmware name so ISH shim loader can load firmware from file system. BUG=b:354607924 TEST=Boot trulo board, check that ISH is enabled and loaded lspci shows: 00:12.0 Serial controller: Intel Corporation Device 54fc Change-Id: Id60cb416a1cce5407bd483f0ce54f477584459b1 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83671 Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-05mb/asus/p8z77-m_pro/overridetree.cb: Correct PCIe devices configKeith Hui
Match PCIe root port allocation and associated comments to boardview, as follows: Z77 PCIe ports 1-4: PCIEX16_3 (x4) Z77 PCIe port 5: PCIEX1_1 Z77 PCIe port 6: RTL8111F LAN Z77 PCIe port 7: ASM1042 USB3 Z77 PCIe port 8: ASM1061 eSATA CPU PCIe lanes 1-8: PCIEX16_1 CPU PCIe lanes 9-16: Multiplexed via 4x ASM1480 to PCIEX16_1 lanes 9-16 and PCIEX16_2 lanes 1-8 (CPU PCIe lanes are not covered by overridetree.cb.) These are not hardware tested. Change-Id: I472e28add254ea945b401d1ddfd03f29f46d8fd2 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-05mb/supermicro/x10slm-f: Add board id for flashing via BMCNico Huber
The ID for X10SLM+F is 0811 as reported by Knogle on IRC. Change-Id: Ie58aad50e66efbc3113541884beea9668d886b5d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-05mb/google/dedede/var/awasuki: Disable SD cardWeimin Wu
Because Awasuki doesn't have SD card, disable related configurations. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: I1b0d2a9c2f9cdd4bca7c30cdc454ffa84b293146 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83706 Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-05mb/google/brox: Add model brox-ti-pdcBob Moragues
BRANCH=None BUG=b:348171026 TEST=Test on TI PDC device Cq-Depend: chromium:5691079 Cq-Depend: chromium:5691080 Cq-Depend: chrome-internal:7464767 Original-Change-Id: I6ffb8bdb2245a74b0d5270435d0ffc8a44e7c2a6 Original-Signed-off-by: Bob Moragues <moragues@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5691110 Original-Reviewed-by: YH Lin <yueherngl@chromium.org> Change-Id: Iac5b4cd4dcb1d274553f78e9d4295f8f9ad8a863 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-08-04mb/google/brya/var/nova: Adjust Type-C port to USB 2.0 onlyPranava Y N
This patch introduces the following changes, - Remove TCSS XHCI (USB 3.x) devicetree settings - Update Over Current (OC) & USB 2.0 config - Update TCSS-XHCI capabilities BUG=b:348332200 TEST=Able to build google/nova and ensure lsusb can list genesys hub device. Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83707 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-04mb/google/brya/var/nova: Remove PMC MUX settingPranava Y N
This patch removes the PMC MUX related setting from devicetree as Nova doesn't include a MUX for it's USB-C port. BUG=b:348332200 TEST=Able to build google/nova Change-Id: I23a949ba9b598d7a86c6f8b08a2821651978e489 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-03mb/dell/optiplex_9020: Fix UB in package power calculationMate Kukri
Fix potential undefined behaviour in the `get_pkg_power()` function: - If `rapl_power_unit == 0`, `pkg_power_info / rapl_power_unit` is invalid - If `rapl_power_unit > 7`, the result of the shift doesn't fit into a `uint8_t` Signed-off-by: Mate Kukri <km@mkukri.xyz> Change-Id: I48ef59c4fbeb0a55675ac24da31e6e0b194cb58d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83736 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-03mb/google/rex: Skip UART0 config in FSPSubrata Banik
UART0 is already configured in coreboot, so this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. BUG=none TEST=Able to build and boot google/rex0. Able to see all debug prints over CPU uart. Change-Id: I37744f05083eb82ba8ca579b628b69aa976e3d1f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83750 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-02soc/ti/am335x: Change and optimize memlayoutArthur Heymans
Clang builds (bootblock: 20800 bytes) are slightly larger than GCC builds (bootblock: 18688 bytes) so increase the size of both bootblock and romstage. The technical reference manual mentions no upper limit to the size of the bootblock in the TI header so increasing the bootblock size is allowed. To be able to link the clang bootblock increase it from 20K to 22K. Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02mb/google/brya/var/trulo: Remove mux references from typec portAmanda Huang
The Type-C kernel driver no longer programs the AP mux. So remove device references to the TCSS Mux control device from the Type-C port driver. BUG=b:351117685 TEST=USB-C drive can be detected after system warm or cold reboot. Change-Id: I2fd6e8fcebd194da03ba3f264ee89037ca11769a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83746 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-02mb/google/brox/var/greenbayupoc: update ALC236 verb tableWu Garen
The previous uploaded verb table is not fully applied due to configuration error. Uploaded the verb table provided by Realtek which can be found in b:336967284. BUG=b:326412504, b:336967284 TEST=deploy and check volume Change-Id: Ib9a8248c4a437fd204f40918d801a4a010a5c4df Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Terry Cheong <htcheong@chromium.org>
2024-08-02mb/google/brox/var/brox: Enable Class-D calibrationTerry Cheong
DC offset of class-D amplifier is 7mV in Brox which is larger than the expected 3mV. Add a section in the verb table to enable class-D calibration based on the updated verb table provided by Realtek in b:342506575 comment#6. This improves the offset to be less than 1mV. BUG=b:342506575 BRANCH=main TEST=Verify DC offset of speaker amplier output is less than 1mV with a multimeter when \ playing -100dB sine waves. Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85 Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-01mb/google/brox: Create jubilant variantRen Kuo
Create the jubilant variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:348543712 TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_JUBILANT. Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83212 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-08-01mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDsSean Rhodes
Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-01mb/starlabs/*: Add the subsystem ids for HDASean Rhodes
The Windows drivers require the subsystem ID to match on the PCI device, so set these to allow the driver to install. Change-Id: I01b36554d5322018efc72734a8e749cc06263577 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83621 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01mb/emulation/qemu-q35/memmap: Remove redefine macrosElyes Haouas
SMRAMC, C_BASE_SEG, G_SMRAME, D_LCK, D_CLS, D_OPEN, ESMRAMC, T_EN, TSEG_SZ_MASK and H_SMRAME are already defined in included "q35.h" file. Change-Id: Ic3c01cca14749f77adecc327a78ac011ba3f4c0b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83429 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01mb/google/nissa: Create teliks variantzengqinghong
Create the teliks variant of the nissa reference board by copying the anraggar files to a new directory named for the variant. BUG=b:352263941 BRANCH=None TEST=1. util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TELIKS 2. Run part_id_gen tool without any errors Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768 Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83408 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-01mb/google/brya/var/orisa: Remove mux references from typec portAmanda Huang
The Type-C kernel driver no longer programs the AP mux. So remove device references to the TCSS Mux control device from the Type-C port driver. BUG=b:351117685 TEST=USB-C drive can be detected after system warm or cold reboot. Change-Id: I4a24fb69ebec87f65b679cde0e4a1a8827cd365d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83722 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-31mb/google/trulo: Keep ISH default enableSubrata Banik
This patch drops fw_config probing for ISH because ISH IP should remains on by default for all Trulo variants. Additionally, removed the redundant ISH entries from variant override devicetree. BUG=b:354607924 TEST=Able to verify ISH PCI Device is available while booting eMMC sku. ``` lspci 00:00.0 Host bridge: Intel Corporation Device 461c ... 00:12.0 Serial controller: Intel Corporation Device 54fc ... 00:1a.0 SD Host controller: Intel Corporation Device 54c4 ``` Also, able to enter S0ix with this patch. ``` > suspend_stress_test -c 1 --ignore_s0ix_substates At AP console: s0ix errors: 0 s0ix substate errors: 0 s0ix pc10 errors: 0 At EC console: power state 5 = S0ix, in 0x38d87 ``` Change-Id: Ic1e415ec848ac91a9bbf21b26597f4e6b5f7a1f5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83695 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31mb/google/brya/var/xol: Using baseboard's PchPmSlpAMinAssert settingsRaymond Chung
Reduce PchPmSlpAMinAssert (pch_slp_a_min_assertion_width) to minimum time (98ms) from 2sec. BUG=b:349595391 BRANCH=firmware-brya-14505.B Test=Verified on xol Change-Id: Ia4b7b7ab5dc9afeb3505dfd2b42d0d397aed7a5c Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83683 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-30mb/google/brya/var/orisa: Remove redundant defaults from overridetreeRishika Raj
Streamline variant-level overrides by removing redundant entries that already exist in either the SoC-level or the platform-level configurations. BUG=None TEST=emerge-nissa coreboot Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-27mb/google/brya/var/trulo: Add USB2 Bluetooth device on Port 10Subrata Banik
This change adds a new USB2 Bluetooth device configuration on Port 10 for the Trulo variant. * A new `drivers/usb/acpi` chip is added with: * `desc` set to "USB2 Bluetooth" * `type` set to "UPC_TYPE_INTERNAL" * `reset_gpio` set to "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" * `device` referencing `usb2_port10` BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I9a92a4d008eb4d0c339079ecbbb77facece435ba Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-27mb/google/brya/var/trulo: Remove unused Bluetooth deviceSubrata Banik
This change removes the configuration for the unused USB2 Port 6 (index 5) and its associated Bluetooth device on the Trulo variant. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I9970274b9b1b1076a2f9d649d61c825cac71d0c7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83665 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rishika Raj <rishikaraj@google.com>
2024-07-27mb/google/brya/var/orisa: Remove unused Bluetooth deviceSubrata Banik
This change removes the configuration for the unused USB2 Port 6 (index 5) and its associated Bluetooth device on the Orisa variant. It also cleans up a redundant newline before the `serial_io_i2c_mode` definition. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: Icf1ff442530ad2263ad0b58829e5c7b2ce544439 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83664 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rishika Raj <rishikaraj@google.com>
2024-07-27mb/google/brya: USB2 Port 9 for integrated BT on Trulo baseboardSubrata Banik
This patch moves the configuration for integrated Bluetooth functionality (USB2 Port 9) from Orisa variant to the Trulo baseboard. This change is necessary to support the CNVi BT module on Trulo variants. The configuration is skipped for Orisa. Trulo: USB2 Port 9 is now configured as USB2_PORT_MID(OC_SKIP) to support the CNVi BT module. Orisa: The previous configuration of USB2 Port 9 as a Bluetooth port for CNVi WLAN has been removed. This change ensures proper Bluetooth connectivity is applicable for all Trulo variants including Orisa and Trulo. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I760a82cb6f6c98db7249caf1ba7e6d6c5dc8f2c4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83663 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27mb/google/brya/var/orisa: Update fw_config probe for storage devicesRishika Raj
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices. 2. Update fw_config probe to enable/disable devices in devicetree. 3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config is enabled. BUG=None TEST=emerge-nissa coreboot Change-Id: Id3a22aa2206e86fdca6f6fadbc849572890fee58 Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83657 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for OrisaAmanda Huang
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Orisa variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. BUG=b:345112878 TEST=Able to enter S0ix on Orisa eMMC sku after disabling UFS during boot path. Change-Id: I969b0c0c785ed4c408f6fc6de71e7d0c1a1ea27c Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-27mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSSubrata Banik
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Trulo variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. Note: Enabling this config would introduce an additional warm reset during the cold-reset scenarios due to the function disabling of the UFS controller as results we are expecting ~300ms higher boot time (which might not be user visible because `cbmem -t` can't include impacted boot time due to in-between resets). BUG=b:355384185 TEST=Able to enter S0ix on Trulo eMMC sku after disabling UFS during boot path. Able to grep below debug prints while booting the eMMC sku. [INFO ] FW_CONFIG value from CBI is 0x20000000 [INFO ] Disabling UFS controllers ... [INFO ] fw_config match found: STORAGE=STORAGE_EMMC Change-Id: I06a84fa8c3843edae5932e19d394b18b72ace422 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83654 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2024-07-26mb/starlabs/starbook/rpl: Don't set tcss_aux_oriSean Rhodes
Not setting tcss_aux_ori in devicetree is the same as setting it to zero so remove it. Change-Id: Ia0e90179dd05b23f1f36935be51327250c5a8684 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-07-26mb/intel/beechnutcity_crb: Update SMBIOS info for type 0,1,2,3Li, Jincheng
Update wake-up type, mainboard feature flags and enclosure type. All other info are used from src/lib/smbios_defaults.c Change-Id: I8a7d4958171df121e2cd3acb3a71554c695d64ab Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-26mb/intel/avenuecity_crb: Update SMBIOS info for type 0,1,2,3Li, Jincheng
Update wake-up type, mainboard feature flags and enclosure type. All other info are used from src/lib/smbios_defaults.c Change-Id: I8e68c057fefa1d408fb8d69fef066cb573c929a4 Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83328 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26soc/intel/xeon_sp/gnr: Add dimm_slot configurationJincheng Li
Add sample DIMM slot configuration table for avenuecity CRB and beechnutcity CRB. This table will be used to fill SMBIOS type 17 table. TEST=Boot on intel/avenuecity CRB It will help to update Locator, Bank Locator and Asset Tag with the value described in dimm_slot_config_table Change-Id: I53556c02eb75204994a1bcb42eccb940e83bd532 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26mb/starlabs/starbook/cml: Drop superfluous devices from devicetreeFelix Singer
In order to clean up a bit, drop devices which are equivalent to the ones from chipset devicetree. Change-Id: I92765b404508901c7e84fad0bca30489cf69abac Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83456 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-26ec/google/chromeec: Drop ability to build Chrome-EC, PD componentsMatt DeVillier
In preparation for dropping the Chrome-EC submodule, remove the ability for Chrome-EC and PD components to be built as part of coreboot. These components have not been used or buildable for many years. Change-Id: Ibf6bd43e755cf5b4d2aa8a42f38dc52e7023e9b3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83638 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-25mb/protectli/vault_[adl_p,bsw]/Kconfig: drop unneeded MAINBOARD_VENDORFelix Held
MAINBOARD_VENDOR is already provided by the Kconfig file on the vendor level, so there's no need to redefine it to the same value at the mainboard level. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icfcbcec005fadb8eaf1b8f90e1d71b3c6ee32088 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83640 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-25mb/google/nissa/var/riven: Add Fn key scancodeDavid Wu
The Fn key on riven emits a scancode of 94 (0x5e). BUG=b:345231373 TEST=Flash riven, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Iddedd08fc50e8e8e369ce3d73edf0f3077867e87 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83614 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-25mb/google/brya/var/trulo: Configure GPIO pins for ramstageSubrata Banik
This patch configures GPIO pins as required for booting the Trulo device from ramstage. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I7b540416083a923ba4d2e52aa8edafb4bfb9ac0e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-24mb/google/volteer/{delbin,drobit}: Use alias name for DPTF PCI deviceFelix Singer
Change-Id: If514ee7c1174d13b8ca8eb7fd20359e0730a8893 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83525 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24mb/protectli/vault_cml: Drop superfluous devices from devicetreeFelix Singer
In order to clean up a bit, drop devices which are equivalent to the ones from chipset devicetree. Change-Id: Ie485684747efccb8fb0ab87f10694c52a98f3c88 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83455 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24mb/google/dedede/var/awasuki: Initialise overridetreeWeimin Wu
Initialise overridetree based on the schematics revision 20240715. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-23mb/google/dedede/var/galtic: Group fw_config fields togetherMatt DeVillier
No need to have separate sections, and will be cleaner when adding another section in a subsequent patch. Change-Id: I4ad6be9dd67b5adbc9c5b0fcab51ce0c54351173 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-23mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670Michał Żygowski
It is a new incoming Protectli product based on Alder Lake-P SoC. More details and documentation will be added later. TEST=Boot Ubuntu 22.04 LTS and Windows 11 on VP6670. Change-Id: If4ae5b14b69806b6b0727d1ca1dcf56f47cfcd8e Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80501 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23mb/google/rauru: Add MediaTek MT8196 reference boardJarried Lin
Add mainboard folder and drivers for new reference board 'Rauru'. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/83573 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23mb/google/brya/var/xol: Limit power limits for low/no battery caseSeunghwan Kim
Xol has a shutdown issue on our reliability test environment: - High temperature - No battery condition It needs to have margin for the PL2 and PL4 values from the adapter power, this will limit the PL2/PL4 values up to 30W/40W for xol's 45W power adapter. The new values are confirmed by our power team. BUG=b:353395811 BRANCH=brya TEST=built and verified MSR PL2/PL4 values. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:18000000 <= MSR PL1 (18W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) [When connected 60W adapter without battery] Before: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:60000000 After: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:30000000 constraint_2_power_limit_uw:40000000 [When connected 45W adapter without battery] Before: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:45000000 constraint_2_power_limit_uw:45000000 After: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:30000000 constraint_2_power_limit_uw:40000000 Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-07-22mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INTSeunghwan Kim
If user continues to use the touchpad for over 3 minutes on Xol, the pointer movement is stuttering. Touchpad I2C transaction should appear during the interrupt signal level is low, but we could see some more I2C transaction after the interrupt signal(GPP_F14) went to high. We found experimentally that changing the interrupt type to GPIO_INT from APIC_IRQ improved this issue. We are still investigating, would like to apply this change first for Xol's dogfooding. BUG=b:350609957 BRANCH=brya TEST=built and verified there's no stuttering issue on touchpad movement Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-07-22mb/google/brya/var/trulo: Configure early and romstage GPIOsSubrata Banik
This change adds early and romstage GPIO configurations for the trulo variant, including: Early GPIOs: - GSC (Google Security Controller) - WP (Write Protect) - UART0 (for serial debug) Romstage GPIOs: - Touch Screen early power sequencing CrOS GPIOs: - CROS_GPIO_VIRTUAL - GPIO_PCH_WP BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ic1b84f61ef62ddbadc2a45758fb3fce90fce0e88 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83568 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/trulo: Add fw_config for PDCSubrata Banik
This patch adds FW Config to the device tree for choosing between the discrete PD chip. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I0a8fb0225edecb063dede31efaec6f2502476977 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add PnP descriptionsSubrata Banik
This patch adds power related entries (FIVR and policy to control lower power c-state transitioning) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ib125c91be79a81f3103dcd587dc685134a292e03 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-07-22mb/google/brya/var/trulo: Add Thermal descriptionsSubrata Banik
This patch adds Thermal related entries (like, TDP, TCC and enabling DPTF config with required sensor configuration) to the devicetree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I32f9219c0ba6b70f847f0752bff8aa2e4fdd0979 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83565 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-22mb/system76/mtl: Add Darter Pro 10Tim Crawford
The Darter Pro 10 (darp10) is an Intel Meteor Lake-H based board. There are 2 variants to differentiate them as they have different keyboards and so use different EC firmware. - darp10: 16" model with 102 key keyboard - darp10-b: 14" model with 83 key keyboard Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82609 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya: change NAU8825 config to fix headset button detectionTerry Cheong
Brya/brask devices using NAU88L25 are not recognizing headset buttons correctly. The reason is we are using wrong reference voltage of MICBIAS. Use VDDA instead. BUG=b:352215240 TEST=test with 3.5mm headset with buttons on volume up/down and pause Change-Id: I0619021c6fd0a196c318aee58e07dc4149f1d64e Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/variants/orisa: Change board strap memory configRishika Raj
Reorder GPIO pin mapping as per platform documentation: * GPIO_MEM_CONFIG_0 -> GPP_E2 * GPIO_MEM_CONFIG_1 -> GPP_E1 * GPIO_MEM_CONFIG_2 -> GPP_E12 * GPIO_MEM_CONFIG_3 -> NC BUG=None TEST=emerge-nissa coreboot Change-Id: I4e979686833095a904b114500dc1142def583afa Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83549 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-22mb/google/brya/var/trulo: Add Audio descriptionsSubrata Banik
This patch adds descriptions for Audio device (Speaker, Jack and Mic) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ied531dde856fb7c9a410b5667843c9be759cfc8f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add eMMC descriptionsSubrata Banik
This patch adds descriptions for eMMC device (supported mode and DLL tuning) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I8f1310313b8114731aa417610f245f94c8978ac0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add fw_config probe for storage devicesSubrata Banik
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices, this is used for the first boot in factory. 2. Add fw_config probe to enable/disable devices in devicetree, to avoid suspend(s0ix) fail issue. 3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config is enabled. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ifdaa0bf35413981327097c260ab47e757f697e37 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add CNVi descriptionsSubrata Banik
This patch adds descriptions for CNVi WiFi and BT device to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I7396917ca7875dcbe1d35a371cc450a9e070b18d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add LSIO descriptionsSubrata Banik
This patch adds descriptions for Low Speed I/O (I2Cx, GSPIx, UARTx) to the device tree. It also includes entries that will generate ACPI code at runtime with LSIO end-point device. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I94a3a7f6f85d84407f32ab4c879b236a80859f2d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83550 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/trulo: Add TCSS port descriptionsSubrata Banik
This patch adds descriptions for TCSS port, including over-current (OC) pin configuration, to the device tree. It also includes entries that will generate ACPI code at runtime with port definitions, locations, and type information. Additionally, implement the TCSS PMC MUX programming. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83548 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/trulo: Add USB2/3 port descriptionsSubrata Banik
This patch adds descriptions for USB2/3 ports, including over-current (OC) pin configuration, to the device tree. It also includes entries that will generate ACPI code at runtime with port definitions, locations, and type information. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I873810e401c4afdc162036f01bae7247f9b8c749 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/rex/variants/screebo: Generate RAM IDsKun Liu
Generate 3 Samsung RAM IDs K3KL9L90CM-MGCT Samsung K3KL6L60GM-MGCT Samsung K3KL8L80CM-MGCT Samsung BUG=b:331539447,b:333145301,b:333220620 TEST=Run part_id_gen tool without any errors Change-Id: I4ba0fb409015c24446b2ae8e224fbce3910715e3 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83501 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21mb/google/brya/var/trulo: Add minimal devicetree entries to bootSubrata Banik
This patch adds minimal device entries and chip configs for Trulo overridetree.cb to boot. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ic8b90dbaaabb439c347a891650d255948d48810a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83546 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21mb/google/brya: Centralize EC configuration in trulo baseboardSubrata Banik
This change moves the EC configuration from the orisa variant to the trulo baseboard, enabling reuse by other variants in the future. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: Ib5611cf67a41950c1c4ce936a5d2bea7fdca5c68 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83544 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21mb/google/brya: Centralize GPIO configuration in trulo baseboardSubrata Banik
This change moves the GPIO configuration from the orisa variant to the trulo baseboard, enabling reuse by other variants in the future. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: If41c1b567a0ed6397bc935183c832a423f43e8b9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83545 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21mb/google/brya: Enable SKIP_RAM_ID_STRAPS for TRULO variantSubrata Banik
This change enables SKIP_RAM_ID_STRAPS for the TRULO board variant as this board design won't stuff MEM strap GPIO hence, sets the static SPD ID to 0 for the MT62F512M32D2DR-031 DRAM part. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I1acb4680a143611c55f4fa6e032fde38c62af054 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-21mb/google/brya/var/trulo: Populate DRAM configuration parametersSubrata Banik
This patch adds key DRAM configuration parameters as below: - Rcomp - DQ byte map - DQS CPU<>DRAM map - ECT - CCC Mapping - SPD Index Source: Trulo Schematics Rev0.5 (dated June'24) BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: Ie7abc393a71becf26d53ae9e4fc56f66c7117051 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-21mb/google/brya/var/trulo: Add LPDDR5 DRAM (MT62F512M32D2DR-031)Subrata Banik
This patch adds Micron Technology LPDDR5 DRAM (part: MT62F512M32D2DR-031) for Trulo. Make use of spd_tools to generate SPD file after following the below steps: 1. make -C util/spd_tools 2. ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt Output files are: 1. dram_id.generated.txt 2. Makefile.mk BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: Id35f6b57b716375abb66db187413f0f82361d962 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83539 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19mb/google/dedede/var/awasuki: Add initial GPIOs configTongtong Pan
Configure GPIOs according to schematics revision 20240712. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: Ic8f346b788b489f50ab96c0ace8541720a832f72 Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83449 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-07-19mb/google/dedede/var/awasuki: Generate 3 RAM IDsTongtong Pan
Vendor DRAM Part Name Type SAMSUNG K4U6E3S4AB-MGCL LP4X SAMSUNG K4UBE3D4AB-MGCL LP4X MICRON MT53E1G32D2NP-046 WT:B LP4X BUG=b:351968527 TEST=Run part_id_gen tool without any errors Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83427 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-19mb/google/dedede: Create awasuki variantTongtong Pan
Create the awasuki variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:351968527 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_AWASUKI Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0 Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-19cpu/intel: Add socket typesJincheng Li
Add socket types for LGA1700, LGA3647_1, LGA4189, LGA4677. Select the socket type for different boards. For the socket types which are not defined in SMBIOS type4, CPU_INTEL_SOCKET_OTHER could be used. Change-Id: Ida3315694f3ce397b9ad9d676d3195da5f096cb7 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83329 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-07-18tgl,adl,rpl mainboards: Drop superfluous cpu_cluster deviceFelix Singer
The cpu_cluster device is defined in the chipset devicetree. So drop it from the mainboards. Change-Id: Ib84e7804c03f1c0779ab7053a09e397a267a3844 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83523 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/nissa/var/glassway: Add WIFI_SAR_ID_1Daniel_Peng
Set "option WIFI_SAR_ID_1 1" for WIFI_SAR_ID field in fw_config. BUG=b:347108861 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I179dad5eeabc1d84aa0a2de5359be5848a2ecc39 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83478 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/brya: Add config options for TRULO boardSubrata Banik
This change adds the necessary Kconfig options to enable support for the TRULO board, including selecting the appropriate baseboard, HDA verb table, and TCSS configuration. Additionally, corrected the TPM_TIS_ACPI_INTERRUPT from `13` to `17` for Trulo as applicable. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I5c1cbd56cf2734058aced35868ae42c1c160f62e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83500 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/brya/variants/trulo: Include hda_verb.cSubrata Banik
This change adds hda_verb.c to the ramstage build, but only when the CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB config option is enabled. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I9b17126ff1493b5714d6ae715ad2863bdff4ed46 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83499 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/brya: Standardize TPM TIS ACPI interrupt configurationSubrata Banik
This patch sets a default value of 13 (GPE0_DW0_13/GPP_A13_IRQ) for the `TPM_TIS_ACPI_INTERRUPT` configuration option across most Google Brya variants. The HADES board uses interrupt 20 (GPE0_DW0_20/ GPP_A20_IRQ), and the ORISA board uses interrupt 17 (GPE0_DW0_17/ GPP_A17_IRQ). This refactoring simplifies future additions of board-specific TPM interrupt configurations, improving maintainability. BUG=none TEST=The timeless builds with this patch for both Nissa and Brya devices produce the same binaries. Change-Id: I9d913bf3da6957ab5c700dd746bc4b5350427d73 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83493 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-16mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinterEmilie Roberts
Fixes a pmc_mux port mapping error introduced in coreboot commit 4fa8354 Mithrax and felwinter do not have sequential mux_conn[X] to connY mappings which led to the kernel subsystem linking between Type C connectors and USB muxes to be incorrect. The previous patch attempted to fix this by changing the custom_pld layout. However this broke USB usage except for charging. This patch reverts the custom_pld layout and instead changes the pmc hidden and tcss_xhci port mappings to match the hardware layout. BUG=b:352512335 b:329657774 b:121287022 b:321051330 b:204230406 TEST=emerge-${BOARD} coreboot TEST=Manually check that usb-role-switches are mapped to the correct port. Attach USB 3 A to C cable from development machine to left port of DUT. Attach nothing to right-hand port. ectool commands below are only for felwinter as a workaround for devices without a firmware patch to connect superspeed lines. ectool usbpd 0 none ectool usbpd 0 usb ectool usbpd 1 none ectool usbpd 1 usb echo host > /sys/class/typec/port0/usb-role-switch/role (should succeed) ls -l /sys/class/typec/port0/usb-role-switch (note CONX-role-switch) echo host > /sys/class/usb_role/CONX-role-switch/role (should succeed) echo host > /sys/class/typec/port1/usb-role-switch/role (should fail as no cable attached) ls -l /sys/class/typec/port1/usb-role-switch (note CONY-role-switch) echo host > /sys/class/usb_role/CONY-role-switch/role (should fail as no cable attached) BRANCH=firmware-brya-14505.B Change-Id: Iebd259842d3affa259069cd776b46759c1c60712 Signed-off-by: Emilie Roberts <hadrosaur@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83472 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-15mb/lenovo/t420: Use vendor default power limitsAnastasios Koutian
Also set the vendor default TCC offset temperature Change-Id: Ia187b67ae28fbcda7d5d0e35ec64a3b21d97a21b Signed-off-by: Anastasios Koutian <akoutian2@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-15mb/clevo/cml-u/dt: Make use of chipset devicetreeFelix Singer
Make use of the alias names defined in the chipset devicetree and remove devices which are equal to the ones from the chipset devicetree. Change-Id: Ifc882c2ac9d4e9ce2ed4305bdd6859a5d1e1b09c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-07-15mb/google/poppy: Drop superfluous devices from devicetreeFelix Singer
In order to clean up a bit, drop devices which are equivalent to the ones from chipset devicetree. Change-Id: Ief199db47fc529c510709ac37be6014b63244e84 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-13cfl/cml/whl mainboards: Drop superfluous cpu_cluster deviceFelix Singer
The cpu_cluster device is defined in the chipset devicetree. So drop it from the mainboards. Change-Id: I65bfeaf0b8771c123c0615531c2cc608b222949b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83440 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-13mb/google/byra: Add VBTs for variants missing themMatt DeVillier
Several brya variants were missing VBT files, add and select them in Kconfig. Also select in Kconfig for VELL, which already had a VBT but was not using/selecting it. TEST=build/boot google/brya (marasov), verify display init functional / payload screen shown. Change-Id: I6848c2b78cf37157299d94bf12c0b6d925ea1432 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83434 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>