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2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04amdfam10: Drop tests for LATE_CBMEM_INITKyösti Mälkki
Change-Id: Ibe16242d98531ff8e8a696f571496c6f46ea964b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-04mb/lenovo/t430/devicetree: Add missing TPM entryPatrick Rudolph
Tested on Lenovo T430: The TPM is advertised through ACPI tables and the version can be read using tpm_version, tcsd and tpm_tis. Change-Id: I0b0c39e7aa1be4a479325d4b5eff5892a7e2f69f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/26780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-04mainboard/amd/inagua: Fix a typo in commentElyes HAOUAS
Change-Id: I5ace69f9a624da9556a14c498a592305a3b1c89f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/samsung: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I0aefe25e3af61c747c06629e365b8e27459181aa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/msi: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I9d35bc706b0daac1e234441c86286cb2957f89ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/winent: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ib06f771b6b50f2ad1af440c8019e8cca38d2a4f0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/via: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I490091e7dec5a46040e8ba7cd5cd6c244b017e30 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/supermicro: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Id2622e473959dcf105bfeeaebddd582593a3c274 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/siemens: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ic334f65e5c27d4f773f81fc1c9e3df7d63d47a11 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/lippert: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I52fe5a67e6b914426943c3499904e0546c3ea623 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/lenovo: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I958fe66655cc3c589ce6709b83c56a9472628324 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/kontron: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I335dda11d0c1ee58bd2728580c48c41cef574654 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/jetway: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Icc7d7fee38e41f4bfda685fd42bf504a788b440c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/intel: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I891b056b64fde27ef0e351f8cf24a258fb5cabfa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/iei: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I750ec788b7526ee2a7aa803bffb93805cedfb2ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/ibase: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I8e21843e11498438e115f1f82f94f2944ae7a3c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/hp: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I3f85e2ef0682b808f6e99dc406bccb88badcb82c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/google: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I24fd33887152c12b9db9742af475115b02b31ff2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/gizmosphere: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Iacbd72e1c60573f4bb5ffa40717141e9fbca01bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/gigabyte: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I0b0a09098bd4185ae36f1468ebc151e39668ee86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/getac: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ib7068f381971d1270b22cb03937f1e7fa30acb46 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/foxconn: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I0a4b7d774db1b2b486f44bd7363555c15d464484 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/esd: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I0458e4fe08e32daf0b880e0a29752297e8159fe6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/elmex: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I085a5b7dca252943590a30c1afe6ad776dac6c97 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/cubietech: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I299c579c996da4e0e9fa1fc4d8b40706356509f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/biostar: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I15c34c65fba22c297cd26c2ee23bcf5e7b56e233 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/bap: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I8999f1603014b558a9efd3823614020ba0ecce82 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/bachmann: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I2022100f7d1d7b7f2667e45efc8cea074b424b65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/avalue: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I2c3e44e1f7ad7dd14f62fd99fd48c485ec74b3cf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/asus: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Id572144827b515e9e84c51aa3e4f8a20baf1c212 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/asrock: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ie1e319375ab0f5565805557b15e0bf821dfb223e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/aopen: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I05d938add5aabe2557a5d915a54a920e7ba9f50f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/advansus: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I6a3df8074d874cc5f4e1ff45c422c685cc90dbb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mainboard/adi: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I2c2e00cef28414d6beff1e37539977ee4c6e5088 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src/mainboard: Add space after 'if'Elyes HAOUAS
Change-Id: Icae1983be6b8c5aebb121be8a383e2613e064122 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04sb/amd/rs780: Fix invalid function declarationsKyösti Mälkki
Provide empty stub implementations for set_pcie_reset() and set_pcie_dereset(), many boards do not provide a proper one. Change-Id: Ia6811442905ef1776fa5a8e3f5d4433e86e42f88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04sb/amd/sr5650: Fix invalid function declarationsKyösti Mälkki
Change-Id: I5034debc2296352e698898c20910a2d76071e30a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04amdfam10: Fix mismatch of function declarationsKyösti Mälkki
Callsite declared returning int, which makes more sense than u8 the motherboard side code defined the functions with. Change-Id: I8ee83aa2833408ad163c9011a076e08578f3ca6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04amdfam10: Fix function declaration to staticKyösti Mälkki
Change-Id: Ifb73f51d34e179ff95b2b1e3ab28adc21717f9ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-03mb/google/kahlee: Remove #include <soc/smi.h>Richard Spiegel
Because of struct sci_source table of events that have to generate SCI or SMI, <soc/smi.h> was included to kahlee/grunt gpio.c files. However, new code transfered most of SCI/SMI/interrupt programming (with exception of events not associated to a GPIO pin), and therefore smi.h is now included by gpio.h. It was also added to some other files where they are not needed. Only smihandler.c truly needs it. Remove the includes. BUG=b:78139413 TEST=build and boot grunt. Change-Id: I64cf0796103a5226ddace03d05d94160bf93aa69 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26721 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-03mb/google/poppy/variants/nami: Load vayne VBT binaryIvy Jian
Load vbt-vayne.bin by reading sku-id. BUG=b:80509366 TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: Ia26ea4a9b7679aeb9d98f19ffaa1b686af828339 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-03pcengines/apu1: align with apu{2,3,4,5} lowercase namingPiotr Król
This change may require board_mismatch=force if mainline firmware was used. If vendor firmware was used this patch remove flashrom confusion since system product name reported by SMBIOS tables will match mainline firmware. Change-Id: Ic6942bc36df1a02db61b035ddc892585688aa27b Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/26757 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-03intel bd82x6x/lynxpoint systems: Update ACPI thermal zone handlerMartin Roth
Currently the throttle event handler method THRM is defined as an extern on the intel bd82x6x and lynxpoint chipsets, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. This also requires moving the thermal handler, which now includes the define to before the gnvs asl file. TEST=Build before and after, make sure correct code is included. Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26123 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-03mainboard/asus/am1i-a: turn on the tpmKevin Cody-Little
Along with other patches submitted for review to get the chipset parts working, this allows Linux or other OS to use a TPM module plugged into the 20-pin LPC header on the board, by exposing its presence through the ACPI and PNP tables. This patch adds to the Kconfig and devicetree.cb files. Tested with the TPM/FW 3.19 and the trousers tools. Change-Id: I8c1aea245f81fa44a6bdd5301bbee958cbcdfaaa Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INITKyösti Mälkki
With implementation of LATE_CBMEM_INIT, top-of-low-memory TOLM was adjusted late in ramstage. We do not allow that with EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO space is now used with statically set TOLM. Also remove support code for the obsolete LATE_CBMEM_INIT this northbridge used. Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02src/mainboard: Add and update license headersMartin Roth
This change adds and updates headers in all of the mainboard files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all mainboard directories. Change-Id: Ibe038a8f7468253b21fd2ac90c045d0c9cc89dfc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-01mb/google/nautilus: Add "rotation" controljimlai
The driver only supports streaming images flipped horizontally and vertically. In order to ensure that all current users will be fine if or when support for upright streaming is added, require the presence of the "rotation" control now. BUG=None BRANCH=None TEST=Verified the MIPI and USB camera function on DUT board Change-Id: I7e3abdea9071da1a089c7165f6bb609428090792 Signed-off-by: Lai, Jim <jim.lai@intel.com> Reviewed-on: https://review.coreboot.org/26727 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01mb/google/octopus: Enable RT5682 headset codec for BIP boardNaveen Manohar
Patch adds required changes for RT5682 codec enablement for the BIP board. And code clean-up nhlt blob selection method in config. BUG=b:77892150 TEST=build and boot on a BIP PO board. verify headset codec i2cdetects at address 1a. Change-Id: Iee91518c03a0e9e6ed52bc54a60fc607730a0b7d Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/26211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-01mb/google/rambi: Set SMI mask using google_chromeec_events_initFurquan Shaikh
This change updates rambi ec init to perform SMI mask setting using google_chromeec_events_init. Change-Id: I7def3c07b4d7bfbe15b2d1c45381bdc31b7e3476 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-01superio/nuvoton/npcd378: Add PSU fan controlPatrick Rudolph
Implement method to access the SuperIO's harware monitor (HWM) IO space. Set the PSU fan using a new CMOS option psu_fan_lvl. Add the CMOS option to all board that use NPCD378. In case no CMOS is set use the default fan level 3. The HWM space can be written to at any time, but the SuperIO has to be notified that a write is ongoing. After clearing the write-lock bit all changes are applied at once. Tested on HP Compaq 8200 SFF. Change-Id: I56ce7ad1df88638589a577b8a09d5d775557887b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26050 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01mb/google/fizz: Add USB port infoEmil Lundmark
This adds all USB ports to the device tree. Additionally, it adds _PS0 and _PS3 ACPI methods for the visible USB A ports, which makes it possible to control the port power (VBUS) of each port individually. Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://review.coreboot.org/26472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-05-31mainboard/google/kahlee: Add careena variantMartin Roth
Add Careena variant, based on the grunt board. BUG=b:80106042 TEST=Build Careena Change-Id: I87a24f6d8115aacf5b21181f3820cf2718ad252a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31mb/google/poppy/variants/nocturne: configure the FPMCU interfaceVincent Palatin
The FPMCU is using the standard cros-ec-spi interface on GSPI1. Configure the GPIOs controlling the MCU too. We need to be able to wake from S3 on the MCU interrupt, re-configure GPE0 DW0 to point to GPP_C bank. BRANCH=poppy BUG=b:79666174 TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version', verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup' then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs with the flash_fp_mcu script. Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/26684 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDENico Huber
As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31mb/via/epia-m700: Remove boardKyösti Mälkki
Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I34f9bffcced5ccdd8691994b78fffed057021d0e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31mb/via/vt8454c: Remove boardKyösti Mälkki
Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: Ic135c3f8eb18818d0ae3b63f53b542905815bbd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31Remove all VIA CN700 boardsKyösti Mälkki
Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I06840476ad187cbb6e6af554b5c8e8c4d66f6624 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31Remove all AMD K8 boardsKyösti Mälkki
Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-31mb/msi/ms9652_fam10: Fix dependency on amdk8/util.aslKyösti Mälkki
Change-Id: I0bb515fbf7b1ae9b0dd1b61bad0c45a7f38d6767 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-30mainboard/google/kahlee: move grunt's chromeos.fmd to baseboardMartin Roth
The chrmoeos.fmd file will be common across variants, so move it out of of grunt directory and into the variants/baseboard directory. BUG=b:80106042 TEST=Build grunt Change-Id: I259d85f60c5e19e00f7d9149542bcfdcc6dfaf4f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-30mainboard/google/kahlee: move SPDs to variants/baseboard/spdMartin Roth
The SPD files will be common to many of the mainboards, so move them out of grunt and into the variants/baseboard directory. BUG=b:80106042 TEST=Build grunt, make sure spd.bin is the same. Change-Id: I53975a46a8c7d7e519bb6f7ef6ccd0b817ac4c92 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-29chromeec platforms: Update ACPI throttle handler callMartin Roth
Currently the throttle event handler method THRT is defined as an extern, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I6337c52edaf9350843848b31c5d87bbfca403930 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-29mainboard/hp/dl145_g1: Remove empty WAK ACPI methodMartin Roth
Change-Id: I16cdf2781ce1bf9458300de70a87a3bb98d01636 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-28soc/intel/apollolake: Don't use pulldowns in standby state for 1.8/3.3V pins.Shamile Khan
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination Configuration. Furthermore, some of these pins were configured with normal termination of None which would as per above mentioned document lead to a standby termination of None anyways. Instead of pull downs, use the IOSSTATE setting for driving low via the Tx mode. BUG=b:79874891, b:79494332, b:79982669 BRANCH=None TEST=Flashed image and booted to OS on Yorp. Touchscreen does not consume power in suspend state. Change-Id: I7dcf3691b969d018b3cfb6af3f7467c9b523fee5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/26491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-27grunt: Wire up the EC SMI handlerRaul E Rangel
This won't actually get called yet since the GPIO pin has not been configured as SMI. BUG=b:80295434 TEST=grunt: Made sure events could be processed. Change-Id: I189e26196e4543b3e34bff5d9df8566eff07d585 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-27stoneyridge GPIO: Create and use PAD_INT for interrupt pinsRichard Spiegel
The default interrupt control for GPIO pins within stoneyridge is for edge triggered, high. However, sometimes these need to change, or maybe the interrupt needs to be reported or delivered. This was the case of platform grunt, where the interrupt related bits were being changed afterwards. Ideally all the bits should be programmed through the same procedure. Create several PAD_INT definitions (for general configuration, for trigger configuration and for interrupt type configuration) and change function sb_program_gpios() to accept the output from PAD_INT_XX and program all the necessary bits while keeping compatibility with other PAD_XX definitions. BUG=b:72875858 TEST=Add code to report GPIO and interrupt configuration, build grunt and record a baseline. Add new code, rebuild grunt and record a test output. Compare baseline against test, there should be no change in GPIO or interrupt programming. Remove code that reports GPIO/interrupt configuration. Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-26mainboard/intel/dg41wv: Fix lint check errorMaulik V Vaghela
Fix lint error due to non-ASCII characters BUG=none BRANCH=none TEST=check if no error in checkpatch.pl script. Change-Id: Iec7682e460c8e0d467a70349a23390554cc1de92 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26562 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-26mb/intel/dg41wv: Add mainboardArthur Heymans
This board was used a test target for the x4x DDR3 raminit patches and has an easy to access DIP8 socket. What is tested and works: * S3 resume * PEG, PCI, USB, SATA * Sound * Ethernet * Native graphic init (textmode and linear fb) on the VGA output * Passing memtest86+ with 2 2Rx8 4G dimms * PS2 Keyboard * Flashing coreboot internally from vendor BIOS. What does not work: * Running dram at 533 MHz (limited at 400MHz currently) Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux 4.10. Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20003 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25mb/google/poppy/variants/nami: Perform PL2 setting in variant_devtree_udpateFurquan Shaikh
This change moves PL2 override to variant_devtree_update for two reasons: 1. This function was added to basically override devtree settings in variant specific code. So, it would be a good idea to perform all the overrides in a single place. 2. Adding a device for performing nami_enable would require changes to devicetree and special handling for calling this device enable. Thus, nami_enable was never getting called. BUG=b:80148703 Change-Id: Ifa24a7b6e99cad2368b3d656a757f26297373121 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-25mb/google/reef: fix indention in memory.cAaron Durbin
In cbdbf018 (mb/google/reef/variants/: Add new memory ID) a new memory configuration entry was added. However, it was using spaces for indention. Correct that. Change-Id: Iaf788b0ad8a6ef3b001e7f29a6710e6e8f731ecf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-25mb/google/poppy/variants/nami: Use GPP_E4 for BT_OFF#Frank Wu
The BT W_DISABLE2# pin is connected to GPP_E4 in the latest schematic. Update GPP_E4 as GPO and set 1 as default. BUG=b:79993692, b:72007632 BRANCH=None TEST=Enable/disable BT/WLAN by following command. Enable: localhost ~ # iotools mmio_write32 0xfdae0590 0x40000201 localhost ~ # iotools mmio_write32 0xfdae05a0 0x40000201 Disable: localhost ~ # iotools mmio_write32 0xfdae0590 0x40000200 localhost ~ # iotools mmio_write32 0xfdae05a0 0x40000200 Change-Id: I9ef1a5314652ab29172d246abd58ee4e1a8a6299 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26502 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25mb/google/kahlee: Init APU_BIOS_FLASH_WP_L GPIO to reset stageDaniel Kurtz
GPIO APU_BIOS_FLASH_WP_L is first read in ROM stage to determine the state of the BIOS FLASH Write Protect signal at boot. The result of this read accumulated in the vboot state that's passed on to the upper layers of the stack. Therefore this GPIO must be configured as a "reset stage" GPIO, not a "RAM" stage GPIO. BUG=b:79866233 TEST=firmware_WriteProtect Change-Id: I1d96ab4bbfeaf9db9f74cf0c58cbab2104079bf7 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26498 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24mb/hp: Add new port compaq_8200_elite_sffPatrick Rudolph
Add new port based on autoport. The board uses a NPCD378 SuperIO, that is full of custom hardware. The 8MiB flash SOIC-8 can be accessed after cutting of a part of the DIMM slot holder. The flash IC has no diode, powering a part of the board while flashing externaly, including the Standby-LED. The following have been tested and is working: * Native raminit with up to four DIMMs * Libgfxinit on DisplayPort * USB * EHCI debug * Serial on RS232 * Ethernet * PCIe on x4 * PCIe on x16 * SATA * Booting GNU Linux 4.14 using SeaBIOS 1.11.1 as payload * Flashing internaly * PS/2 is working Untested: * PCI slot * LPT port * VBIOS * S3 resume Not working: * PSU fan managment (runs at 100%) * Half of SuperIO functionality is unknown TODO: * Reverse engineer remaining SuperIO registers * Reverse engineer SMM Fixes on follow-up commits: * Added PSU fan control * Reverse engineered some of Super IO's HWM registers * Added SMBIOS tables for IPMI Change-Id: I4ee8da6349222fda8b6c30a7210ffdd65c183439 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25385 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24AMD geode/lx: Remove generic_sdram.c includeKyösti Mälkki
The file under lib/ will be removed with K8 and Geode LX is the only other platform using it. Change-Id: Id49d72358ecfc4aae4980e3ae787952073e5c838 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24mb/gigabyte/ga-h61m-s2pv: Add new mainboardAngel Pons
Tested with GRUB 2.02 as a payload, booting Arch Linux with latest kernel. This code is based on the output of autoport as well as existing ga-b75m-d3h and ga-b75m-d3v mainboards. Working: - Serial port I/O - S3 suspend/resume (broken with SeaBIOS 1.11.1) - USB ports and headers - Gigabit Ethernet - Integrated graphics (libgfxinit) - PCIe x16 graphics - PCIe x1 - SATA controller - Hardware Monitor - Fan Control (fancontrol on linux works well) - Native raminit (4+4GB, 4+2GB, 2+2GB, DDR3-1333) - Native graphics init with libgfxinit - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested. - NVRAM settings. Only `gfx_uma_size` and `debug_level` have been tested with values different from the default. Untested: - VGA BIOS for integrated graphics init - DVI port. It can detect a "fake" display, that is, an EEPROM connected to the DVI port. - PS/2 ports - Audio: Only rear output (green) has been tested. - EHCI debug. - Parallel port - Non-Linux OSes - ACPI thermal zone and fan control (probably not working) Not working: - SATA devices with Tianocore (payload issue) - PCIe to PCI bridge. It seems to be poorly supported on Linux, it lacks a public datasheet and vendor BIOS behaves in the same way: The bridge and the devices behind it appear, but drivers fail to find devices attached to the bridge. Change-Id: I598a0b75093a0f1aef2ac615035d66786a8c22cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/25912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-24mb/packardbell/ms2290: Get rid of device_tKyösti Mälkki
Change-Id: I42b19d660b681cca8fea7d2f52b43c8daceb5e35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24mb/emulation/qemu-q35: Get rid of device_tKyösti Mälkki
Change-Id: I74461e75abce6cdd0c7a16b3a6589de3486a1a3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24src: Add space after 'while'Elyes HAOUAS
Change-Id: I44cdb6578f9560cf4b8b52a4958b95b65e0cd57a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-24mb/intel/glkrvp: Remove unused DPTF_CPU_ACTIVE_ACx definesSumeet Pawnikar
GeminiLake platform is fan-less design. We do not need these DPTF_CPU_ACTIVE_ACx defines. Removing these for GeminiLake RVP board as these are not being used. Change-Id: I810809bf58198a028e6cfcdbd68887f5f154a0ad Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/26469 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24mb/google/reef: Remove unused DPTF_CPU_ACTIVE_ACx definesSumeet Pawnikar
ApolloLake based reef platform is fan-less design. We do not need these DPTF_CPU_ACTIVE_ACx defines. Removing these from all reef variants as those are not being used. Change-Id: Id3cb7f7826a5e02cf447c70ab5cdc9b5d86982ca Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/26468 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24src: Remove space after `defined`Elyes HAOUAS
Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26460 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24mb/intel/glkrvp: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I791a69aeca9b44daabc9a3e5fb9ac92e6b22f3e5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-24mb/nvidia/l1_2pvv: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ife8ca30322d83c6d9276e79c057f12a901d6e8f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26312 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24mb/google/poppy: Enable SAR config on NamiAmanda Huang
This change enables SAR config on Nami with CHROMEOS option. BUG=b:75077304 BRANCH=master Change-Id: I8217333db2db6c0fd5e1c144dedd3692b1e1e6a3 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/kahlee/dsdt.asl: Add method _SWSRichard Spiegel
_SWS is the recommended method of wake source retrieval. Now that PM1I and GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code. BUG=b:76020953 TEST=Build grunt Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-23mb/siemens/sitemp_g1p1: Get rid of device_tKyösti Mälkki
Change-Id: I2362c46c0b525fa67833e52f210265da1926142c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-05-23mb/emulation/qemu-i440fx: Get rid of device_tKyösti Mälkki
Change-Id: I11c35d22d9a9cba3cdb6af0ec1d2c01de8c20b6e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-23mb/google/poppy/variants/nocturne: enable MKBPNick Vaccaro
BUG=b:79617938 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", flash nocturne, boot to kernel, run evtest and verify that cros-ec-buttons is present and functional. Change-Id: Id710782e1f4e18eaac2a90c7c0f91af5223dbce3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/poppy/variants/nocturne: enable I2C #5 busNick Vaccaro
Enable I2C #5 for rear camera and SAR. BUG=b:79784124 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' and verify i2c bus #5 is detected. Change-Id: Ic5b754fb97231aeab0278d71f8ced9343c30feda Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/poppy/variants/nocturne: deassert audio amp resetNick Vaccaro
Drive SPKR_RST_L (GPP_A19) high at boot to take audio amps out of reset. BUG=b:78122599 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", boot to kernel, and verify sound works via "aplay /dev/random" Change-Id: Ia49931f2dc7802edc8a46114b081e4a96eeee604 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23mb/google/poppy/variants/nocturne: add touchscreen register infoNick Vaccaro
- add ACPI register information for touchscreen WCOM digitizer BUG=b:78122599 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage" and verify touchscreen on Nocturne board works. Change-Id: I9790a930e8ed2748d568ce58c931ce34b3e22007 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-22mb/google/octopus: Re-size flash WP_RO segmentSrinidhi N Kaushik
Update the size in WP_RO segment of the flash to accommodate latest FSP builds with debug. CQ-DEPEND=CL:*627827 Change-Id: Ic0eb9254421e99c8d204d8dbb86e6c6c2ec8719c Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-22mainboard/google/kahlee: Update RW_LEGACY size in fmapMartin Roth
Add the unused space to the RW_LEGACY area. BUG=b:79433466 TEST=None Change-Id: I897d1dcf75466fe9bdb814c8a9db0fecb5c42af6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-22google/kahlee: Swap UNIFIED_MRC_CACHE and RW_SECTION_A in fwmapDaniel Kurtz
The firmware_Mosys FAFT test does not allow RW_SECTION_A, RW_SECTION_B or RW_SHARED to be 0-sized, nor located at offset 0x00000000. Swap UNIFIED_MRC_CACHE and RW_SECTION_A to pass this test. BUG=b:79865447 TEST=test_that -b grunt ${IP} firmware_Mosys Change-Id: If60919fd998ac786d58a5a258d7b5ded727db64b Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-22rk3399: Enable bootblock compressionJulius Werner
This patch enables the new bootblock compression feature on RK3399, which requires moving MMU initialization into the decompressor stage and linking the decompressor (rather than the bootblock) into the entry point jumped to by the masked ROM. RK3399's masked ROM seems to be using a bitbang SPI driver to load us (very long pauses between clocking in each byte), with an effective data rate of about 1Mbit. Bootblock loading time (as measured on a SPI analyzer) is reduced by almost 100ms (about a third), while the decompression time is trivial (under 1ms). Change-Id: I48967ca5bb51cc4481d69dbacb4ca3c6b96cccea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21google/kahlee: Reduce UMA memory to 32MBMarshall Dawson
Lower the amount of UMA memory to 32MB at AMD's request. TEST=none BUG=b:79906569 Change-Id: Ib1365dc38850b4b92c944ff95534573addbe4362 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21google/grunt: Reduce UMA memory to 32MBMarshall Dawson
Lower the amount of UMA memory to 32MB at AMD's request. TEST=boot Grunt, try S3 BUG=b:79906569 Change-Id: I5af038688b38b53c94b8265823eeee0f37980522 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21mb/google/octopus: Add devicetree for BipJustin TerAvest
Bip should have different devicetree entries than Yorp; it doesn't have a DA7219 audio codec (instead it uses ALC5682). BRANCH=none BUG=b:79771967 TEST=boot, no longer see DA7219 ACPI in console. Change-Id: Ic63bbc51e122afc9fc2e8ec7fb024d18a3815b38 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/26342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>