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2021-03-22lynxpoint/broadwell: Rename LP GPIO config globalAngel Pons
Do not use the same name as the non-LP GPIO config. This allows checking at build-time that a mainboard uses the correct GPIO config format. Without this commit, there are no build-time errors when using the wrong format of GPIO config, but there would be undefined behavior at runtime. Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the USB config arrays for asrock/b85m_pro4). In both cases, building failed because the necessary GPIO config global is not defined, as expected. Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/zork: Enable SSFC as upper 32 bit of fw_configFrank Wu
To append SSFC to top 32 bits of fw_config. BUG=b:177971830 BRANCH=firmware-zork-13434.B TEST=Build coreboot and get the value of SSFC. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iab1596f1cc8fbbf45e6a9269351bf422a43f3583 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51655 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/brya: Enable S0ixSugnan Prabhu S
This change enables S0ix for brya platform. BUG=b:181843816 TEST=Built image and booted to kernel. Change-Id: Idc6f7fce9779ef4458375becebf5dc65b228abeb Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51526 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/dedede/var/storo: Add USB Port ConfigurationZanxi Chen
Add USB Port configuration into devicetree for storo BUG=b:177389444 BRANCH=dedede TEST=built firmware and verified USB3.0 function is OK Change-Id: I1527c7178ffac9b2322eb65aab6e2086d949e47c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-22mb/google/zork: Move max98357a out of baseboardEric Lai
Not all of dalboz variants support the this amp. Thus, move out of baseboard. BUG=b:182815488 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If708574f5fb18dd3b4f2ef978529a16a40d5dc0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-22mb/google/guybrush: Enable AP <-> H1 communicationKarthikeyan Ramasubramanian
Configure H1 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for H1 device and enable the required config items. BUG=b:180528902 TEST=Build Guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22mb/google/guybrush: Add initial I2C configurationKarthikeyan Ramasubramanian
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. I2C GPIOs are configured as required in CB:50091. BUG=b:180531661 TEST=Build guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I67690fbd25639879a730260aaca4cddb5e47bbc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22mb/amd/majolica: Set IOMUX to enable I2C2 & I2C3Zheng Bao
Change-Id: I142c06c150214d58acc04b8c6b3b027fff0256db Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-03-22soc/amd/common/block/i2c: Move SoC agnostic parts into commonKarthikeyan Ramasubramanian
The logic behind I2C bus initialization, I2C MMIO base address getter and setter, I2C bus ACPI name resolution are identical for all the AMD SoCs. Hence moving all the SoC agnotic parts of the driver into the common driver and just configure the SoC specific parts into individual I2C drivers. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. Verify some I2C peripheral functionality like trackpad and touchscreen. Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mainboard/: Register chipset_lockdown on xeon_sp mainboardsMarc Jones
Set chipset_lockdown in devicetree for recommended security settings. Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mb/purism/librem_cnl: Add new board/variant Librem 14Matt DeVillier
Add support for the CometLake-U based Librem 14 laptop. Change-Id: I24a2a92091cc272638ecaf8ea23a896cab8a7153 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51549 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20google/trogdor: Add new variant MarzipanKevin Chiu
This patch adds a new variant called Marzipan that is identical to Lazor for now. BUG=b:182181519,b:182018606 BRANCH=master TEST=make Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20mb/google/trogdor: Add support for SPI_FLASH_GIGADEVICExuxinxiong
Add support SPI_FLASH_GIGADEVICE for some project. BUG=b:182246432 BRANCH=trogdor TEST=emerge-strongbad and test with power on. Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: I6ab948909f4e17b4b992be6d699646f7a62bef7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-19mb/lenovo/x200: Fix boot-time docking stateKevin Keijzer
The X200 would undock itself when waking up from S3, requiring a physical reconnection before the dock would work again. Similar to 4611ad8, this reintroduces h8_mb_init() for the X200. A hook function h8_mb_init() will be called at the end of h8_enable(), in place of the ancient h8_mainboard_init_dock(). This should fix the regression the X201 and T410 also suffered from for the X200. Change-Id: Icb6dd145e56b90e0e04133810c5e9ac7b641ad68 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51123 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/scaleway/tagada: Don't change FIAMUX when Security Override is setJulien Viard de Galbert
This will not enable M.2 SATA drive if the ME config was lost (For instance after flashing a full flash factory image) This is required so that the system can boot without FIA MUX error during flash update procedure. Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19mb/google/volteer/var/elemi: Config GPP_B7/GPP_B8 as NCWisley Chen
elemi does not use the GPP_B7/GPP_B8, so config to NC. Currently, there is no functional impact. BUG=b:182981460 TEST=emerge-volteer coreboot, boot into OS, and suspend/resume successfully. Change-Id: I7b491fd595b0e77e6dcce08e3172dbe592f63c37 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19mb/purism/librem_cnl: drop MAX_CPUS from KconfigMatt DeVillier
No need to restrict this further than the platform default, and will be problematic with the addition of the upcoming 6C/12T Librem 14 board. Change-Id: I1913992ec12578e1ad3bf6bf679d1a35a46d7370 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19mb/{clevo/cml-u,system76/lemp9}: Clarify `gen2_dec` useAngel Pons
This I/O range is for a PM channel on the EC, not the PCH PMC. Change-Id: I64422e537c1edcd0673cf87f16139fb117b10e75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51604 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19nb/intel/haswell: Consolidate memory-down SPD handlingAngel Pons
Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to a struct instead of an array, and update all the mainboards accordingly. Currently, the only board with memory-down in the tree is google/slippy. Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts the channel population accordingly. Then, northbridge code reads the SPD file and uses the index that was read in `mb_get_spd_map`, and copies it to channel 0 slot 0 unconditionally. MRC only uses the first position of the `spd_data` array, and ignores the other positions. In coreboot code, `setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has to account for this. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/google/slippy: Correct memory-down SPD handlingAngel Pons
MRC only uses the SPD data for the first index, and ignores the rest. Moreover, index 1 corresponds to the second DIMM on the first channel, which does not exist on ULT (only one DIMM per channel is supported). Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge code to retrieve the serial number from the correct SPD data block. Tested on Google Wolf, both channels are still correctly detected. Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-18mb/google/brya: Implement SLP_S0_GATE signalTim Wawrzynczak
The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to provide an indication to the rest of the platform when the system is entering its software-initiated low-power state (i.e. S0ix). This lets the platform distinguish between opportunistic S0ix entry and the runtime suspend mechanism. BUG=b:180401723 TEST=abuild Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/amd/majolica: Generate OIPG PackageRaul E Rangel
This fixes the unknown reference errors for OIPG. Since Majolica doesn't actually have any of the GPIOs ChromeOS uses, we leave the arrays empty. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifeae84e0ccab187a4e7131cd6ea9e1336d79df67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51536 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Add eSPI GPIO back to init tableMathew King
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I9896db41dbe2812856357510bc4420482e73ab3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51547 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Configure UART0 gpio in early stageMathew King
BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8aa54acf1fa9295b27c33a0066432665e6e3755c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-18mb/ocp/deltalake: Initialize VPD 'coreboot_uart_io' with default value 1Johnny Lin
In case the VPD variable cannot be read. Change-Id: I79fae6f4b4aad91a4040387ca6ddee8dfcc34d90 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51559 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/mancomb: Configure eSPI GPIOs in early stageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifa51705b3b5aab16f9cd2c11084220aafacd2774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Configure early GPIOs in earliest stageEric Lai
Configure early GPIOs in verstage if it is run in PSP otherwise configure them in bootblock. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic1faeea59462319c1652c69034b4dde01669e13b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Enable internal graphics deviceEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0f5026b77513118a6c21eca78c9788c0bdc7ec6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Enable verstageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic07a3ac556637919742fcbe899ee3fdfac38bb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/zork/var/shuboz: adjust telemetry settingsKane Chen
According to stardust test tracking report to adjust telemetry setting. VDD Slope : 30518 -> 30595 VDD Offset: 435 -> 77 SOC Slope : 22965 -> 24063 SOC Offset: 165 -> 105 BUG=b:182399760 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie7e6af77bdaad6cc964ac206a69ccb854aae869f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-18mb/prodrive/hermes: Disable HDA codec Port E by default on R04+Angel Pons
If the board settings aren't valid, Port E uses the settings for earlier board revisions, which is undesired. Disable Port E by default on R04+. Change-Id: I03bd50b915a2120283b77179debaa735bb7ef027 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51529 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP initArthur Heymans
Tested with and without -enable-kvm, with -smp 1 2 and 32. Change-Id: I612cebcd2ddef809434eb9bfae9d8681cda112ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48262 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()Julius Werner
In pursuit of the goal of eliminating the proliferation of raw region devices to represent CBFS files outside of the CBFS core code, this patch removes the get_spd_cbfs_rdev() API and instead replaces it with spd_cbfs_map() which will find and map the SPD file in one go and return a pointer to the relevant section. (This makes it impossible to unmap the mapping again, which all but one of the users didn't bother to do anyway since the API is only used on platforms with memory-mapped flash. Presumably this will stay that way in the future so this is not something worth worrying about.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Replace more instances of cbfs_boot_locate() with newer APIsJulius Werner
In pursuit of the eventual goal of removing cbfs_boot_locate() (and direct rdev access) from CBFS APIs, this patch replaces all remaining "simple" uses of the function call that can easily be replaced by the newer APIs (like cbfs_load() or cbfs_map()). Some cases of cbfs_boot_locate() remain that will be more complicated to solve. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17mb/google/kukui: Add new config 'cozmo'Lucas Chen
New board 'cozmo'. BUG=b:181144502 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Ia0ec1d89444d2634bfcfb3475a422f4e4ae92b7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-17mb/google/dedede/var/sasukette: Enable ALC1015 AMP (Auto Mode) driverwuweimin
Enable gpio mode driver for ALC1015 AMP Auto Mode. BUG=b:176956779 BRANCH=dedede TEST=ALC1015Q-VB drive speaker OK Change-Id: Iaa5650e120362e81fa36530f6a207c9c07e1139a Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-17mb/google/dedede/var/lantis: Update DPTF parametersTony Huang
DPTF paramerters from thermal team. 1. PL2 =15W 2. Add TSR sensor charger, 5V regulator BUG=b:177249297 BRANCH=dedede TEST=build image and verified by thermal team. Change-Id: Ia5f6cc2a4564bb5558cbaca8daf31ee70145019f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-17mb/intel/shadowmountain: Update HDMI audio mode to 8TSugnan Prabhu S
This patch sets the HDMI audio mode to 8T as required by the latest FSP version v2081_02 TEST: HDMI audio codecs detection is failing without this change. Change-Id: Ie5a825da7d199c9ee61e64d8f4ee7dec28fdaacd Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-17mb/intel/shadowmountain: Disable xDCISugnan Prabhu S
This patch disables the xDCI which is causing PC8 to PC10 state transitions during sleep. TEST: Confirmed that the transition is happening with this change. Change-Id: I9bbf7b52c36954600d7e66f9b03fad39b8881a5f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-03-17sar: Fix semantics of `get_wifi_sar_cbfs_filename()`Furquan Shaikh
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then `get_wifi_sar_limits()` assumes that the default filename is used for CBFS SAR file. This prevents a board from supporting different models using the same firmware -- some which require SAR support and some which don't. This change updates the logic in `get_wifi_sar_limits()` to return early if filename is not provided by the mainboard. In order to maintain the same logic as before, current mainboards are updated to return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default case. Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17drivers/wifi, mb/google: Drop config `WIFI_SAR_CBFS`Furquan Shaikh
Now that SAR support in VPD is deprecated in coreboot, there is no need for a separate Kconfig `WIFI_SAR_CBFS` as the SAR table is only supported as a CBFS file. This change drops the config `WIFI_SAR_CBFS` from drivers/wifi/generic/Kconfig and its selection in mb/google/.../Kconfig. wifi_sar_defaults.hex is added to CBFS only if CONFIG_WIFI_SAR_CBFS_FILEPATH is not empty because current mainboards do not provide a default SAR file in coreboot. Thus, CONFIG_WIFI_SAR_CBFS_FILEPATH is updated to have a default value of "". BUG=b:173465272 Cq-Depend: chromium:2757781 Change-Id: I0bb8f6e2511596e4503fe4d8c34439228ceaa3c7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-16AGESA,binaryPI boards: Drop invalid MP table filesKyösti Mälkki
If we spot any error in the file, treat it as untested and broken copy-paste. Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16AGESA,binaryPI boards: Move IRQ table programmingKyösti Mälkki
IRQ programming should be done outside (obsolete) MP table generation. Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38564 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16mb/google/dedede/var/storo: Add USB Port ConfigurationZanxi Chen
Add USB Port into devicetree for storo BUG=b:177389444 BRANCH=dedede TEST=built firmware and verified USB3.0 function is OK Change-Id: I4d5160ff23d2bd386cb33164b580e6d6f3bf30fd Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Add camera supportZanxi Chen
Add camera support in devicetree and associated GPIO configuration. BUG=b:181729304 BRANCH=dedede TEST=built blipper firmware and verified camera function is OK Change-Id: I806ec207a454d4383aca093159553b7e618e16b2 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Add codec and speaker amplifier supportZanxi Chen
Add audio codec and speaker amplifier support into devicetree BUG=b:181732574 BRANCH=dedede TEST=built blipper firmware and verified audio function is OK Change-Id: Id4633649b5e0595ed99a40ae35eb54b005154604 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Enable touchscreen for blipperZanxi Chen
Add G2 and ELAN touchscreen into devicetree for blipper. BUG=b:181098785 BRANCH=dedede TEST=built blipper firmware and verified touchscreen function is ok Change-Id: Ie0bfc2972fc1a33a6f02495d3976b816209e956b Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/sasuke: Configure GPP_B7 as GPO_HIGHSeunghwan Kim
Configuring GPP_B7 as GPO_HIGH. Sasuke doesn't have SAR sensor, GPP_B7 is routed to the LTE module and is kept high so that the LTE module uses the default emission power. BUG=b:180492044 BRANCH=firmware-dedede-13606.B TEST="FW_NAME=sasuke emerge-dedede coreboot" Change-Id: Ib38c649830db2291b3a2a771f5c884acf37dcbeb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51049 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16mb/google/asurada: fix boot failure when reading SKU IDHung-Te Lin
The SKU IDs also need mapping table when reading voltages. BUG=None BRANCH=asurada TEST=emerge-asurada coreboot Change-Id: Ice91961d6c33cfa27254221663edca1547c9ddcc Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16mb/google/guybrush: Add initial fch irq routingMathew King
BUG=b:181972598 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1abb070324254e21b03bfe00d6eee3b70120564c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-15mb/google/guybrush: Enable eSPI VW SCI eventsMathew King
Guybrush does not have a dedicated SCI pin so it uses VW. BUG=b:181134664 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I12fb7c23718ad2350478b89b321e9f0aa099e53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/magolor: Fix DPTF passive and critical policiesKarthikeyan Ramasubramanian
Some of the temperature sensors defined in baseboard do not exist in magolor. With the format the DPTF policies are defined in magolor, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=None BRANCH=dedede TEST=Build and boot to OS in magolor. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I43f0b188e49e24657db055ce898ce159d499a22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15mb/google/dedede/var/madoo: Fix DPTF passive and critical policiesKarthikeyan Ramasubramanian
Some of the temperature sensors defined in baseboard do not exist in madoo. With the format the DPTF policies are defined in madoo, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=b:182513022 BRANCH=dedede TEST=Build and boot to OS in madoo. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Idc5d0b357d61b9346b4d20ec8322b124c9655b4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ben Kao <ben.kao@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-FAlexander Couzens
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in difference to the X11SSH-F which only has 2 NICs. The two additional NICs aren't populated on the X11SSH-F. Enable the PCIe root ports connected to the two additional Intel NICs. Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-15mb/prodrive/hermes: Drop AZALIA_PLUGIN_SUPPORTPatrick Rudolph
Already selected by SoC. Change-Id: I1d941881f50350b6b581416a2e722ea2e7485a1c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-15mb/google/dedede/var/sasukette: Add USB2 PHY parametersTao Xia
This change adds fine-tuned USB2 PHY parameters for sasukette. BUG=180753635 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I5612e7dcca15b340763dee1475e979ee551a2146 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15mb/google/volteer/variant/lindar: Disable SA GV for Samsung memory with ↵Kevin Chang
wrong date code MB Disable SA GV, because factory used Samsung memory with wrong date code. So we need to use board version to identify build MB phase to disable SA GV. Disable SA GV when board version equal one. BUG=b:179747696 BRANCH=firmware-volteer-13672.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/intel/tglrvp: Enable RTD3 for WWANBora Guvendik
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root Port 4 and provide the reset GPIO / src clk pin. BUG=none TEST=Boot to OS, verify the link is in L2 state during S0ix. Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2021-03-15mb/google/dedede/var/storo: Support LTE modulechenzanxi
Add LTE module support into devicetree and associated GPIO configuartion. BUG=b:177955524 BRANCH=dedede TEST=LTE function is OK Change-Id: I9aff9608e08eae00ab5ac8547f63bc83b62fea78 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15mb/google/dedede/var/storo:Add P-sensor for storochenzanxi
Add P-sensor into devicetree for storo according to configuration information provided by the vendor. BUG=b:177392203 BRANCH=dedede TEST=built storo firmware and verified P-sensor function Change-Id: Iced4ab7d94b38ef8b1807955cbb887454accb1e8 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-03-15mb/google/dedede/var/storo: Add codec and speaker amplifier supportchenzanxi
Add audio codec and speaker amplifier support into devicetree BUG=b:179057895 BRANCH=dedede TEST=audio function is OK Change-Id: Ia864ac47223adb80463966209f6ff3640b715378 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51003 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/storo: Add camera supportchenzanxi
To support mipi camera. 1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU 2. add IPU/VCM/NVM/CAM1 into devicetree To support usb camera. add camera support in devicetree and associated GPIO configuration. BUG=b:177393430, b:177388006 TEST=Build and boot to OS. Camera function is OK. Change-Id: I98d5708d1955406c2e46db972903057bb3d12dcc Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50995 Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/lenovo/t440p: update VBT to version 2179Da Lao
Update T440p's VBT from version 1215 to version 2179. Extracted using VBiosFinder (https://github.com/coderobe/VBiosFinder) from the latest bios update file: https://download.lenovo.com/pccbbs/mobiles/gluj42us.iso The new version solves the problem that DP output was broken under Windows. Test: boot t440p with both SeaBIOS and Tianocore payloads, verify dp output and backlight control all works under both Linux and Windows. Signed-off-by: Da Lao <dalao@tutanota.com> Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jamal Wright <Crabstorage@getbackinthe.kitchen>
2021-03-15mb/intel/tglrvp/variants: Disable non-existing BT PCI interface and add BT flagCliff Huang
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is enumerated. Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/volteer/variants: Disable non-existing BT PCI interface and add BT ↵Cliff Huang
flag Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is enumerated. Change-Id: Ic700021d7a09be63ffc2715f31992257e2e893af Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50898 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/hatch: Update DPTF parameters for genesisKenneth Chan
update the DPTF parameters received from the thermal team. BUG=b:181627614 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ied6b71d9285662a70446af2e781b630e184c3b19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joe Tessler <jrt@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15mb/google/brya: Remove BT PCI interface and add BT flagCliff Huang
Remove the CNVi BT PCI config and add Bt flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: I7e8ca1bb6a57721a72478137612d7a9c391ca0b2 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flagCliff Huang
Remove the CNVi Bt PCI config and add Bt flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/ocp/deltalake: Override uart base address via VPD variableBryant Ou
Use VPD of "coreboot_uart_io" to select uart io if OVERRIDE_UART_FOR_CONSOLE is selected. Tested=On OCP Delta Lake, console messages correctly output to uart port which is defined in VPD. Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/45408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-03-15mb/google/volteer: Create collis variantFrankChu
Create the collis variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:182227204 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_COLLIS Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ibcf8b59b38d02517cea0a3ee474ff82fc0a2a958 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-15mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUsMeera Ravindranath
Add support to pick the right vbt from cbfs according to SKU-ID. Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/ocp/deltalake: Override SMBIOS type 2 feature flagsTim Chu
Override SMBIOS type 2 board feature flags. For Delta Lake, board is replaceable and is a hosting board. Tested=Execute "dmidecode -t 2" to check info is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I4469360ec51369dbf8179b3cbac0519ead7f0382 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-03-15mb/google/mancomb: Configure non-native function GPIOsEric Lai
Follow 20210308 schematic. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib259f3defc606c373f5ccac5f022d93e9a5c1469 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15mb/google/mancomb: First pass GPIO configurationEric Lai
Follow 20210308 schematic. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1720ea8fec004d3ed3b3faaffa3b37dfcd710241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15rammus: get cbfs sar table name based on the sku idZhuohao Lee
This patch overrides the get_wifi_sar_cbfs_filename() to return different sar table according to the sku id. BUG=b:173465272 TEST=checked bios log and the correct sar table was loaded. Change-Id: Ia30d760b1a029197d470818c73bfd2c00514652d Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/google/volteer/variants/copano: Add gpio-keys ACPI node for PENHhao_chou
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:175519097 BRANCH=firmware-volteer-13672.B TEST=build and verify on a Copano Change-Id: Id0a132aa398abde4983af123d00e355ac61839a8 Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51249 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/intel/shadowmountain: Add ACPI entry for BT reset GPIOAamir Bohra
Change-Id: Ia9e57f34eceaf1925dc5e3ffa6370ba0241447a4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-03-15mb/google/volteer: Add WiFi SAR table support for Lindar/LillipupKevin Chang
Lindar/Lillipup uses the WIFI_SAR_ID field in FW_CONFIG to pick which SAR table to load. BUG=b:178302811 BRANCH=volteer TEST=build and test no lindar/lillipup Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ibe829062033ba8246b9d9550cdcdc360f5f67dd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2021-03-15mb/google/volteer/var/lindar: Add FW_CONFIG WIFI_SAR_ID fields in devicetreeKevin Chang
Add FW_CONFIG WIFI_SAR_ID fields in devicetree. BUG=b:178302811 BRANCH=volteer TEST=build and test on lindar/lillipup Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I7ec37b80ffca6924f1f0952dcfbc43c378a70923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51386 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/octopus/var/fleex: Add RTL5682 supportEric Lai
Fleex will use SSFC to support RTL5682. BUG=b:178653122 TEST=abuild Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icb06eabe297c5562bd2171b52cc9671c342e6dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/51423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-03-15mb/google/dedede/var/sasuke: Update LTE GPIO configurationSeunghwan Kim
Update GPP_A10 and GPP_H17 configuration to meet LTE power sequence specification. - FCPO (GPP_A10) should not turned off during warm reset. BUG=b:177177967 BRANCH=dedede TEST=Verified LTE power signal waveforms during powering on and off Change-Id: I469f9c94ebd6bf2b68a0edc74f229158d82d0ef8 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15mb/google/kahlee: remove get_gpe_tableFelix Held
Since no board overrides the weak get_gpe_table function, gpe_configure_sci wasn't called for any variant, so drop the function. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de204cc808449b625e1fa1e79fe653608e4b88a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCESTim Wawrzynczak
This change select the Kconfig to pre-allocate the Intel-recommended bus and memory resources per-PCIe TBT root port for the adlrvp mainboard. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/brya: Select ADL_ENABLE_USB4_PCIE_RESOURCES for brya0Tim Wawrzynczak
This change select the Kconfig to pre-allocate the Intel-recommended bus and memory resources per-PCIe TBT root port for the brya0 mainboard. TEST=snippet from dmesg logs shows the correct resources being allocated: PCI: 00:07.0 resource base 27fc00000 size 1c000000 align 20 gran 20 limit 29bbfffff flags 60181202 index 24 PCI: 00:07.0 resource base 83000000 size c200000 align 20 gran 20 limit 8f1fffff flags 60080202 index 20 PCI: 00:07.1 resource base 29bc00000 size 1c000000 align 20 gran 20 limit 2b7bfffff flags 60181202 index 24 PCI: 00:07.1 resource base a0000000 size c200000 align 20 gran 20 limit ac1fffff flags 60080202 index 20 PCI: 00:07.2 resource base 2b7c00000 size 1c000000 align 20 gran 20 limit 2d3bfffff flags 60181202 index 24 PCI: 00:07.2 resource base ac200000 size c200000 align 20 gran 20 limit b83fffff flags 60080202 index 20 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6b520ae50f19a730263de7918594718f3b4b1c1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51455 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/blipper: Enable touchpad supportZanxi Chen
Add touchpad into devicetree for blipper. BUG=b:172787208 BRANCH=dedede TEST=built blipper firmware and verified touchpad function the kernel log: found RMI device, manufacturer: Synaptics Change-Id: I2c9b61ba9d282f994e2f756bafe4af1091d4d617 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51188 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15Revert "mb/google/zork: restore stamp_boost parameter to 2500 for dirinboz"Kevin Chiu
This reverts commit 87a1bd696d47f80101e46132efae8cad8cfe5c7e. Reason for revert: skin temperature is overheating due to boost time is too long BUG=b:175364713 TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I31db06f4bcb986398e7bd2ac2858ffbedb257e2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-03-15mb/google/asurada: get SKU ID from AP strapping pinsHung-Te Lin
The SKU ID for Asurada should come from AP ADC channel 5 and 6. BUG=None TEST=make; boots on asurada Change-Id: I6a00c555f20aca4cd7f8bcee46ee81c17ef6ca3c Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-15mb/google/asurada: revise PMIC and RTC initializationYidi Lin
Move the initialization from bootblock to romstage for following reasons: - Follow MT8183 initialization sequence. - PMIC and RTC functions are only called after verstage. - Reduce bootblock size. - PMIC initialization setting is complex and may need to be changed by an RW firmware update. TEST=boot to kernel successfully Change-Id: I3e4c3f918639590ffc73076450235771d06aae91 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xi Chen <xixi.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-14mb/google/guybrush: Enable PCIe devices in devicetreeMathew King
BUG=b:181690884 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8ceeb8db24be34588b370c13d865753f095e4be6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-14mb/google/guybrush: Add SPDs into buildMartin Roth
This enables the standard library method of adding SPDs to CBFS. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51022 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14mb/google/guybrush: Enable EM100 support on guybrushMathew King
Add the option to build guybrush firmware with support for EM100. This will assist in bringup of the new board. BUG=b:180723776 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I2246d2952f341cd8fff8fd486cf989cdb7929411 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51071 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUMERaul E Rangel
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Add guybrush APCBs into buildMartin Roth
This adds the Guybrush APCBs into the AMD firmware binary. BUG=b:182510885 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iba40cab1d68e9f8d7291e7d715be185a3b6249f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-13mb/google/guybrush: Add ACPI support for Chrome ECMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Icb8aba87390475cad7a2a9911c3832a59c987b65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13mb/google/guybrush: Configure eSPI GPIOs in early stageMathew King
BUG=b:181961514, b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I0d22de977f09cbf46b28243d9f0c1e9a36e1398f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51295 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Configure early GPIOs in earliest stageMathew King
Configure early GPIOs in verstage if it is run in PSP otherwise configure them in bootblock. BUG=b:181961514, b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib9410089592776ffe198901f2de914fd04bdbade Reviewed-on: https://review.coreboot.org/c/coreboot/+/51348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13mb/google/guybrush: Enable verstageMathew King
BUG=b:181961514 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I289a2ad1adc5dcc33c5863d6138f66b9b6dc6590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-12mb/google/dedede/var/boten: Increase Goodix touchscreen reset delay to 180 msStanley Wu
1. Follow GT7375P Programming Guide_Rev.0.6 to increase reset delay to 180ms. 2. Add TOUCH_RPT_EN pin(GPP_A11) control to fix TOUCH_RPT_EN pin keep high after system suspend. BUG=b:181711141 TEST=Build and boot boten to OS. Confirm TOUCH_RPT_EN pin keep low after system suspend. Change-Id: I98efbe68dab538906802647582eba0e068d9c11f Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51254 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12mb/google/dedede/var/boten: Configure I2C5 p-sensor high and low timeStanley Wu
Configure I2C bus 5 high and low time for p-sensor device. BUG=b:181727056 TEST=Measured the I2C bus frequency reduce to 387 KHz. Change-Id: I4b6d78d84b8ea145093f52bbb13684e2c6aa979c Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-12soc/intel/braswell: Factor out common `acpi_fill_madt`Angel Pons
Function is identical for all mainboards, so factor it out. Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>