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2021-08-02mb/google/brya: Configure H21 as GPO and A17 as lowVarshit B Pandya
As per the schematics, UFC has on card oscillator so we donot need H21 in NF1 that is IMGCLKOUT H21 is used to enable this oscialltor so configuring it as 1 A17 is configured as high while _ON method is called by driver and it is configured as low when _OFF method is called by driver. Hence coreboot should configure it as low on boot. BUG=b:190674542 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56655 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/google/dedede/var/cappy2: Disable external bypass VRSunwei Li
The cappy2 removed the anpec apw8738bqbi and "disable_external_bypass_vr" should be set to "1" to disable BUG=b:194146867 BRANCH=dedede TEST=VCCIN_AUX is disable Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ieb4182a989459db629e3b69757c293ca26e8b0cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/56687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2021-08-02mb/google/dedede/var/cappy2: Add Tpm2.0 device supportSunwei Li
Using Tpm2.0 device instead of the Cr50 in cappy2 BUG=b:191743435 BRANCH=dedede TEST=tpm2.0 device function is ok Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I216ceb6386ad57c9f1982187a4525d89869fa9c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56658 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31mb/google/dedede/var/boten: Set the xHCI LFPS period sampling off time to 0msstanley.wu
LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:187801363 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.corp-partner.google.com>
2021-07-30mb/google/brya/variants/primus: Disable PCIe6Malik_Hsu
WWAN (fibocom L850-GL) works in USB mode, so turn off PCIe 6. BUG=b:194861116 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: Ie04a5bb2af9ce11f57339f460a7f880bfc14b688 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-29mb/google/dedede/var/cappy2: Add I2C devicesSunwei Li
Add tp and audio devices support in devicetree. BUG=b:193099842 BRANCH=dedede TEST=i2c devices function is OK Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I995e93b5a4c4294d6f6b97c48d14fabf48004d92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56513 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/google/brya: add BASEBOARD_DIR to support different baseboardZhuohao Lee
In order to support different baseboard configuration, we add the BASEBOARD_DIR to switch the directory. The expected structure looks like: mb ..|_ google .........|_ brya .............. |_ variants .....................|_ baseboard ..............................|_ brya ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ..............................|_ brask ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ......................|_ brya_variant1 ......................|_ brya_variant2 ......................|_ ... ......................|_ brask_variant1 ......................|_ brask_variant2 ......................|_ ... ...............|_ <all mb common code> BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ic99e42dbbd27fa3e1f6cb3a1b5daee1c8c7b1083 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-29mb/google/dedede: Configure VCCIOSEL for EN_SPKR GPIO PadKarthikeyan Ramasubramanian
Realtek speaker amplifiers under auto mode operation have Absolute Max Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker amplifier and program the VCCIOSEL accordingly. BUG=b:194120188 TEST=Build and boot to OS in Storo. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: Ibd3bc90bd0bbc9a35922b29e3d1e106321bc7a06 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56616 Reviewed-by: Evan Green <evgreen@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Disable LTR for all PCIe root portsWerner Zeh
Latency Tolerance Reporting is yet another PCIe power management feature which can have a bad influence on realtime performance. Disable this feature for all PCIe root ports. Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-29mb/siemens/mc_ehl1: Disable L1 substates for PCIe root portsWerner Zeh
L1 substates of a PCIe link are meant to save some power when the link is not active but have the drawback that the PCIe latency is increased as PLLs are switched on and off as needed. In order to get a better realtime performance, disable all substates for every PCIe root port. Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-29mb/siemens/mc_ehl1: Enable Intel I210 MACPHY driverWerner Zeh
This variant uses I210 MACPHYs so enable the I210 driver in order to set the needed MAC addresses. In addition add the function to retrieve a valid MAC address for the given MACPHY. Change-Id: Id1d59349db1b86cfdd71bbe27577c0530e8f0b51 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56567 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable Siemens NC-FPGA driverWerner Zeh
All the boards based on the mc_ehl baseboard have the NC-FPGA available. Enable the appropriate driver on baseboard level. Change-Id: I40b76a837b7ddb70ceba3135996b1c1080170c4d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56566 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable SIEMENS_HWILIBWerner Zeh
All variants based on mc_ehl will use the Siemens HWILIB. Select the Kconfig switch on baseboard level. Change-Id: I940f84a4a7449487fe78c793f8dbb1c1b49fa54b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56565 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Enable In Band ECCWerner Zeh
Enable IBECC for mc_ehl1 to provide a memory failure protection. Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56564 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Disable System Agent dynamic frequency supportWerner Zeh
In favor of better realtime performance disable dynamic frequency support in the System Agent for mc_ehl1. Change-Id: I0e62bcf2e5efa97d89bf7192f1536747a02ad992 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56563 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable measured bootWerner Zeh
Enable measured boot for all boards based on mc_ehl baseboard. Change-Id: I3aff943305c024d1f25d2127e6f60495828da3eb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-29mb/siemens/mc_ehl: Enable LPC TPMWerner Zeh
All the boards based on the mc_ehl baseboard have a TPM which is connected to SPI but mapped into the address space of the x86 so that it acts like a LPC attached TPM. Enable the TPM driver so that it will be used. In addition add the needed entry in devicetree. Change-Id: I301d0ed4a108bac45d95eced120e7ba280945d9c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-29mb/siemens/mc_ehl: Add external RTC RX6110SAWerner Zeh
All the mainboards based on mc_ehl use the external RTC RX6110SA. Enable the driver in Kconfig for all boards based on mc_ehl. In addition, as mc_ehl1 has the RTC attached to the SMBus, add the devicetree entry on behalf of the SMBus device 00:1f.4 for this variant. Change-Id: Ie1f45d0e6f9063c00253fe58a6268d40de91cf63 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56523 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/google/dedede/var/storo: Set the xHCI LFPS period sampling off time to 0msTao Xia
LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:193898133 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ic84dc83b749cf3c6029a06730096b64ef8cb8cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-29mb/google/dedede/var/pirika: Configure I2C times to 380-400 kHz for touchpadAlex1 Kao
Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Audio codec:388.91 kHz Touchpad:394.48 kHz BUG=b:193864546 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: Ia57c90ead44ceb0990878dc0566e595bae5a9099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56383 Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/intel/ehlcrb: Select LPSS console by defaultLean Sheng Tan
Select `INTEL_LPSS_UART_FOR_CONSOLE` to allow using PCH UART 2 as coreboot console. Also, simplify `UART_FOR_CONSOLE` defaults. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I853777116fc541e5dc31f3ca8673f8bf66c7c9e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28mb/google/brya/var/kano: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B H54G46CYRBX267 H54G56CYRBX247 K4U6E3S4AB-MGCL K4UBE3D4AB-MGCL BUG=b:194766276 b:194686484 b:194765811 TEST=build Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iba019c50224be8322865eee7baf81e3a574ff9a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-28mb/google/volteer/variants/drobit: Add Charger Performance Control table ↵Wayne3 Wang
TCHG for DPTF setting. Add Charger Performance Control table TCHG for DPTF setting. BUG=b:194256990 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by thermal team. Change-Id: I9dba3f0e75d07d8ee9656bd1ee8d6de2d3b8c152 Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Paul F Yang <paul.f.yang@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
2021-07-28mb/google/brya/variants/primus: Update NVMe clkMalik_Hsu
According to the schematic diagram of proto, modify the clock of nvme from the baseboard default to src0. BUG=b:194487277 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I41be517b434513bca2332ec37e54f56910302bb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-28Revert "mb/google/dedede: Program VCCIO selection for EN_SPKR GPIO"Karthikeyan Ramasubramanian
This reverts commit ce79ceec86a38145b3a27aa4c78cf83a76cd51d0. This has introduced a regression in mainboards using JSL SoC such that it overrides the soft straps for all the GPIOs. This in turn has led to some of the peripherals not working. Change-Id: Ifea5d4d0f474873f8bf4818ec1986e534f455216 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56615 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28ec/roda/it8518/acpi: Don't hard-code GPE offsetNico Huber
The GPE offset of 16 is PCH specific. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I4ec38fc28d2436f84a090bb4ab38f20612cfd795 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28mb/google/dedede/var/magolor: Add custom Wifi SAR for magisterDavid Wu
Add wifi sar for magister. Due to fw-config cannot distinguish between magolor and magister. Using sku_id to decide to load magister custom wifi sar. BUG=b:192290227 TEST=build and test on magolor/magister Cq-Depend: chrome-internal:3986580 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4510cc2ad42a11ec802ecd439b353f8e87d63868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28mb/google/dedede/var/sasukette: Set the xHCI LFPS period sampling off time ↵Tao Xia
to 0ms LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:191426542 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I3be7adad49f87956a6764ad91fec6e76681b393f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chiasheng Lee <chiasheng.lee@intel.com>
2021-07-28mb/google/volteer/var/collis: Update DPTF parameters for DVT buildFrankChu
Update Passive Policy and TCHG parameters. BUG=b:188936764 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Id75bfa74ba353f2342c95bcf8d73cd83c957deb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56512 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `OVERRIDE_DEVICETREE` onceAngel Pons
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/intel/galileo: Clean up `FMDFILE` Kconfig handlingAngel Pons
Remove redundant type, prompt and help text, and replace `depends on` clause with conditional default to allow specifying a FMAP when vboot is not selected. Change-Id: I37ddab3a27e304e810ea55f13821d755bb70cb4b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56551 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/facebook/monolith: Don't override `CBFS_SIZE` promptAngel Pons
Change-Id: I6fac40918f1ca3227ff68e79fcae039a26356d0d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56550 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/brya: Deduplicate chipset lockdown configFelix Singer
Due to an issue in sconfig, move `chipset_lockdown` out of `common_soc_config` and configure it separately in the baseboard's devicetree since it might get overwritten if a variant configures `common_soc_config`. Also, deduplicate the configuration of `chipset_lockdown`. Change-Id: Id969346df06aa82ab2ad2b1aa4884a9bcd876d75 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56408 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/intel/coffeelake_rvp: Use CHIPSET_LOCKDOWN_COREBOOTFelix Singer
Currently, internal flashing is not possible due to FSP lockdown. Thus let coreboot do chipset lockdown on all variants. Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/dedede: Program VCCIO selection for EN_SPKR GPIOKarthikeyan Ramasubramanian
Realtek speaker amplifiers under auto mode operation have Absolute Max Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker amplifier and program the VCCIOSEL accordingly. BUG=b:194120188 TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: Ifa0b272c23bc70d9b0b23f9cc9222d875cd24921 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26mb/google/dedede/var/pirika: Add USB2 PHY parametersAlex1 Kao
This change adds fine-tuned USB2 PHY parameters for pirika. BUG=192601233 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: Icf9fb41cd0ae40728e4ec5bd72a15ec3c45c963b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26mb/google/dedede/var/cappy2: Generate SPD ID for supported memory partsSunwei Li
Add supported memory 'K4U6E3S4AA-MGCR' for cappy2 BUG=None TEST=Build the cappy2 board. Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ie76a4dca607bb2c3261bbe5478209a43e8430591 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26mb/asus/p5ql-em: Add default value for `gfx_uma_size`Angel Pons
Taken from Asus P5QPL-AM. Change-Id: If26e98eba5d762d99991bfc06cad1b84e1f430e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56562 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26soc/intel/jasperlake: Set xHCI LFPS period sampling off timeBen Kao
Provide an option to set xHCI LFPS period sampling off time (SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0). If the option is set in the devicetree, the bits[7:4] in xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated. The host will sample LFPS for U3 wake-up detection when suspended, but it doesn't sample LFPS at all time due to power management, the default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS period sampling off time is not 0ms, the host may miss the device-initiated U3 wake-up and causes some kind of race condition for U3 wake-up between the host and the device. BUG=b:187801363, b:191426542 TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash the image to the device. Run following command to check the bits[7:4]: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Ben Kao <ben.kao@intel.com> Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26mb/google/brya: move the common config to the baseboardZhuohao Lee
This patch moves the common config to the Kconfig under BOARD_GOOGLE_BASEBOARD_BRYA and removes the redundant config. BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ie59299dfaba6bb23758d4a4c22a6dbbb4ba6520e Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56387 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/brya: Enable BT offload conditionallySugnan Prabhu S
Currently, BT offload is disabled/enabled unconditionally based on the devicetree settings. BT offload uses I2S lines and cannot be enabled when a I2S based audio daughter card is active. So we need to enable BT offload only while using soundwire based audio daugther card. BUG=b:175701262 TEST=Verified BT offload on brya with soundwire audio daughter card BT offload enabled Change-Id: I6a9ad463e13e2cfcfc3b7de5a61a25cdef0641f7 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-25mb/razer/blade_stealth_kbl/Kconfig: Fix up indentationAngel Pons
Change-Id: I0ffae7408f11f4f517204a0a670845c11b3601a8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56549 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24soc/amd/*/chip.h: Correct PSPP Enum ValueMatt Papageorge
It appears the pspp_policy enum is not the same as the FSP definition currently being used. This means that the incorrect PSPP value setting would get read by FSP. For Zork programs this meant we actually were setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE. This change adds DXIO_PSPP_DISABLED as the first enum value to properly match the FSP definition and adjusts non AMD Customer Reference Boards that reference the enum to still send the same value even though it has now change definitions. If we actually want DXIO_PSPP_POWERSAVE for those boards that can be adjusted in a future change. BUG=b:193495634 TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi with other server on local network. Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-07-24mb/google/guybrush: Update GPIOs settingsMartin Roth
- The WWAN card was being disabled later than desired. - The SD card was never being placed into reset on BoardID 1. - Enable Touchscreen power - Enable PCIe_RST1 at the same points as PCIe_RST - Remove Redundant Bootblock settings BUG=b:193036827 TEST=Build & Boot, look at GPIO states through boot process Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5431da755d98e4ad0b300d01cac562d61db0bc08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-23soc/amd/stoneyridge/fch: change sb prefix of sb_clk_output_48Mhz to fchFelix Held
Stoneyridge has an integrated FCH and no south bridge, so change the sb prefix to fch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23herobrine: get boardid from GPIO configurationRavi Kumar Bokka
Getting boardid information for the different SKU variants BUG=b:182963902, b:193807794 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I2b7625f9b98563438d1ac20e6f29411ef1058cf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-23mb/siemens/mc_ehl1: Add GPIO configurationWerner Zeh
Provide a valid GPIO configuration based on the mainboard wiring. Change-Id: I36f0e8292a405b4bac74fbc5fde62e5e414387e7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56519 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23mb/siemens/mc_ehl1: Remove SD-Card card detect GPIO in devicetreeWerner Zeh
Since there is no SD card interface on this mainboard do not set the card detect GPIO. Change-Id: Ibe6799c5c540538f97d1726ec16e79f3edbb16fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56489 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23mb/siemens/mc_apl{1,2,3,5,6}: Use PCI_ALLOW_BUS_MASTER_ANY_DEVICEWerner Zeh
Use the Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE instead of PCI_ALLOW_BUS_MASTER to enable PCIe bus master bit as requested in CB:56441 during review. Change-Id: I433dbae0d9b15e41d1d0750298868341ce3d6b46 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-23mainboard/up/squared: Add one more DRAM configurationFlorian Laufenböck
Add a new configuration option with more density for 8GB variants of the up squared board. Settings are taken from slimbootloader. Signed-off-by: Florian Laufenböck <florian@laufenbock.de> Change-Id: I217b04be94e913b75e2bac0a4ae1c43f2411a044 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-07-23mb/google/veyron: Remove references to EC firmware board namesPatrick Georgi
Chrome EC is relatively quick with retiring "old" boards from their tree so when upreving it, the last veyron in that list that wasn't commented out is gone as well. Change-Id: Ie1ef693c8d0947396ee01e5aa5f40ef36c8a317a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56430 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23mb/google/cherry: replace magic numbers by the I2C bus nameRex-BC Chen
When accessing I2C, we should use the official names (I2Cx) instead of magic numbers. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I17cc4c87f5ad26deeb5e529d1c106b697a53591b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56504 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mb/google/guybrush: Setup EC_IN_RW GPIO and export to payloadKarthikeyan Ramasubramanian
EC_IN_RW_OD signal is routed from Google Security Chip to GPIO_91 in the upcoming hardware build. The existing SD_EX_PRSNT signal is dropped in the upcoming hardware build because SD7 support is dropped. Export the EC_IN_RW GPIO for use by payload. BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the device can boot successfully in both recovery and normal mode. Cq-Depend: chromium:3043702 Change-Id: I8986ba007a2d899c510be61664d90430b8d2d384 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56493 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mb/siemens/mc_ehl1: Disable GSPI in devicetreeWerner Zeh
Since this mainboard does not use GSPI at all, disable all GSPI ports. Change-Id: I60254e9f4047537d86c972151ec9e33552332959 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-22mb/siemens/mc_ehl1: Adjust I2C bus enablement in devicetreeWerner Zeh
This mainboard uses I2C1 and I2C4 buses only. Disable all the others as they are not connected at all. Change-Id: I4743f6ea6b9a9987ad63b60f56ee9a597a08284b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-22mb/siemens/mc_ehl1: Disable power management features for SATAWerner Zeh
Features like DevSLP and Aggressive Link Power Management are not supported on this mainboard and are therefore disabled. Change-Id: I3bc650ea78be8587889fb7abfe7075cd9a122198 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-22mb/google/dedede/var/cret: Add Wifi SAR for cretIan Feng
Add wifi sar for cret. BUG=b:194163601 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ic2f3dbc5822c1f4b1c935c87295ba9916e0e359e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-22mb/siemens/mc_ehl1: Adjust PCIe settings in devicetreeWerner Zeh
This board does not use CLKREQ-signaling for PCIe, so disable the pin assignments. In addition only three clock outputs are used for PCIe, therefore disable all others to improve EMI. Change-Id: I545f890fa55a109df7f44d2c82170874fb769009 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56455 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mb/siemens/mc_ehl1: Adjust USB port settings in devicetreeWerner Zeh
There are in total three USB ports that are used on mc_ehl1: - Port 1: Type A connector connected to USB2/USB3 port 0 - Port 2: Type A connector connected to USB2/USB3 port 1 - Onboard: connected to USB2 port 2 None of the ports supports overcurrent reporting. Adjust the appropriate UPDs in devicetree to match the hardware configuration. Change-Id: I220637b8e9f03efccacd0955e82cfc0c7a6f53ee Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56454 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mb/siemens/mc_ehl1: Remove display related UPDs from devicetreeWerner Zeh
Since mc_ehl1 does not have a display attached nor have a display connector available (pure headless design), remove display related settings from the devicetree. Change-Id: Id31c09fcfba15f55eed19134bd0c2fb887bd2478 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56453 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mb/google/brya/variants/redrix: Configure GPIOs according to schematicsWisley Chen
Update initial gpio configuration for redrix BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I2294fb3bdba832677038cfe24b5014014c7f03e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56428 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mainboard/google/herobrine: Add configuration for SD card detect pinShaik Sajida Bhanu
Without this configuration, even though there is no SD card it shows as SD card is present and host controller waits for card to respond. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board with SD card and without SD card, make sure if SD card not present then host controller should not wait for card to respond. Change-Id: I5dc5ba10c98d606d98e7d4f4c41c3e4f45e94452 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-21mb/google/brya/variants/primus: Update two GPIOsariel fang
1. Move M2_SSD_PLN_L to GPP_D3 for power loss notify function. 2. Set GPP_E21 as NC to remove LCLW_DET function BUG=b:190643562 Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: Id3c60adeb5d35c79a1c700937f93a80ad3587c5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56420 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya: Program Unused Cnvi BT related GPIOs to NCMaulik V Vaghela
Program unused Cnvi BT UART GPIOs as NC since we are using Bluetooth over USB mode for Brya. Change-Id: I33a37ceb8a91603d2a193de5bdd1b6885eb3c319 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55317 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya: Create taeko variantKevin Chang
Create the taeko variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:193685558 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TAEKO Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: If738849bc3103c52a4c4d8a8aaef3f90a62ad5c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56385 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya/var/gimble: Include SPD for MT53E1G32D2NP-046 WT:A and ↵Mark Hsieh
K4U6E3S4AA-MGCR Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:A and K4U6E3S4AA-MGCR. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4bfc18fd42c6ff2675e6f836c2ecc9617fac3aff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56329 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/siemens/mc_apl{1,2,3,5,6}: Set PCI bus master bit only if allowedWerner Zeh
Take Kconfig switch PCI_ALLOW_BUS_MASTER into account and set the PCI bus master bit for legacy devices only if it is allowed. Change-Id: I7798a767d528419bb093f301140ab68cc8b9c5ae Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-21mb/google/brya: Add variant specific soc chip config updateSugnan Prabhu S
This patch adds support for variant specific soc chip config update function. Change-Id: Ic3a3ae0b409433e6dfa102c5e7a6322d4f78f730 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-21mb/google/octopus/variants/ampton: Resume from suspend on critical batteryJames Chao
This patch makes Ampton EC wake up AP from s0ix when the state of charge drops to 2%. Demonstrated as follows: 1. Boot Ampton. 2. Run powerd_dbus_suspend. 3. On EC, run battfake 2. 4. System resumes. BUG=b:189540432 BRANCH=Octopus TEST=Verified on Ampton. Change-Id: I98d8e6ea185e8782ad675d4668678b341ca5d350 Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56341 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya/variants/primus: add dram part idMalik_Hsu
This change adds mem_parts_uesd.txt that contains the new memory parts used by primus and Makefile.inc generated by gen_part_id.go using mem_parts_used.txt. BUG=b:193813079 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I6aa37114f3a164a4f3c35dfc9b43e1106b825bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-21mb/google/herobrine: Retrieve SKU ID from ECPhilip Chen
BUG=b:186264627 BRANCH=none TEST=build herobrine Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Id3faf7af64c0129ec646a01085adc43b561225d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-21mb/google/cherry: add mt6360 support for MT8195Rex-BC Chen
For new MT8195 devices we will control mt6360 via EC, so we have to add ec function of controlling MT6360 and add CONFIG to separate them. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic2228f5b45173f0905ea66a3a1f00ec820e0f855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-21mb/google/cherry: initialize SD card reader using regulator interfaceRex-BC Chen
TEST=boot kernel from sd card pass on Cherry board. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic20a2f3f053130ded202cf5ec861450f0f18eed0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56437 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/intel/ehlcrb: Update FIVR configsLean Sheng Tan
This patch sets the optimized FIVR configs for ehlcrb customized based on the performance measurements to achieve the better power savings in sleep states. - Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5 states. - Update the supported voltage states. - Update max supported current, voltage transition time and RFI spread spectrum. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/cherry: add mt6360 ids for regulator.cRex-BC Chen
Add MTK_REGULATOR_VCC and MTK_REGULATOR_VCCQ for regulator.c. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iedb1036da3c87106157c51cc46b52545faba102c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56436 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21soc/mediatek/mt8195: modify mt6360 interfaceRex-BC Chen
With the new definition of mt6360_regulator_id, merge the MT6360 LDO and PMIC interfaces into one. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7ccc32cb0a9481d5f55349c152267a44fe09d20a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-21soc/mediatek/mt8195: redefine mt6360_regulator_idRex-BC Chen
On MT8195 platforms with BC1.2, we have to use EC to control MT6360 so the mt6360_regulator_id is redefined to match the numbers defined in EC driver. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9437edb9776442759ce04c31d315c3760078ffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56434 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/intel/adlrvp: Enable I2S audio codecs on ADL-M RVPAnil Kumar
- Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: If2649647e58c5f30e2b539d534adf2a4e68f4fda Reviewed-on: https://review.coreboot.org/c/coreboot/+/52221 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21Revert "mb/google/brya: Enable south XHCI ports 1 and 2"Tim Wawrzynczak
This reverts commit f7f715dff38c4a629139b2493ed6e0d7cc2eb36f. Reason for revert: FSP 2207.01 uses the UsbTcPortEn UPD for TCSS XHCI enable BUG=b:184324979 TEST=boot brya, all 3 USB Type-C ports still enumerate devices Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56132 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-20mb/siemens/mc_ehl: Move SPD data to variant directoryWerner Zeh
Since the variants can have different memory move the SPD related content to the variant directory. Change-Id: I38aa5e7514437bfcc61c38d64f0ba6f19350810d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56036 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-20mb/google/volteer/variants/collis: Fix pen ejection eventFrankChu
Modify PENH device GPIO GPP_E17 for pen ejection event. BUG=b:192511670,b:193093749 BRANCH=firmware-volteer-13672.B TEST=test pen insert and remove by evtest , SW_PEN_INSERT value 1 when insert pen to pen slot. SW_PEN_INSERT value 0 when remove pen from pen slot. Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ida5e5b35464471a7896cef392e178a3d2c0ea1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-07-19grunt/treeya: add Realtek ALC5682 codec supportKevin Chang
Replace audio codec from DA7219 to Realtek ALC5682. Add Realtek ALC5682 support. BUG=b:185972050 BRANCH=master TEST=check on treeya system ALC5682 audio codec is working normally. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-19mb/{google, intel}: Make use of `cpu/intel/cpu_ids.h'Subrata Banik
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated cpu_ids.h file in SoC directory. Change-Id: I411f4f2c237a9e2d39038ee30f2957698ee053bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-17mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:BFrank Wu
Add new ram_id:1000 for memory part MT40A1G16RC-062E:B. BUG=b:193732051 TEST=Generate new spd file and build coreboot. Then boot from the DUT with new memory MT40A1G16RC-062E:B Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56328 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) siliconSridhar Siricilla
The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is enableda on the system. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-17mb/google/volteer: Deduplicate lockdown configFelix Singer
The setting `chipset_lockdown` has the same configuration for all variants and they also match with the baseboard configuration. Thus, remove it from the variant overridetrees. Built google/delbin with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56199 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17mb/google/volteer/baseboard: Configure chipset_lockdown separatelyFelix Singer
The configuration of the setting `chipset_lockdown` doesn't have any effect for most of the variants since their configuration of `common_soc_config` overwrites the configuration of the baseboard's devicetree. If `chipset_lockdown` is configured separately in the baseboard devicetree, the variant overridetrees reuse its configuration. Thus, move `chipset_lockdown` out of `common_soc_config` in the baseboard devicetree and configure it separately. Change-Id: I595c042cf62680d61f60965710d382bfdcd81671 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56209 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16mb/google/kahlee/Kconfig: add board-specific MAINBOARD_PART_NUMBERFelix Held
Before the part number for all boards was "Grunt". This patch adds the correct part number/name for all variants. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If506df0b1027fb09f5027d8b9653b776fe3bdc75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55681 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17FrankChu
Redefine GPIO_EC_IN_RW to GPP_F17 BUG=b:193091165 BRANCH=firmware-volteer-13672.B TEST=verify FAFT firmware_DevMode Pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I24f4803dc99ef3fc78852241f3a9e86ec70293d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-16mb/google/cherry: Allow payloads to enable USB VBUSYu-Ping Wu
Configure GPIO DGI_D4 (AP_XHCI_INIT_DONE) as output, so that payloads (for example depthcharge) can assert it to notify EC to enable USB VBUS. BUG=b:193499785 TEST=emerge-cherry coreboot BRANCH=none Change-Id: I21b7b811b8138cb3f71efecb0a0a886905c65a9c Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-07-15google/trogdor: Enable SPI_FLASH_MACRONIXJulius Werner
We may want to use that flash vendor on future variants. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-15mb/intel/adlrvp: Disable xDCI in devicetreeMonika A
Disable tcss_xdci as it is not used. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I94102240b13d2b96e0295f41bc2b0ba078faf342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-15mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a defaultMartin Roth
To be able to enable & disable PSP_verstage in the saved .config file, the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a select to a default with a prompt. BUG=182477057 TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK, verify that VBOOT_STARTS_IN_BOOTBLOCK is set. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14mb/google/cherry: add configuration for tomatoRex-BC Chen
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I972c70773d4d928e75098efbf78f174d7c3ebf50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 11:42:21 +0000