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2019-06-12mb/google/octopus: make new targets have DRAM part in CBI by defaultAaron Durbin
All new targets utilizing octopus mainboard support default to always using DRAM_PART_NUM_IN_CBI. This allows easier addition of new targets. BUG=b:132668378 BRANCH=octopus Change-Id: Idb136aa960260abe1657b16ded02a7dfb63c6849 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33370 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-12{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK supportFrans Hendriks
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-12mb/google/hatch: Disable dynamic clock gating for cr50's GPIOSubrata Banik
Disable dynamic clock gating for the community cr50's IRQ lives on. That IRQ is pulsed very quickly, and with clock gating enabled pulses tend to be missed. This is expecially true on the default 0.0.22 firmware that cr50 comes with out of the factory. BUG=b:130764684 b:130338605 BRANCH=None TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width, observe that even with sub-microsecond pulses no IRQs are missed. Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-12Revert "mb/google/poppy/variants/atlas: enable NVMe"caveh jalali
This reverts commit 41979d862a972375d6800afdf2b8b52d408fd220. Reason for revert: NVMe is no longer supported. BUG=b:134752066 Change-Id: I95f2e5f5efe2417700d458f0efd3c793fd8ce8c3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33307 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-11mainboard/google/kahlee: Reduce VRAM to 16MBMartin Roth
It was determined through testing that 16MB of reserved VRAM is sufficient. Additional RAM for the graphics driver is allocated out of system memory. BUG=b:123579702 TEST=Boot Grunt, watch VRAM usage with graphics driver logging. Change-Id: I44b640f015b45c0dc3d701929549f3a1082a9268 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33368 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-10mb/google/sarien/variants/arcada: Update thermal configuration for DPTFMike Hsieh
Update dptf for arcada DVT2. BUG=b:123924662 TEST=Built and tested on arcada system Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Change-Id: I302b7cd4c7e0579acb5482800241b5229cfc49f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-06-10mb/google/poppy/variants/nami: remove redundant breakEric Lai
Break never comes after return, remove it. BUG=N/A BRANCH=firmware-nami-10775.108.B TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I005918d6a04cd21df496dea0f2cb1ed6108675af Reviewed-on: https://review.coreboot.org/c/coreboot/+/33299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10mainboard/hp/z220_sff_workstation: remove unused header fileFelix Held
Change-Id: I4c780afaccd604a1bf4da67eea713f809744ddb2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-09mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM sizeKacper Słomiński
Signed-off-by: Kacper Słomiński <kacper.slominski72@gmail.com> Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/30980 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09mb/google/hatch: Add 16G 2666 LPDDR3 SPDShelley Chen
One variant is asking for support for 16G 2666 LPDDR3, so adding generic SPD for that. BUG=b:133455595 BRANCH=None TEST=None as this is not being used yet Change-Id: If16a101119aabc30d6ea83e95e9ded2e089a982d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-06-09mb/google/hatch: Add 8G 3200 SPDShelley Chen
One variant is asking for support for 8G 3200 DDR4, so adding generic SPD for that. BUG=b:132920013 BRANCH=None TEST=None as this is not being used yet Change-Id: I89cd3287aaf0baf384c4fe82d0881b0c48e09753 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33258 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09mb/intel/icelake_rvp: Update FSP-M UPDs to support iclrvp memory initAamir Bohra
Change-Id: Ib55fdfae6e9320c44761682fc134be0731de0fcf Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32522 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09mb/google/dragonegg: Pass FSP-M UPD as per dragonegg requirementSubrata Banik
TEST=Able to boot dragonegg board with LPDDR4 memory. Change-Id: Idbe0aa79879f2b1a754dd1f6718ad4ba1173e760 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31956 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08mb/lenovo/t430: Fix Dual GraphicsPatrick Rudolph
* Select ONBOARD_VGA_IS_PRIMARY in driver/lenovo/hybrid_graphics to fix disabling iGPU in 'Dual Graphics' on Lenovo T430. * Remove ONBOARD_VGA_IS_PRIMARY in mainboards that already select DRIVERS_LENOVO_HYBRID_GRAPHICS. Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-06mb/google: Add GPU panel settings for SKL/KBL boardsNico Huber
The values are generated from the respective VBTs. Change-Id: Ic74e9dac898c17ce64a94b06682997a39daeff69 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30247 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06qcs405: Add PRESERVE flag for RO_VPDNitheesh Sekar
Add PRESERVE flag to preserve the VPD data. Change-Id: I78ab4de31030465345c5ae58813bfed5e27494fb Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33020 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move LPC support to commonMarshall Dawson
AMD devices traditionally have the LPC-ISA bus at 14.3 and the definition has been very consistent. Relocate the feature from stoneyridge into common/block. BUG=b:131682806 Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move GPIO support to commonMarshall Dawson
The banked GPIO functionality in the AcpiMmio block has been consistent since the Mullins product. Move the basic support into a common directory. Each product's pin availability, MUXes, and other details must remain specific to the product. The relocated source also drops the weak configure_gevent_smi() that reports SMI is not available. The stoneyridge port relies on SMI to do its initialization, similar to modern soc/intel devices. This is the plan for future soc/amd ports, so make a missing function a build error instead of a runtime warning. BUG=b:131682806 Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-06mb/hp: Add Z220 SFF workstationPatrick Rudolph
* Add initial board commit based on HP8200 SFF. * Add documentation. * Serial and PCIe slot are working. Tested on HP Z220. Change-Id: I75987a7ea9a008a64281f0d5ab27e5148d36a4ec Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33207 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06siemens/mc_apl5: Add own GPIO tableMario Scheithauer
Because of some differences to the baseboard this board variant needs its own GPIO table. Change-Id: Ie3424cb0b867c5d43cd7db9e9ae654196cef5e90 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-06-06sb/intel/i82801gx: Detect if the southbridge supports AHCIArthur Heymans
This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-05mb/google/hatch: Increase RW_LEGACY to 1M for 16MB BIOSShelley Chen
The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS region, we had this region set too small, which was causing the firmware_FMap FAFT test to fail. BUG=b:133857135, b:129464811 BRANCH=None TEST=test_that -b hatch <IP> firmware_FMap Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-05mainboard/facebook/fbg1701: Do initial mainboard commitFrans Hendriks
Initial support for Facebook FBG-1701 system. coreboot implementation based on Intel Strago mainboard. Configure 'Onboard memory manufacturer' which must match HW. BUG=N/A TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701 Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-05sb/intel/i82801gx: Include chip.h directlyArthur Heymans
Change-Id: I3d743e90444292be687999ab4f50aa89d514fbad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33171 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05mb/*/devicetree.cb: Remove unavailable PCIe portsArthur Heymans
Some variants only support 4 PCIe ports so there is no need to have those unavailable ports in the devicetree. Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30821 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04mb/google/sarien: Fix SSD's power off sequence before going to S5Roy Mingi Park
BUG=b:133389422 TEST=check SSD's power off sequence to meet PCIE requirement. SSD's reset should be cleared before clearing SSD's power EN Pin. Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04mb/apple/macbookair4_2: Fix DRAM_RESET_GATE_GPIOEvgeny Zinoviev
It's GPIO28 according to schematics. Change-Id: I55be1ed178c818a17766e22cb2fd010412b8fe02 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-04mb/google/hatch: Enable LTR for PCIe portsFurquan Shaikh
Enable LTR for NVMe and WiFi PCIe ports so that they can use ASPM L1.2 BUG=b:134195632 TEST=Verified L1 substate with lspci on hatch: Before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ After: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33161 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03mainboard/intel/saddlebrook: Remove unused functionsArthur Heymans
Setting up the SIO serial console is done in the bootblock. Change-Id: Ideaf8f3dc0ee067e96d3fb5046071551c6d45329 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32985 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03mb/sifive/hifive-unleashed: Check for errors in fixup_fdtJacob Garber
It is possible that cbfs_boot_map_with_leak() and malloc() could fail, so detect those conditions and print error messages if they do. Change-Id: I34951da0b73028c4c89446cb1779a72422997325 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1399147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Xiang Wang <wxjstz@126.com>
2019-06-03mb/google/poppy/variants/nami: Add fallthrough commentJacob Garber
This fallthrough is intentional (see commit 2257a35862 - Perform PL2 setting for syndra), so add a comment to make that explicit. Change-Id: I57fe1e08f59aed12544cd2a71f1e0464f432f03b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1397063 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-03mb/lenovo/*: Remove useless smihandler codeArthur Heymans
This code to handle the brightness from SMM is copied from the Lenovo Thinkpad X60 code, but does not work on later generation. The PCI device it tries to address does not even exist on those devices. Change-Id: Ia959eb5b747846048396e66d4c926c96c27f3878 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33138 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03mb/google/link: Remove Link's own native graphics initNico Huber
The code was already orphaned since its hook-up was removed with a6be58fece (nb/intel/sandybridge: Remove the C native graphic init). Change-Id: Ia554c457e2f3a2dc42965ac5cded0be8e82311fb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-02soc/intel/baytrail: set default VBIOS filename and PCI IDMatt DeVillier
All Baytrail boards have the same GPU PCI ID, so set it here to avoid having to set it in each board's config. Move the VGA_BIOS_FILE config from google/rambi into soc/baytrail since it likewise applies to all Baytrail boards. Change-Id: Id1e0580b55e3590d868cb839987f06c49bb07cf5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33026 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02google/buddy: fix Windows ACPI error with WLANMatt DeVillier
Buddy's WLAN ACPI code was equivalent to, but formatted differently from the other auron variants. Since only differnce is root port used, have buddy use common WLAN ACPI and use preprocessor guards to set the root port correctly. Test: build/boot Buddy, verify Windows 10 boots without ACPI BIOS ERROR. Change-Id: I78d994f2bb3981d4d10cb534cd6e0ae673f73527 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30523 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02qcs405: Enable SPI-NORNitheesh Sekar
Enable support for Gigadevice spi-nor flash. Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-06-02qualcomm/qcs405: enable SPI bus 4 for TPMPatrick Georgi
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-31mainboard/google/hatch: Add Helios supportTim Wawrzynczak
Add Helios as a variant of Hatch. BUG=b:133182138 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a attempts to build a Helios target. Change-Id: I64ba06932eb0ee32405f7b14a94971a64c8fce71 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32918 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-31mb/google/hatch: Create helios variantTim Wawrzynczak
Created helios (hatch variant). Currenly copied from kohaku. Helios- specific changes will come later. BUG=b:133182138 BRANCH=none TEST=none Change-Id: I9d151621a1c42e6f3cadb288f7ea476828c059b5 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-05-31mb/google/hatch: Create kindred variantPaul Fagerburg
Create the Kindred variant of Hatch by taking a copy of the Hatch files as placeholders. Kindred-specific changes will happen in future CLs. BUG=b:133181366 BRANCH=NONE TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_KINDRED Change-Id: I09ad3da0505d599fc3797d7fa24b4dc170dcd18b Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-30mb/lenovo/*20*: Remove default FMAPNico Huber
These boards don't need a default FMAP. Moreover, having a default FMAP disables automatic integration of optional regions like `CONSOLE`. Also, these files contain an error: `COREBOOT` isn't placed at the top of the image. Resulting in default builds without a reset vector ;) Change-Id: If6331e19955034c02828e88902a5934c34d3e784 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33110 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29src/mainboard: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I3b1a395cfe8b710fb6b468e68f4c92e063794568 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29drivers/intel/fsp1.1: Simplify bootflow and clean upArthur Heymans
This gets rid of the boilerplate back and forward calls between the SOC/FSP-driver code and mainboard code. Change-Id: I5d4a10d1da6b3ac5e65efd7f82607b56b80e08d4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32961 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29commonlib: fix typo LB_TAB_* (instead of LB_TAG_*)Patrick Georgi
Also adapt all users of these symbols Change-Id: Ibf924a283d438de49a93ce661b0d9ca1a81cd6d1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-29google/clapper: fix up devicetreeMatt DeVillier
When clapper was upstreamed, the devicetree was pulled from the wrong firmware branch, leading to some incorrect settings and touchpad, touchscreen, and audio not working. Correct devicetree settings using Chromium branch firmware-clapper-5216.199.B Test: build/boot google/clapper, verify touchpad/touchscreen/audio functional under Linux (GalliumOS 3.0/kernel 4.16.18). Change-Id: Iacfce575a054b1f484149f36d0aa83d20d034d8a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-29mb/google/{misc}: set default SMBIOS manufacturerMatt DeVillier
Legacy Google mainboards (pre-Skylake) shipped with the SMBIOS manufacturer set to GOOGLE, which many Linux drivers rely on for application of DMI quirks. Set it as the default to avoid having to do so for each board's config Change-Id: I61b0217f3535852d7d6e24a1ac78075c20c0825a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-29Clean up unused arch/early_variables.h headerArthur Heymans
Change-Id: Ib863e23863ba6d7504b6c4d32de2f1fea4e57fec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29mb/gigabyte/ga-b75m-d3{h,v}: Switch to variant setupAlex James
The Gigabyte GA-B75M-D3H/D3V mainboard trees share a lot of duplicate code, and can serve as a base for porting other Gigabyte 7 series motherboards. Switch the Gigabyte GA-B75M-D3H/D3V mainboard trees to a variant setup, defining ga-b75m-d3v as a variant of ga-b75m-d3h. Signed-off-by: Alex James <theracermaster@gmail.com> Change-Id: Ia175207a2568aefe1aa9bd8d4d990de6a26f1657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-29mb/google/sarien: Send post code to the ECEric Lai
Use the mainboard post code hook to inform the wilco EC driver of the every stage. BUG=b:124401932,b:133466714,b:133600566 BRANCH=sarien TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de Reviewed-on: https://review.coreboot.org/c/coreboot/+/33047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29mb/google/poppy/variants/nami: Disable FPMCU for non-fingerprint variantsIvy Jian
Even fingerprint device probe failed on non-fingerpint boards,the CRFP driver still register the device that cause the GPE#1 as wake source every time. Override devicetree for non-fingerpirnt variants to avoid unexpected wake event(GPE#1). BUG=b:129650040 BRANCH=firmware-nami-10775.108.B TEST=Boots to OS and check no GPE#1 wake event from eventlog when S0ix exit. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I6fa96e04a34e296889414b96a8c604fc61b8a236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33017 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-28mb/google/sarien: Modify SSD power sequenceEric Lai
Due to we turn off SSD power in S5. CB:32952 Based on M2 spec we have to turn on SSD power before RST assert. BUG=b:133389422 TEST=verify warm boot and cold boot are boot successfully. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5b78bab4be675bbb8795361bcfa5af52cb54bb1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/33029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-28mb/google/sarien: Fix SSD power leakage in S5Eric Lai
Turn off SSD power in S5. BUG=b:133389422 TEST=measure H13 is low in S5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-28mb/google/sarien: Modify arcada touchscreen reset delayCasper Chang
Modify reset delay to 20ms of touchscreen to address i2c hid driver rebind failed issue after auto update of touchscreen firmware BUG=b:132211627 TEST=Touchscreen works after auto update and no re-bind driver failed issue Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: If17afbd160a2c97beb69d0cb50e4a7dc654775f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Crews <ncrews@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-27sb/intel/ibexpeak: Use common Intel SMM codeArthur Heymans
TODO in followup patch: Some not mainboard specific things should be moved out of mainboard_smi_apmc. Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-25nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-25mb/lenovo: Unify thermal threshold handlingPeter Lemenkov
Unify thermal handling across Lenovo boards (except g505, which is different). Namely, do the following: * Move thermal levels from acpi_tables to thermal.h (and create if necessary). * Don't use board-specific ifdef guards. * Set thermal levels using dedicated acpi_update_thermal_table function as almost all Lenovo boards do. * Update list of authors in comments. Merge all author's entries. * Minor whitespace and formatting. This makes diff -ruw between the Lenovo boards smaller. Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29659 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23mb/google/hatch/variants: Fix DPTF sensor IDsEvan Green
There are indeed two temperature sensors hooked up to the EC, but they are indexed as 0 and 1, not 1 and 2. BUG=b:132999028 TEST=Boot hatch with hardened EC, observe no more index overflows Change-Id: Ia7f503bc1dc941635db52fce40f217bf34da6d2b Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-23src/mainboard/google: Adopt Mainboards to changed Type41 FuncChristian Walter
Required for automatic onboard device detection in the next patch. Change-Id: I3087de779faf8d006510c460b5372b22ae54b887 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32909 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23mb/asus/p8h61-m_pro: Add small fixesPatrick Rudolph
* Add VBT * Configure OnBoard NIC * Add documentation Change-Id: Iad739b4e1dacb41f5f63247150951df7013bbf0c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-22mb/google/sarien: Send post code to the ECDuncan Laurie
Use the mainboard post code hook to inform the wilco EC driver of the latest boot stage. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). Change-Id: If5bf69365d8be3bdbd433f305c85848206ded7b0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32937 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-22mb/up/squared: Add mainboardFelix Singer
Works: - bootblock, romstage, ramstage - Serial console UART0, UART1 - SPI flash console - iGPU init with libgfxinit - LAN1, LAN2 - USB2, USB3 - HDMI, DisplayPort - eMMC - flashing with flashrom externally WIP: - Documentation - VGA For some reason Seabios can not find the CBFS region and therefore it can't load seavgabios, but generally it is working as soon as Linux is booted. - ACPI Works not: - Devices needs proper configuration - Seabios can't find CBFS region Untested: - GPIO pin header - 60 pin EXHAT - Camera interface - MIPI-CSI2 2-lane (2MP) - MIPI-CSI2 4-lane (8MP) - SATA3 - USB3 OTG - embedded DisplayPort - M.2 slot - mini PCIe - flashing with flashrom internally using Linux Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-21mb/google/octopus: Create Garg variantKevin Chiu
This commit creates a garg variant for Octopus. The initial settings override the baseboard was copied from variant bobba. BUG=b:132668378 BRANCH=master TEST=emerge-octopus coreboot Change-Id: I9a36bc5dc3d2b891b1bce86015aa264894d1434b Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-05-21mb/google/kohaku: Set ACPI_GPIO_IRQ_EDGE_BOTH for headset INTKane Chen
Currently, GPP_H0 gpio input rout is set to GPI_INT. So, ACPI_GPIO_IRQ is required for GPP_H0 in devicetree This change also aligns hatch's setting. BUG=b:131742713 TEST=headset is working Change-Id: Ie1264641bc4dfa5f98b6dab2d6f2133a6f9cbdb8 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ben Kao <ben.kao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-05-21mb/lenovo/r500: Add mainboardArthur Heymans
Tested: - Ethernet NIC - Wifi RFKill - USB - LVDS, VGA with libgfxinit - Booting with dock attached (COM1) - Keyboard, trackpoint - SeaBIOS 1.12 - S3 resume - Tested in descriptor mode, with vendor FD and ME - Add VBT to ACPI OPregion Untested: - SATA (likely works) - Trackpad (my cable is broken, likely works) - Displayport (likely works) - Descriptorless mode - DVD drive - Extra battery - model with ATI GPU Does not work: - Dock hotplug - Quad core CPU (hangs during AP init, probably needs hardware mod) - Hotplugging the expresscard slot (works with 'echo 1 | sudo tee /sys/bus/pci/rescan') TODO: - proper dock support - documentation note: This board was hard to flash, I had to desolder the flash. TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.12, Debian 9, Linux 4.9 from USB Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-21mb/lenovo/t400: Add VBT fileArthur Heymans
All variants (t400, r400, t500, w500) use the same OPROM for the IGD. Change-Id: I1b9db7b29b22809542f80f60a5e2eb3283fe1c02 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-20mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configurationSubrata Banik
sarien/arcada: GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM. hatch: GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM. BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20mb/google/dragonegg: Override FSP default GPIO PM configurationSubrata Banik
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration. GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D16 IRQ mapped for H1 TPM. BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20sb/amd/cimx/sb800: Get rid of power button device in corebootPaul Menzel
Apply commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD Brazos boards [1]: > As per the ACPI specification, there are two types of power button > devices: > 1. Fixed hardware power button > 2. Generic hardware power button > > Fixed hardware power button is added by the OSPM if POWER_BUTTON flag > is not set in FADT by the BIOS. This device has its programming model > in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this > power button device by default if the power button FADT flag is not > set. > > On the other hand, generic hardware power button can be used by > platforms if fixed register space cannot be used for the power button > device. In order to support this, power button device object with HID > PNP0C0C is expected to be added to ACPI tables. Additionally, > POWER_BUTTON flag should be set to indicate the presence of control > method for power button. [..] > This change gets rid of the generic hardware power button from all > google mainboards and relies completely on the fixed hardware power > button. The same problem exists with the AMD Hudson devices in coreboot. For AMD Hudson (2) and Yangtze based devices this was removed in commit 44f2fab8 (AMD hudson and yangtze boards: Let mainboard declare power button) [2]. Two devices are detected. $ dmesg | grep Button [ 0.209213] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 [ 0.209254] ACPI: Power Button [PWRB] [ 0.209332] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 0.209349] ACPI: Power Button [PWRF] $ sudo evtest No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Power Button /dev/input/event1: Power Button [..] [1]: https://review.coreboot.org/5546 [2]: https://review.coreboot.org/27272 Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/27496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-05-20mb/google/hatch: Change SD_CD# reset config to PLTRSTKrishna Prasad Bhat
The system should boot fine to OS on pressing power button before the system enters G3. However, on hatch, we observe that the system waits for few seconds at "Starting kernel" and then resets, with SD card tray inserted and SD_CD# pad reset config set to DEEP. Hence configuring SD_CD# pad reset config to PLTRST. BUG=b:129933011 TEST=Built and verified on hatch. Change-Id: Ic4466b96332f095ff39b28d98607e95fc3d12d6a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20mb/google/octopus: Override emmc DLL values for CastaJamie Chen
New emmc DLL values for Casta BUG=b:122307918 TEST=Boot to OS on 12 systems Change-Id: Ie51885fb9628fa093ecc38f4a3f3157f751ca9ab Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-05-18mb/google/sarien: Set serial number in SMBIOSDuncan Laurie
Set the system serial number from the VPD key "serial_number" and the mainboard serial number from the VPD key "mlb_serial_number". BUG=b:132970635 TEST=check serial number is set in SMBIOS based on VPD, and if there is no VPD key found then it is empty. Change-Id: Ia8f1486dcb1edc968b8eb1e6d989b10c05913aca Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-16mb/gigabyte/ga-b75m-d3{h,v}: Various cleanupsAlex James
- Enable LPC TPM support in Kconfig and add pc80/tpm to devicetree - Enable VBT support in Kconfig and add VBT files extracted from vendor firmware - Remove IGPU VBIOS entries from Kconfig - Remove unused PS2 definitions in superio.asl - Add PWRB ACPI device entry to mainboard.asl - Remove duplicate chipset register initialization from mainboard.c - Move ITE Super I/O configuration to mainboard_config_superio in romstage.c Signed-off-by: Alex James <theracermaster@gmail.com> Change-Id: I2d11c55dc809b920bccf55f5f745d9f29b18bbb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-16mb/ocp/monolake: replace IS_ENABLED(CONFIG_*) with CONFIG()Patrick Georgi
That's how we do it these days. Change-Id: I6bf6460440d0f2e6973734ba8894a4be981d03c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-16mb/google/sarien: leave gpio pads unlocks during fspJett Rink
The FSP will lock down the configuration of GPP_A12, which makes the configuration of the GPIO pin on warm reset not work correctly. This is only needed for the Arcada variant since it is the only variant that uses ISH. BRANCH=sarien BUG=b:132719369 TEST=ISH_GP6 now works on warm resets on arcarda Change-Id: Icb3bae2c48eee053189f1a878f5975c6afe51c71 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32831 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-16soc/amd/common: Create AcpiMmio functionality from stoneyridgeMarshall Dawson
Move the stoneyridge AcpiMmio code into soc/amd/common. The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000 commonly known as AcpiMmio. Implementations beginning with Mullins enable decode in PMx04. Older designs use PMx24 and allow for configuring the base address. Future work may support the older version. Comparing the documentation for AMD's RRGs and BKDGs, it is evident that the block locations have not been reassigned across products. In some cases, address locations are deprecated and new ones consumed, e.g. the early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks are now at 0x1500, 0x1600, and 0x1700. Note: Do not infer the definitions within the hardware blocks are consistent across family/model products. BUG=b:131682806 Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15src/mainboard: Remove unneeded include <arch/io.h>Elyes HAOUAS
Change-Id: I73c557d6ef009fb2cac35fdea500dee76f525330 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-15soc/intel/broadwell: Enable LPC/SIO setup in bootblockArthur Heymans
This allows for serial console during the bootblock and enables bootblock console by default. Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-05-15nb/intel/broadwell: Add an option for where verstage startsArthur Heymans
Previously broadwell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. With a separate verstage the romstage becomes an RW stage. The mrc.bin however is only added to the RO COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I900233cadb3c76da329fb98f93917570e633365f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30384 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15mb/packardbell/ms2290/acpi: Serialize Control MethodElyes HAOUAS
IASL reports remarks 'Control Method should be made Serialized'. Change-Id: I5606c6e435da17f7d4732148f6ddcedb1fde4ab0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-15mb/google/poppy/variants/atlas: Remove B0D4 _PSVPuthikorn Voravootivat
Per Intel, the internal thermal protection is working better than putting B0D4 _PSV in dptf. BUG=b:131251533 TEST=Get ~10% better Octane score. Correct TCC and TCC offset in MSR register. Change-Id: If85afdc673687477ec85a47efcb264a7e5d6ae45 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-05-15mb/google/poppy/variants/rammus: Support new onboard Hynix memoryKane Chen
Add hynix_dimm_H9CCNNNCLGALAR-NVD for new onboard memory support. BUG=b:130337306 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-15soc/intel/cannonlake: Support different SPD read type for each slotPhilip Chen
Also clean up cannonlake_memcfg_init. The major changes include: (1) Add enum 'mem_info_read_type' to spd_info. (2) Add per-dimm-slot spd_info to cnl_mb_cfg. (3) Setup memory config for each slot independently. (4) Squash meminit_memcfg_spd(). BUG=chromium:960581, b:124990009 BRANCH=none TEST=boot hatch, hatch_whl, and kohaku Change-Id: I686a85996858204c20fd05ef24787a0487817c34 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-14mb/google/poppy/variant/atlas: Add SPDs for Samsung D-die chipsCaveh Jalali
This adds the SPDs for Samsung D-die 16Gbit and 32Gbit LPDDR3-2133 chips. BUG=b:132206809 TEST=boots on atlas with C-die and D-die memory chips localhost ~ # mosys memory spd print all 0 | LPDDR3 | SO-DIMM 1 | LPDDR3 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG 1 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG 0 | 8192 | 2 | 64 1 | 8192 | 2 | 64 0 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133 1 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133 localhost ~ # Change-Id: I8ba000aeeb77f07d7f18bda86b3c07f5b50478b8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-14mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init errorGaggery Tsai
This patch adds a workaround for Samsung C-die 2G/4G memory chips. For unknown reasons, some boards with Samsung LP3 memory chips could not pass early CS/CMD training. MRC has to change the granularity from 16 ticks to 8 ticks, which implies bad margin with this memory chip. Another way is to enhance the drive strength for CS. This patch is to enhance the drive strength for CS and CMD. Enhancing the drive strength for CMD could gain margin abaout 3 more ticks. Root cause needs to be further investigated with memory vendor. BUG=b:131177542 BRANCH=None TEST=USE=fw_debug emerge-atlas chromeos-mrc coreboot chromeos-bootimage & check the MRC log to ensure correct Rcomp values are passed to MRC. Tested with board ID #8 and #11. Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-05-14soc/intel/broadwell: Clean up the bootflowArthur Heymans
Call the raminit from a common location instead of from the mainboard specific code. Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-14soc/intel/broadwell: Don't use a pointer for pei_dataArthur Heymans
To improve the bootflow, the scope of the pei_data needs to be extended. Change-Id: Ic6d91692a7bf9218b81da5bb36b5b26dabac454e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-05-14soc/intel/broadwell: Move GPIO init to a common placeArthur Heymans
This also links the gpio configuration instead of including it as a header. Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-05-14mb/{lenovo/x201,packardbell/ms2290}: Remove superfluous TS initArthur Heymans
Timestamps are initialized in cpu/intel/car/romstage.c. Change-Id: Ia2b762667be17aa5b482cd585dd6f6198cf50d9e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32758 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13mb/samsung/lumpy: Move onboard SPD to second channelPatrick Rudolph
Move the onboard SPD to second channel as native raminit does and workaround mrc expecations in northbridge code. Required to move pei data to devicetree and to use the same code for mrc and native raminit. Tested on Lenovo T520: Other fields then spd_data[0] are ignored. Change-Id: If1910e82a4bd178c2a6c2991c91e09782122888e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13nb/intel/sandybridge: Update pei_data commentsPatrick Rudolph
Update outdated comments. Change-Id: I100f71345281a1dc52e99d2395f528d60a9a1f58 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13mb/lenovo/s230u: Rewrite trigger inversion ACPI codeMartin Roth
The GPIO invert registers are already defined in the PCH code, so just use the 8-bit versions of the registers instead of creating a new GPIO field for the single bits. This allows us to get rid of the Field(GPIO...) code that's causing problems with IASL version 20190509. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iac5dfb71b3a2b5a25c05a403cf5f403c7acecaaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/32753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-13mb/t400/acpi: Update ATPR buffer to fit all entriesElyes HAOUAS
Error spotted using acpica version 20190509 (Change-Id: I6779a20). Change-Id: Ic9cf16a7494667f6dab156c697fb8f8e9966051e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-13mainboard: remove "recovery" gpio, selectively add "presence" gpio.Matt Delco
The gpio table is only used by depthcharge, and depthcharge rarely has a need for the "recovery" gpio. On a few boards it does use the gpio as a signal for confirming physical presence, so on that boards we'll advertise the board as "presence". All these strings probably should have been #defines to help avoid typos (e.g., the "ec_in_rw" in stout seems questionable since everybody else uses "EC in RW"). Cq-Depend: chromium:1580454 BUG=b:129471321 BRANCH=None TEST=Local compile and flash (with corresponding changes to depthcharge) to 2 systems, one with a "presence" gpio and another without. Confirmed that both systems could enter dev mode. Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-13mb/google/sarien: config ISH_GP6 with NF2Jett Rink
A12 is not current set for ISH_GP6 so the ISH_LID_CL#_TAB signal is not making it to the ISH properly. Enable the second native function instead of the first. BRANCH=none BUG=b:131785573 TEST=gpioget on ISH now shows the correct gpio level Change-Id: Ib3a654ae659037263aa9aa29d45b42ca67b7955b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32738 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13mainboard: Remove unused include <timestamp.h>Elyes HAOUAS
Change-Id: Id05fc39c0c0d0560e34e55f793060d29df82d026 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-05-12mb/asrock/h81m-hds: Drop now obsolete libgfxinit overrideNico Huber
CPU type is detected at runtime now. Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-12mb/lenovo/*: Add MAINBOARD_FAMILYPatrick Rudolph
The Kconfig MAINBOARD_FAMILY sets the family field of SMBIOS entry 1. Match what vendor firmware does and use the same value as in the version field. Required for fwupd which uses the family field to generate a GUID. Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-10mb/google/sarien: Fix s5 touchscreen power leakageLijian Zhao
Leakage power is observed from TOUCH_SCREEN_PD# (GPP_E7 which is connected to RESET pin of Wacom controller) during S5. To avoid leakage power, GPP_E7 needs to be turned off before S5 entry. BUG=b:129899315 TEST=Measure leakage power in S5 from both Arcada and Sarien Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/32367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-10mb/google/nami: Add VBT blobs and include them in cbfsArthur Heymans
Add vbt files for nami variants and select Kconfig option to utilize them. The default vbt is automatically added by the Kconfig selection and so does not need to be specified in the makefile with the others. Test: boot vayne and akali nami variants, verify display functional and correct vbt loaded. Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 14:03:46 +0000