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The patch disables Tccold Handshake to prevent possible display
flicker issue for marasov board. Please refer to Intel doc#723158
for more information.
BUG=b:279117758
BRANCH=firmware-brya-14505.B
TEST=Boot to OS on marasov.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I286e88e5bec240d64e6c801648f6483ad2b0939c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74931
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Configure the SuperIO and logical devices in the device tree. This
overrides the power-on default state.
UART1 was already enabled, and if ENABLE_EC_UART1 was selected in
Kconfig, the LPC UART1 I/O range was also already enabled.
The RTC/BRAM interface was enabled (and the BRAM1 base was 0x360 by
default), but the LPC I/O range was not opened previously. Now it is
open and BRAM bank 1 is accessible.
Mouse/Keyboard are not wired to anything on this board and are now
disabled.
UART2, SMFI, power channel 1, and power channel 2 were enabled
previously, but their LPC I/O ranges were not opened and they were not
accessible to the OS. Fan control is performed by the EC on this board
so there is no change.
SWUC and power channels 3-5 were disabled by default, no change.
Change-Id: I58a5a427737f4a2caa64326c110eb53ec00b347d
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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variant_board_sku() is missing dependences in order to work correctly
in romstage. Rather than more intrusive rework as its use is limited,
move the FPMCU early GPIO init back to ramstage. We still meet
sufficient power off time to fully power cycle the MCU.
BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami and FP tests all pass
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ia428ec5aec1a0438e91bc48903bda043046b740e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74695
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The image processing unit/GMM and xDCI are not used on octopus boards;
additionally, enabling xDCI can cause some problems with USB ports in
both booting from the payload and in the OS.
Change-Id: I1ee99b5c45881a4cf3624bf487bc9d83fb3d07a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.
TEST=build, boot Windows on wyvern variant, verify headphone output
and microphone functional under Windows using coolstar's SOF drivers.
Change-Id: I421c070eac321c2fc160b8f26868bcb1ec13001e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74815
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.
TEST=build, boot Windows on several volteer variants, verify audio
functional under Windows using coolstar's SOF drivers.
Change-Id: I62a96149cec9eeb7b2da8a2337083969a1b0fce0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74816
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.
TEST=build, boot Windows on banshee and osiris variants, verify audio
functional under Windows using coolstar's SOF drivers.
Change-Id: I12614b85f9779cc40d83a9c868cc46b110f26af6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74817
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Add all SOF chip drivers to baseboard and use FW_CONFIG to determine
the correct option, to ensure the correct audio config is passed to the
SOF OS drivers.
TEST=build, boot Windows on several dedede variants, verify audio
functional under Windows using coolstar's SOF drivers.
Change-Id: I9452b11af614d8727aa8dd448e37f7a06faa450d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74818
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Since commit 833bb448c521 ("mb/siemens/mc_ehl: Remove spd.bin from
CBFS"), the subdir 'spd' is no longer necessary.
Change-Id: Ibaf44e3181b2167aa83cffcc59835196e4cb5cdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Remove explicit PNP 6e.1 configuration for UART. This had no effect,
the SuperIO is actually on I/O port 2e. Enabling the 8250IO driver is
sufficient to use the UART, the UART device is enabled by default.
Test: Build Mini v2 with and without CONFIG_ENABLE_EC_UART1, boot and
check output on serial.
Change-Id: Idbb39c81cadd633f4718f0682d231dc578d20325
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74362
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tuning i2c frequency ,timing ,Waveform meet to SPEC
i2c frequency :
I2C0=>399.8khz / Setup Time:1765ns / Hold Time:82.35ns.
I2C1=>390.4khz / Setup Time:1.788us / Hold Time:70.58ns.
I2C3=>308.7khz / Setup Time:1.482us / Hold Time:0.4us.
I2C5=>390.8khz / Setup Time:1.218us / Hold Time:0.405us.
BUG=b:275061994
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot,
EE check OK with test FW and TP function is normal.
Change-Id: I5b77cd3fd3ff00804f1b8dd5828dc831a9732566
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74880
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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The patch orders MTL RVP board Kconfigs alphabetically.
TEST=Build the code for mtlrvp
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib8557aab2848a384fba5203e5f3d62407b2566ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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We have largely dropped from filling in mainboard_ops.name
as unnecessary. A common place should be decided where or if
this information is added in the console log.
Change-Id: I917222922560c6273b4be91cd7d99ce2ff8e4231
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.
TEST=build, boot Windows on several hatch variants, verify audio
functional under Windows using coolstar's SOF drivers.
Change-Id: Ie791fa873fc7bbab84644f5ea5743bdcdc124908
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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The image processing unit (Iunit) and SoC UARTS are not used on any
reef boards.
Change-Id: Iacdf93b4952cbc63fc465f07d440463106527b8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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It's not particularly useful to end users, and shows up as an unknown
PCI device under Windows Device Manager.
TEST=build reef, boot Windows, verify unknown PCI device no longer
present in Device Manager.
Change-Id: Ie8ec46e2e07b6635bfe9766812ce08b866c71d66
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add rules to inject the variant specific SPD binaries into APCB.
BUG=b:273383819
TEST=Build Myst BIOS image. Currently no APCB is present. So no SPD is
injected into APCB.
Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74746
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Generate the RAM Strap IDs based on the initial memory configuration.
BUG=b:272746814
TEST=Build Myst BIOS image.
Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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There is no platform-level implementation for USB port power management
in various sleepstates. This mainboard never evaluates the set GNVS
variables S3U0, S3U1, S5U0 and S5U1 in ASL or in its SMI handlers.
Change-Id: Ic7af2d608d95c6691f31ef1b8af72f96da20787c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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There is no platform-level implementation for USB port power management
in various sleepstates. The mainboards changed here never evaluate the
set GNVS variables S3U0, S3U1, S5U0 and S5U1 in ASL or in their SMI
handlers.
Change-Id: Ia1bc5969804a7346caac4ae93336efd9f0240c87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
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Change-Id: I634af65cd41e0d70e673d550ed8063abc6eea6d4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Add data.vbt files for all variants supported by current volteer
recovery image. Several boards use the same VBT, so place the "common"
VBT under the baseboard directory and set it as the default.
For variants with a unique VBT, override the default and use the file in
their respective variant directory. Select INTEL_GMA_HAVE_VBT for all
variants which have a VBT file.
TEST=build/boot various volteer variants
Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74852
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Camera LED will blink several times as sensor is being probed during kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:274634319
TEST=Build and boot on Craask. Verify & observe Camera LED blinking behavior.
Change-Id: I78ed5efe1e2c071d817c1e0455271886e89e63c7
Signed-off-by: Jimmy Su <jimmy.su@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74728
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The support for a spd.bin from CBFS was removed for all mc_ehl boards in
commit 833bb448c5213 (mb/siemens/mc_ehl: Remove spd.bin from CBFS).
There is still a remaining comment in romstage_fsp_params.c referring to
the removed capability. This fix removes the spd.bin related part of the
comment to stay consistent with the code.
Change-Id: I669ee1c33d1d1c47764640982f71129195e63f14
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74801
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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With the profile ATLAS_PROF_REALTIME_PERFORMANCE it is desired to not
have the option to be able to enter sleep. The reason is that Microsoft
Windows goes to sleep after 30min of inactivity by default.
TEST: See that Microsoft Windows 11 has no 'Sleep' option in the start
menu.
Change-Id: I424db7e712a705c628aa3a10a486d3313404987a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74421
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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FSP is fractionally faster at configuring ASPM (1,118,688 vs 1,122,205)
but coreboot's configuration results in lower power consumption of
approximately 0.5W when idling - the reason why is unknown.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74520
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add functionality to ensure that the FPMCU is power cycled long enough
on boot to ensure proper reset.
This solution relies solely on coreboot to sequence the power and reset
signals appropriately (150ms on boot).
-Confirmed power is off for 150ms on boot.
-Confirmed RCC_CSR of FPMCU indicates power cycle occurred.
-Confirmed reset is de-asserted approx 3ms after power application
(target >2.5ms)
BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami and timings are
as expected.
Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add functionality that allows a variant SKU to have a specific set of
GPIO configs in romstage (modeled after the existing one in
ramstage)
BUG=b:245954151
TEST=builds
Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Generate RAM IDs for -
MT62F512M32D2DR-031 WT:B (LP5)
H9JCNNNBK3MLYR-N6E (LP5)
MT62F1G32D2DS-026 WT:B(LP5x)
H58G56BK7BX068 (LP5X)
BUG=b:276814951
TEST=Run part_id_gen tool without any errors
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74802
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The number of NID entries was too high for the Realtek
and Intel sound cards, preventing the verb table from
loading. Now the values are correct; it loads as intended.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Commit 5103b87a4d7b ("mb/starlabs/starbook/adl: Add an option to
enable Hot Plug") introduced an option to enable Hot Plug for the
SSD. The port was set to 4 (RP5) which is the wireless card. Change
this to 8 (RP9) which is the SSD.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I884f4997d73e31bd422477952466f168afad66a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74738
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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add the initial gpio configuration for screebo initial variant
BUG=b:276814951
TEST=emerge-rex coreboot
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74475
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Because SPL fuse needs to be set before the FW lock. So enable
Markarth project to send the fuse SPL (security patch level)
command to the PSP.
BUG=b:279499511
BRANCH=none
TEST=FW_NAME="Markarth" emerge-skyrim coreboot chromeos-bootimage
Then get "PSP: SPL Fusing Update Requested." in the firmware log.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I8fbbd89d11b1bdb2c95c761955c10bedb366fd70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74753
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Samsung 4G K3KL6L60GM-MGCT support
BRANCH=None
BUG=b:243337816
TEST=emerge-skyrim coreboot
Change-Id: I89b9798c16635a32dff12f1c0b65737d3c16cd59
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch adds new USB_DB FW_CONFIG to enable support for USB4 ANX7452
Rev 2.
BUG=b:279647370
TEST=Able to build and boot google/rex with Proto 2 SKU
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I878b591e5919d05d3c5fc2eefdeb492e95d4f7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Set edp_panel_t9_ms to 8ms which means it will delay 8ms
between backlight off and vary backlight off.
BUG=b:271704149
BRANCH=Skyrim
TEST=Build; Verify the UPD was passed to system integrated table;
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74790
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to
match the eDP sequence timing in milliseconds.
BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Update devicetree to support ELAN I2C generic touchscreen.
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I2779c2930d89ff42233f9b20bd8abdf6dc00c0e0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74776
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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The MIPI panels will be used on the detachable variant starmie, and
there will be different MIPI panels used on starmie. In order to make
the different panels functional on unprovisioned devices, it needs
to pass the SKU ID and panel ID to the payload to load the matched
device tree for kernel. From the schematic, the starmie variant
will read the LCM ID from ADC channel 5.
BRANCH=corsola
BUG=b:275470328
TEST=boot starmie and see FW screen display
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I6339dc3c177fb8982f77fb3bd32dc00da735fce4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
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The signals for the NV33 regulator were swapped (enable and power
good). Switch these back to the way they should be:
GPIO_NV33_PWR_EN GPP_E1
GPIO_NV33_PG GPP_E2
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ic2a53103e1feadd7ecebd4bed02dcc34410b8e3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Change-Id: I8b536f8a1ff4eab06f37aec0f25704525dc1b64e
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Because WD SSD drive isn't holding the clock low for some reason.
So we change to read eMMC clkreq signal instead.
BRANCH=none
BUG=b:274377518
TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok.
Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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By default, coreboot includes support for all the different types of SPI
ROMs. Excluding the unused ROM types shrinks ramstage by almost 4k.
BUG=b:267735039
TEST=Build & Boot ROM
BRANCH=Skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If6e402269d1f2cac8256d478eb36743441497bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72769
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Remove rtd3 for emmc device on taeko
BUG=b:271003060
TEST= emerge-brya coreboot, flash to DUT and can boot to OS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Remove rtd3 for emmc device on taniks
BUG=b:271003060
TEST=emerge-brya coreboot, flash to DUT and can boot to OS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This will fix:
> [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented,
wasting 20ms to wait on Cr50!
BUG=b:277297687
TEST=builds
Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74286
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN. Mapping derived from myst schematic.
BUG=b:275965982
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Ensure that DXIO descriptors are updated using info from AMD and Myst
board schematics.
BUG=b:275960920,b:276744321
TEST=builds
Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74112
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This mainboard has SD slot available and therefore it should be enabled.
Use the same SD card configuration as for mc_ehl2 mainboard.
Change-Id: Icd9b25301311679cf93b05ba83a24e551261a020
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This mainboard has the RTC RV-3028-C7 connected to the I2C1.
TEST:
- Console Log shows no errors for RV-3028-C7 during I2C1 init
- Finalize device for I2C 00:52 shows correct date and time
Change-Id: I1b4115d7844a0c218fdf92cb1af2da5a95eb4337
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74652
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct the USB settings, suitable for this mainboard.
Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74651
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default
value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to
'0'. On this mainboard NC FPGA is connected to PCIe root port #1
(00:1c.0).
Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the GPIOs must
be adjust according to the circuit diagram for this mainboard.
Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The patch disables Tccold Handshake to prevent possible display
flicker issue for Omnigul board. Please refer to Intel doc#723158
for more information.
BUG=b:279539826
BRANCH=firmware-brya-14505.B
TEST=Verify the build for Omnigul board
Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74737
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iae2dc0a934f0ea3ca59d8a811f1daeedb090a7bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
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For uni-processor platforms, with SMP=n or MAX_CPUS=1,
neither the LAPIC or IOAPIC MADT entries are added.
Change-Id: I8777f4e3b37fe7b564189c6bf48e3988026b2361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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IRQ override from IRQ #0 to GSI #2 is changed from
MP_BUS_EISA to MP_BUS_ISA.
Change-Id: I115df037fd79e120b04e6aff9e53f963f045b997
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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i82801gx, i82801ix, i82801jx:
Maintain IRQ #0 to GSI #2 override as positive edge trigger.
ibexpeak, emulation/qemu-q35:
Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).
Change-Id: Ia8a04daf3a79d9f2f4801dc85e4975278e30dc8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms'
implementations of adding IOAPIC and IRQ override entries
for ACPI MADT tables.
Platforms that have a more complex MADT may continue to
add custom entries using CUSTOM_ACPI_MADT.
Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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USB port 6 connects to a USB front camera, it should always probe.
Remove probe by rear camera fw_config.
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I554046718f6e0eb7197970f9a3808b3e1ea7f99c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
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Update devicetree
-Enable USB2 port5 for WWAN
-Update OVTI8856 setting
-Update USB2/3 Type-A 0/1 port location
Probe devicetree based on FW_CONFIG
-pen garage
-rear mipi cam
-USB WWAN
BUG=b:273791621, b:276369170
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
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BUG=b:277294070
TEST=None
Change-Id: I0aa4e0bcfb06e5e5cb7e9d52f2d82b5818925267
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74284
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implement `smm_mainboard_pci_resource_store_init` to store the
resources for XHCI devices. These stored resources are later used by
the elog code to log XHCI wake events.
BUG=b:277273428
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I608d51f438681ac529323c23cc707845a3d609d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74281
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable gfx_hda to allow for audio over hdmi.
BUG=b:277219546
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I58096f1408f66f968af1494e487cf2bfc43b9a0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74278
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add the crypto device to the devicetree.
BUG=b:277214359
TEST=builds
Change-Id: I5394c5f9df64642d8633af84cf662652bd1a5cb2
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74275
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix after 'commit 69a13964ea6c ("sb,soc/amd,intel: Add and use
ACPI_COMMON_MADT_LAPIC")' broke interrupt delivery in kernel.
Apparently combination of LAPIC without IOAPIC is too rare
to be well supported.
Change-Id: I5e2fbf358cf644665b897afb0a9404abb5ca1df2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74472
Reviewed-by: Branden Waldner <scruffy99@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Mendocino and Rembrandt don't have an eMMC controller and also don't
have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC
related code from Mendocino.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:268342532
BRANCH=firmware-octopus-11297.B
TEST=Observe kernel ec panic handler run when ec panics
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I37e566e459f39f8bc2dafc3c3915260259730ca6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add boxy supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K4U6E3S4AB-MGCL
2. Hynix H54G46CYRBX267
3. Micron MT53E512M32D1NP-046 WT:B
BUG=b:278983561
TEST=Use part_id_gen to generate related settings
Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: I317f2b31774627706babdea10776af05ab692d1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Yavilla board memory id setting references to yaviks.
This CL aligen it with yaviks.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
H58G56BK7BX068 3 (0011)
MT62F1G32D2DS-026 WT:B 3 (0011)
K3KL8L80CM-MGCT 3 (0011)
H58G66BK7BX067 4 (0100)
MT62F2G32D4DS-026 WT:B 4 (0100)
K3KL9L90CM-MGCT 4 (0100)
H58G66AK6BX070 5 (0101)
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id
Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
To aid in layout, the PCI ports for LAN and SD card were swapped.
SD Card is now on RP3 (clksrc 4)
LAN is now on RP8 (clksrc 3)
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The patch disables PCH USB2 PHY power gating to prevent possible
display flicker issue. Please refer Intel doc#723158 for more information.
BUG=b:279117758
BRANCH=firmware-brya-14505.B
TEST=Verify the build for marasov board
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74627
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The STARYU is the mt8186 detachable reference design, and the STARMIE
is a variant of STARYU. Let's rename the common config from STARMIE
to STARYU, and we can select the STARYU config for the follow up
mt8186 detachable variant.
BRANCH=corsola
BUG=b:275470328
TEST=./utils/abuild/abuild -t google/corsola -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: If75e94e86420b0a216fe7a1a9dee9cb42bbd985c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74654
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Change-Id: I658596da1d84b486126d751b6066c3efd3f65290
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74523
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Google Brya variants like Nissa family selects
`SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` to store CSE FPT
information.
BUG=b:273661726
TEST=Able to build and boot google/marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I234b5d272077de9a6f0a9ba69fa015cda7ebd56c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74387
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about
100ms on google/rex.
TEST=Tests on google/rex with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to
provide common routine for reading skudid and boardid from Chrome EC.
BUG=b:277293398
TEST=builds
Change-Id: I8e42ba23dada9771f335df34275e44e51d645596
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74283
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds RTD3 RPMX mutex to the root port. It is shared between RTD3
and WWAN. The purpose of using this mutex is to prevent OSPM from
calling _ON and _OFF methods while WWAN kernel driver is calling _RST,
which accesses the GPIO pins.
BUG=NA
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated under the root port.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I5b53765453bac0fc96e9651ab347069c7c8bf058
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73384
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This adds RTD3 RPMX mutex to the root port. It is shared between RTD3
and WWAN. The purpose of using this mutex is to prevent OSPM from
calling _ON and _OFF methods while WWAN kernel driver is calling _RST,
which accesses the GPIO pins.
BUG=NA
BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated under the root port.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I809eb84cb1a09deb168040e83041b65237a1b576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73383
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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This adds RTD3 RPMX mutex to the root port. It is shared between RTD3
and WWAN.
BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated under the root port.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia87b5f9d8300d6263c84a586256424799d3a45b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73382
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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The mp2 PCI device is still present when no mp2 firmware is loaded. When
this device isn't explicitly enabled in the mainboard's devicetree, the
chipset devicetree default of the device being disabled is used. This
results in coreboot's resource allocator not allocating resources to
the device and since the bridge doesn't have enough MMIO space reserved,
the Linux kernel can't assign resources to it. Enable the mp2 device in
the mainboard's devicetree so that it gets its resources assigned by
coreboot.
BUG=b:277217097
TEST=builds
Change-Id: I21885c51ff08846b456675090946f381843ef5e6
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74277
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the audio co-processor in the device tree.
BUG=b:277214614
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I1e1749359804960bbd75d869385b9071e7f33be7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74276
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Because WD SSD drive isn't holding the clock low for some reason.
So we change to read eMMC clkreq signal instead.
BRANCH=none
BUG=b:278495684
TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74583
Reviewed-by: Chao Gui <chaogui@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Add the new memory support:
Samsung K4UBE3D4AB-MGCL
BUG=b:274373361
BRANCH=firmware-volteer-13672.B
TEST=FW_NAME=delbin emerge-volteer coreboot
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ie88c25b4b0f88ed299711f2b6b94006d5301554c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74556
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Configure GSC I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for GSC device and enable the required
config items.
BUG=b:275959717
TEST=builds
Change-Id: I6e235356b252a7b68a42da128ffd3189a829f117
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74111
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers,
hence it makes sense to have a unified name across different device drivers.
BUG=b:278310435
BRANCH=firmware-brya-14505.B
TEST=Verified that the _DSD object is still present in the SSDT.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5a69a47e67f6acaad5a5d1b67e437c5a41bebf3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74499
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the boxy variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:277529068
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BOXY
Change-ID: Ief22eb000421c23abf6de3f99eb860bdae1e7919
Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add eSPI configuration for myst. Ensure the additional windows are used
and remove unnecessary addresses from the range used on skyrim.
BUG=b:275953893
TEST=builds
Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74110
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the `TcssD3ColdDisable` option in devicetree, as it exists
in Kconfig. The setting is only used on `starlabs/starbook` which
selects D3COLD_SUPPORT so the UPDs will not change.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing
something with S3, but it's actually disabling D3Cold support.
Remove it, and instead use D3COLD_SUPPORT so it's clear what the
option is doing.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add PCIe RTD3 support so the NVMe gets placed into D3 when entering s0i3
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B
v0.7
Update devicetree to reference the updated DXIO descriptors.
TEST=boot birman and note the devices show up in the logs correctly
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update the EC GPIO values for Birman, per schematic # 105-D67000-00B
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Icd9df120f555eb06f920f6263a8d2ab45c05baec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73971
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial fch irq routing table for Myst.
BUG=b:275946702
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74109
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Skyrim variants, the eMMC reset GPIO should be SSD_AUX_RST_L (GPIO6).
Update the port_descriptors to link the correct reset GPIO. Data
is from the skyrim variant schematics and go/skyrim-gpios.
BUG=b:278759559
TEST=reboot: 5 iterations
suspend_stress_test: 10 iterations
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74512
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as crota is using a converged firmware image.
BUG=b:267249674
BRANCH=firmware-brya-14505.B
TEST="FW_NAME=crota emerge-brya
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage"
Cq-Depend: chromium:4430832
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I448c58f93fddc44904c1f5ef3f8939618eff536f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Add sdram configs:
- RAM code 0x33: sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB SPD for
K4UBE3D4AB-MGCL 4GB
- RAM code 0x34: sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB for
H54G68CYRBX248 8GB
BUG=b:278644249
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If5b484b5324ba39dbb220f12bdb8344ecb5c4da5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73469
Reviewed-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing
something with S3, but it's actually disabling D3Cold support.
Rename it to D3COLD_SUPPORT to make it clear what it's doing.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Add supported memory part in mem_parts_used.txt, then generate.
K4UBE3D4AB-MGCL
BUG=b:267539938
TEST=run part_id_gen to generate SPD id
Change-Id: Iee41bb4511f2d77e5ddc2798f9d4db6137ed818d
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74497
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The M.2 NVMe SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF),
hence update the correct bridge number in the device tree.
TEST: Builds and boots, the device enumerates.
[DEBUG] PCI: 00:02.4 [1022/14ee] enabled
[DEBUG] PCI: 01:00.0 [144d/a80a] enabled
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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