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2021-03-28mb/google/zork: update telemetry settings for gumbozKevin Chiu
update telemetry to improve the performance. BUG=b:182753072 BRANCH=zork TEST=1. emerge-zork coreboot 2. run AMD SDLE stardust test => pass Change-Id: I6e4d0c6fcd740d82edf073fb307aa6a6b09ec78a Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51790 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/google/caroline: Re-enable I2C2 / fix digitizerMatt DeVillier
Caroline has a Wacom W9013 digitizer on I2C2, which was incorrectly disabled in commit d957d12e6 [mb/google/glados: clean up variant devicetrees] as part of preparation for converting to overridetree format. Test: build/boot, verify digitizer now available under Linux Change-Id: I234bc0126b5d13c22a663d6544382890b312ce63 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configurationMaulik V Vaghela
List of changes: 1. Add correct board Id for ADL-M LP5 configuration 2. Add spd hex files for LP5 Micron part 3. Update memory.c file with correct Dq-dqs and byte mapping for LP5 BUG=None BRANCH=None TEST=Build is successful for ADL-M RVP Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-03-28mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configurationMaulik V Vaghela
List of changes: 1. Add board Ids for ADL-M LP4 configuration 2. Add spd hex files for LP4 configuration 3. Update memory.c file with correct Dq-dqs and byte mapping for LP4 BUG=None BRANCH=None TEST=Build and boot is successful for ADL M LP4 RVP Change-Id: Id817faee3fff2a8a911ebda35774dfb6ddc5524b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/intel/adlrvp: Configure GPIOs for ADLRVP-MVarshit Pandya
List of changes: 1. Add separate file for ADL-M GPIOs 2. Configure GPIOs as per the schematics of ADL-M RVP TEST=Able to build ADL-M Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-03-28mb/intel/shadowwmountain: Enable CSE Lite SKU for shadowmountainSridhar Siricilla
During the initial phases, the development and validation teams have to deal with both Consumer SKU and Lite SKU firmware. Having the support for CSE Lite enabled by default in coreboot helps in integrating both the SKUs. With this we only have to interchange the CSE region in the full BIOS image without having to worry about Kconfigs. Eases the build and integration flow. TEST=Verified build for Shadowmountain Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2ebf4da1b8c1df2e9c43b6e3bb688a9f8db652d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51496 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/intel/adlrvp: Enable CSE Lite SKUSridhar Siricilla
During the initial phases, the development and validation teams have to deal with both Consumer SKU and Lite SKU firmware. Having the support for CSE Lite enabled by default in coreboot helps in integrating both the SKUs. With this we only have to interchange the CSE region in the full BIOS image without having to worry about Kconfigs. Eases the build and integration flow. TEST= Built and booted on ADL-P LP4 RVP Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/google/dedede/var/sasuke: Add support zinitix touchpadSeunghwan Kim
This change adds support zinitix touchpad for sasuke. BRANCH=dedede BUG=None TEST=built and checked touchpad worked on sasuke Change-Id: I85794311c49e33c4683482e125bea5ca2dbacfa8 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28grunt/barla: add Realtek ALC5682 codec supportKevin Chiu
ALC5682 i2c address: 0x1A BUG=b:171755306 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I8bc571104bebe02acf86507774580effc808beb6 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28mb/google/kukui: fine tune the data lane trailJitao Shi
ANX7625 requires customized hs_da_trail time. So override the data trail for ANX7625. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Jacuzzi Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I620035363507daaa19e3c272a44059c17be29af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
2021-03-27mb/intel/dcp847ske: Drop useless MCHBAR writesAngel Pons
There's no need to write the GDCRTRAININGRESULT registers after raminit. Change-Id: If604920fe7a3bee96f72f8aff5e96f0e25548f18 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50534 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27mb/intel/adlrvp: Allow GPIO PM override to disable dynamic GPIO PMSubrata Banik
This patch allows overriding GPIO PM miscconfig register for each GPIO community to avoid dynamic clock gating. TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0] are set to '0'. Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik
Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-26mb/google/zork/vilboz: Enable ALC1015 AMP driverFrank Wu
Enable ALC1015 driver for audio support in vilboz BUG=b:177971830 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: If0abfd6570579fe637a7bef31de2f01d58f3bdf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-26mb/intel/shadowmountain: Disable the unused CPU PCIe RPV Sowmya
This patch disables the unsued CPU PCIe RP for shadowmountain. TEST= Boot shadowmountain and verify the device is disabled. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Ide2badb06178fca8ff5cf51d8573a14635e190cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51772 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-26mb/intel/adlrvp: Remove static VBT stitchingMaulik V Vaghela
Currently, we used to stitch extra VBT files to ADLRVP build using Makefile. With enablement of emerge build, we should be able to integrate more than 1 VBT binaries using ebuild. This removing these lines to avoid compilation issues in emerge builds BUG=None BRANCH=None TEST=Check if compilation passes on emerge build. Stitched additional VBT files using emerge and checked that coreboot picks up correct VBT. Change-Id: I69f1cc6c07415515ff85180fdd7cc5de11b4d805 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-26mb/google/brya: Update ddr configSubrata Banik
Fixed ddr config to override the FSP default value. BUG=b:182772421 TEST=Built image and passed memory training. Without this change: RcompTarget on Lpddr4x = { 40, 40, 30, 30, 30 } With this change: RcompTarget on Lpddr4x = { 40, 30, 30, 30, 30 } Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib07ff36496828b5de78ed928b294a400ad08865f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-26soc/intel/alderlake: Add provision to override Rcomp settingsSubrata Banik
Add function to allow overriding the RcompResistor and RcompTarget UPDs from mainboard if required. Mainboard users can pass required rcomp from memory.c file. Refactor ddr_config structure to take out rcomp related variable outside for all memory type to override if required. BUG=b:182772421 TEST=Able to override the default RcompResistor and RcompTarget values. Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26soc/intel/alderlake: Align RcompResistor definition as per MRCSubrata Banik
List of changes: 1. Alder Lake MRC is expecting a RcompResistor value of word width. Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot is passing an array of RcompResistor which is not completely in use. Note: Rcomp resistor value represents rcomp resistor attached to the DDR_COMP pins on the SoC. 2. Also, remove usage of '&' with memcpy the required value into RcompTarget array. 3. Also, update RcompResistor value for ADLRVP. BUG=b:183341229 TEST=Enable FSP debug log to verify the override value for RcompResistor is reflecting correctly. Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-25mb/amd/majolica: Enable IO port 2E/2FZheng Bao
MEC1701 can be accessed by IO port 2E/2F Change-Id: I31f1b147476ec487e64f3c30b3cf514b45ced416 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-25mb/google/zork/variants/baseboard: USB2 HS phy settingsJulian Schroeder
Set default USB2 HS disconnect threshold to maximum to avoid false disconnects that eventually lock up the xHCI controller BUG=b:174538960 TEST=suspend_stress_test -c 50 on vilboz and morphius. Sample set of USB2 HS devices connect and disconnect successfully Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: Ic921d850a0bdd717a2a7e50e9e6f65e39e0607bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51265 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25mb/google/hatch/var/genesis: Fix PCIe root portsJoe Tessler
The previous "PCIe port" numbering was incorrect and resulted in several PCIe devices failing to enumerate. With lane reversal, these numbers are all backwards. This explains the confusing mapping of Clock Source #1 to Root Port #9 in https://review.coreboot.org/c/coreboot/+/50101. We were confusing "Root Port" vs "PCIe Lane". This change addresses the port vs. lane confusion in the device tree configurations. It also adds more detailed documentation to a future reader (i.e., me) to avoid this blunder. BUG=b:181633452,b:181635072,b:177752570 TEST=build AP firmware; flash device BRANCH=none Change-Id: I47edf0b0af1bdcf86b89f17ad2a1f128ef9e9f7a Signed-off-by: Joe Tessler <jrt@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-25mb/google/hatch/var/genesis: Add missing GPIOsJoe Tessler
After revisiting the genesis GPIO table and schematics for EVT closure, I discovered several missing and/or incorrectly documented GPIO pin mappings. Now the GPIO pin names and functions should match what's written in the latest schematics. BUG=b:181633452,b:181635072,b:177752570 TEST=build AP firmware; flash device BRANCH=none Change-Id: I73e6733bce761b00717091834c7a49e85154f80b Signed-off-by: Joe Tessler <jrt@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51677 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25nb/intel/haswell: Decouple mainboard USB config from MRCAngel Pons
With this change, only raminit.c uses pei_data.h definitions. With MRC cornered, making it optional is just a matter of writing a replacement. USB config definitions will be moved to Lynx Point code in a follow-up. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-25mb/google/volteer: Collis: Update SPD tableFrankChu
Add memory table to "mem_list_variant.txt", and command to generate files: go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/collis/memory/ src/mainboard/google/volteer/variants/collis/memory/mem_list_variant.txt DRAM Part Name ID to assign MT53D512M64D4NW-046 WT:F 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) BUG=b:182227204 TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I773c65c0b6d5e868572530305ab8a61a0dd1532d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-25mb/google/dedede/var/cret: Enable touchscreenDtrain Hsu
Add ELAN and Weida touchscreen into devicetree for cret. BUG=b:180547621 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Icdb7aabe4a9ecd7b5a057c4644799aa537adb6ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/51737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-25mb/google/dedede/var/cret: Configure I2C ports and touchpadDtrain Hsu
1. Support Elan touchpad. 2. Support JYT touchpad. 3. Follow schematic to disable I2C1 and I2C3. BUG=b:183454249, b:180547781 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I8c150c3f65d0e057d5ba1b07ec1c20886f02ef6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51726 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25mb/google/dedede/var/cret: Generate SPD ID for supported partsDtrain Hsu
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. H9HCNNNBKMMLXR-NEE 2. MT53E512M32D2NP-046 WT:F 3. K4U6E3S4AA-MGCR BUG=b:183057749 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iacfdd9a27f126ba4b97d1a6493bcc09bb31454a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51619 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25mb/google/dedede/var/cret: Configure USB port settingsDtrain Hsu
Follow schematic to modify USB port settings. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 0 USB2 [3]: LTE USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: Camera WFC USB2 [7]: Integrated Bluetooth USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: LTE BUG=b:182973703 BRANCH=dedede TEST=Build the coreboot image. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I80447d6ac3422f858a9022f550b4f42353819405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-25mb/google/dedede/var/cret: Configure GPIODtrain Hsu
Follow schematic to modify some GPIO pins. GPP_C12 - NC Pin, UP_20K GPP_C18 - NC Pin GPP_C19 - NC Pin GPP_C22 - NC Pin, UP_20K GPP_D12 - NC Pin GPP_D14 - NC Pin GPP_D15 - NC Pin GPP_D19 - NC Pin GPP_D20 - NC Pin GPP_E0 - NC Pin GPP_E2 - NC Pin GPP_H1 - NC Pin GPP_H6 - NC Pin GPP_H7 - NC Pin GPP_G0 - NC Pin GPP_G1 - NC Pin GPP_G2 - NC Pin GPP_G3 - NC Pin GPP_G4 - NC Pin GPP_G5 - NC Pin, UP_20K GPP_G6 - NC Pin GPP_G7 - NC Pin BUG=b:183078393 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Id966884f3e36303b636fa13ef9baecccae87604a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-24mb/purism/librem_mini: Drop superfluous devices from devicetreeMatt DeVillier
The 'device pci 00.0 on end' entries are not necessary for socketed devices unless a chip driver needs to be bound to a device, so remove them from the devicetree. Also remove the `drivers/wifi/generic` chip driver as it was not necessary either. Change-Id: Id5f2e34d98b236f9cfac9f0afd8a8017e349603f Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-24mb/google/guybrush: Temporary fix to set eSPI muxMathew King
This change allows guybrush EC communication while other patches in the SOC code are worked on. BUG=b:183149183 TEST=Boot guybrush with EC comunication Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I56fb64d4c065cf0665025346218cc66d77dacb52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51665 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24mb/google/guybrush: disable KBRSTENKangheui Won
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a logic to clear it. BUG=b:183340503 TEST=build Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-24mb/google/volteer/variants/drobit: Modify touchpad power sequenceWayne3 Wang
Modify power sequence of touchpad to meet the definition in the spec. BUG=b:178353432 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by EE team. Change-Id: I8b8e383223d017223c36044efdf21738fe26d2ea Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51514 Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24mb/emulation/qemu-q35: Fix format specifier for a `size_t`Benjamin Doron
Fix compilation on GCC 10.2.1 Change-Id: I47d29ef065f57f171f429bb6a368bc86e31acee9 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-24mb/system76/gaze15: Add System76 Gazelle 15Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux 20.10 and Windows 10 Not working: - Discrete/Hybrid graphics This requires a new driver to work correctly, which will be added and enabled later. Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24mb/intel/adlrvp: Enable CnviBtAudioOffloadUsha P
This change enables CnviBtAudioOffload. FSP is invoked to configure BT over USB and BT I2S pins for cAVS connection. BUG=None TEST=Verified BT offload working on ADL RVP Signed-off-by: Usha P <usha.p@intel.corp-partner.google.com> Change-Id: I1185a6c2295bae7d469be4da86502506adbeb8cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-24soc/mediatek: Use MRC cache API for asuradaYu-Ping Wu
Use the MRC cache API for asurada, and sync dramc_param.h with dram blob (CL:*3674585). With this change, the checksum, originally stored in flash, is replaced with a hash in TPM. In addition, in recovery boot, full calibration will always ne performed, and the cached calibration data will be cleared from flash. This change increases ROMSTAGE size from 236K to 264K. Most of the increase is caused by TPM-related functions. Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be moved to soc folder. With this CL, there is no significant change in boot time. Normal AP reboot time (fast calibration) is consistently 0.98s as before, so this change should not affect the result of platform_BootPerf. BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Hayato boots with both full and fast calibration BRANCH=none Cq-Depend: chrome-internal:3674585, chrome-internal:3704751 Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-23mb/google/octopus: Wake up AP on AC plug and unplugDerek Basehore
This patch makes all Octopus variants resume from S0ix/S3 on AC plug and unplug. Change-Id: Iab054d77368bf2047b6d523188b8c401a7643aaa Signed-off-by: Derek Basehore <dbasehore@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-23haswell boards: Use zero length for disabled USB portsAngel Pons
For disabled USB ports, the length setting does not matter. In future commits, disabled USB ports will end up with length field set to zero. Change-Id: I7613e1b0c89c0b58eca790ca14fcd1633c8a93af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-03-23nb/intel/haswell: Use unshifted SPD addresses in mainboardsAngel Pons
It's common to use the raw, unshifted I2C address in coreboot. Adapt mainboards accordingly and perform the shift in MRC glue code. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23mb/google/kukui: Add a new config 'Makomo'Sunway
A new board introduced to Kukui family. BUG=None TEST=make # select Makomo BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I42b84e2c0926e755ba210fc8baac19f8ed2c4e57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51565 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23mb/google/volteer/variants/delbin: Disable PmcUsb2PhySusPgEnableRavi Sarawadi
eDP panel flicker during system idle state is observed. Disabling USB2 SUS well power gating can remove flicker symptom. Please refer to doc#634894 for more details. BUG=b:182323059 BRANCH=None TEST=Boot and confirm no display flicker. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Icadf9c494fab82b219317c3ca3b04f633b543083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2021-03-22mb/google/volteer/variants/eldrid: Include SPD for H4AAG165WB-BCWENick Vaccaro
Add SPD support to eldrid for DDR4 memory part H4AAG165WB-BCWE. Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated with H4AAG165WB-BCWE DDR4 memory parts. BUG=b:181732562 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Change-Id: I38cfe3eb26b00563ce17df3a3ac2a0a846f2ae00 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51667 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/dedede: Create cret variantIan Feng
Create the cret variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:181325655 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CRET Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I700201cf81b25c6776df3ec9fc843cd9bd8c88c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-22mb/google/volteer/variants/copano: Configure specific DPTF parametershao_chou
Configure board specific DPTF parameters for copano BUG=b:176961219 BRANCH=firmware-volteer-13672.B TEST=build and verify by thermal team Change-Id: Ibce67f81503b84b58798bc198947e61907276ad3 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51561 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22purism/librem_14: add on-board LAN deviceMichael Niewöhner
On-board devices should be present in the devicetree, so that `.on_mainboard` field of `struct device` is `1`. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I3678514482724377bcdfcbdc7f2c5b312a48b2c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-03-22mb/asus/p2b: Refactor southbridge ACPI stuffKeith Hui
Move (remaining) southbridge ACPI stuff into one file under sb/intel/i82371eb, that is simply included from the board's \_SB scope. Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22lynxpoint/broadwell: Rename LP GPIO config globalAngel Pons
Do not use the same name as the non-LP GPIO config. This allows checking at build-time that a mainboard uses the correct GPIO config format. Without this commit, there are no build-time errors when using the wrong format of GPIO config, but there would be undefined behavior at runtime. Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the USB config arrays for asrock/b85m_pro4). In both cases, building failed because the necessary GPIO config global is not defined, as expected. Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/zork: Enable SSFC as upper 32 bit of fw_configFrank Wu
To append SSFC to top 32 bits of fw_config. BUG=b:177971830 BRANCH=firmware-zork-13434.B TEST=Build coreboot and get the value of SSFC. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iab1596f1cc8fbbf45e6a9269351bf422a43f3583 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51655 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/brya: Enable S0ixSugnan Prabhu S
This change enables S0ix for brya platform. BUG=b:181843816 TEST=Built image and booted to kernel. Change-Id: Idc6f7fce9779ef4458375becebf5dc65b228abeb Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51526 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/dedede/var/storo: Add USB Port ConfigurationZanxi Chen
Add USB Port configuration into devicetree for storo BUG=b:177389444 BRANCH=dedede TEST=built firmware and verified USB3.0 function is OK Change-Id: I1527c7178ffac9b2322eb65aab6e2086d949e47c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-22mb/google/zork: Move max98357a out of baseboardEric Lai
Not all of dalboz variants support the this amp. Thus, move out of baseboard. BUG=b:182815488 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If708574f5fb18dd3b4f2ef978529a16a40d5dc0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-22mb/google/guybrush: Enable AP <-> H1 communicationKarthikeyan Ramasubramanian
Configure H1 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for H1 device and enable the required config items. BUG=b:180528902 TEST=Build Guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22mb/google/guybrush: Add initial I2C configurationKarthikeyan Ramasubramanian
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. I2C GPIOs are configured as required in CB:50091. BUG=b:180531661 TEST=Build guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I67690fbd25639879a730260aaca4cddb5e47bbc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22mb/amd/majolica: Set IOMUX to enable I2C2 & I2C3Zheng Bao
Change-Id: I142c06c150214d58acc04b8c6b3b027fff0256db Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-03-22soc/amd/common/block/i2c: Move SoC agnostic parts into commonKarthikeyan Ramasubramanian
The logic behind I2C bus initialization, I2C MMIO base address getter and setter, I2C bus ACPI name resolution are identical for all the AMD SoCs. Hence moving all the SoC agnotic parts of the driver into the common driver and just configure the SoC specific parts into individual I2C drivers. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. Verify some I2C peripheral functionality like trackpad and touchscreen. Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mainboard/: Register chipset_lockdown on xeon_sp mainboardsMarc Jones
Set chipset_lockdown in devicetree for recommended security settings. Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mb/purism/librem_cnl: Add new board/variant Librem 14Matt DeVillier
Add support for the CometLake-U based Librem 14 laptop. Change-Id: I24a2a92091cc272638ecaf8ea23a896cab8a7153 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51549 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20google/trogdor: Add new variant MarzipanKevin Chiu
This patch adds a new variant called Marzipan that is identical to Lazor for now. BUG=b:182181519,b:182018606 BRANCH=master TEST=make Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20mb/google/trogdor: Add support for SPI_FLASH_GIGADEVICExuxinxiong
Add support SPI_FLASH_GIGADEVICE for some project. BUG=b:182246432 BRANCH=trogdor TEST=emerge-strongbad and test with power on. Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: I6ab948909f4e17b4b992be6d699646f7a62bef7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-19mb/lenovo/x200: Fix boot-time docking stateKevin Keijzer
The X200 would undock itself when waking up from S3, requiring a physical reconnection before the dock would work again. Similar to 4611ad8, this reintroduces h8_mb_init() for the X200. A hook function h8_mb_init() will be called at the end of h8_enable(), in place of the ancient h8_mainboard_init_dock(). This should fix the regression the X201 and T410 also suffered from for the X200. Change-Id: Icb6dd145e56b90e0e04133810c5e9ac7b641ad68 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51123 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/scaleway/tagada: Don't change FIAMUX when Security Override is setJulien Viard de Galbert
This will not enable M.2 SATA drive if the ME config was lost (For instance after flashing a full flash factory image) This is required so that the system can boot without FIA MUX error during flash update procedure. Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19mb/google/volteer/var/elemi: Config GPP_B7/GPP_B8 as NCWisley Chen
elemi does not use the GPP_B7/GPP_B8, so config to NC. Currently, there is no functional impact. BUG=b:182981460 TEST=emerge-volteer coreboot, boot into OS, and suspend/resume successfully. Change-Id: I7b491fd595b0e77e6dcce08e3172dbe592f63c37 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19mb/purism/librem_cnl: drop MAX_CPUS from KconfigMatt DeVillier
No need to restrict this further than the platform default, and will be problematic with the addition of the upcoming 6C/12T Librem 14 board. Change-Id: I1913992ec12578e1ad3bf6bf679d1a35a46d7370 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19mb/{clevo/cml-u,system76/lemp9}: Clarify `gen2_dec` useAngel Pons
This I/O range is for a PM channel on the EC, not the PCH PMC. Change-Id: I64422e537c1edcd0673cf87f16139fb117b10e75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51604 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19nb/intel/haswell: Consolidate memory-down SPD handlingAngel Pons
Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to a struct instead of an array, and update all the mainboards accordingly. Currently, the only board with memory-down in the tree is google/slippy. Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts the channel population accordingly. Then, northbridge code reads the SPD file and uses the index that was read in `mb_get_spd_map`, and copies it to channel 0 slot 0 unconditionally. MRC only uses the first position of the `spd_data` array, and ignores the other positions. In coreboot code, `setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has to account for this. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/google/slippy: Correct memory-down SPD handlingAngel Pons
MRC only uses the SPD data for the first index, and ignores the rest. Moreover, index 1 corresponds to the second DIMM on the first channel, which does not exist on ULT (only one DIMM per channel is supported). Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge code to retrieve the serial number from the correct SPD data block. Tested on Google Wolf, both channels are still correctly detected. Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-18mb/google/brya: Implement SLP_S0_GATE signalTim Wawrzynczak
The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to provide an indication to the rest of the platform when the system is entering its software-initiated low-power state (i.e. S0ix). This lets the platform distinguish between opportunistic S0ix entry and the runtime suspend mechanism. BUG=b:180401723 TEST=abuild Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/amd/majolica: Generate OIPG PackageRaul E Rangel
This fixes the unknown reference errors for OIPG. Since Majolica doesn't actually have any of the GPIOs ChromeOS uses, we leave the arrays empty. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifeae84e0ccab187a4e7131cd6ea9e1336d79df67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51536 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Add eSPI GPIO back to init tableMathew King
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I9896db41dbe2812856357510bc4420482e73ab3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51547 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Configure UART0 gpio in early stageMathew King
BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8aa54acf1fa9295b27c33a0066432665e6e3755c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-18mb/ocp/deltalake: Initialize VPD 'coreboot_uart_io' with default value 1Johnny Lin
In case the VPD variable cannot be read. Change-Id: I79fae6f4b4aad91a4040387ca6ddee8dfcc34d90 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51559 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/mancomb: Configure eSPI GPIOs in early stageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifa51705b3b5aab16f9cd2c11084220aafacd2774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Configure early GPIOs in earliest stageEric Lai
Configure early GPIOs in verstage if it is run in PSP otherwise configure them in bootblock. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic1faeea59462319c1652c69034b4dde01669e13b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Enable internal graphics deviceEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0f5026b77513118a6c21eca78c9788c0bdc7ec6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Enable verstageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic07a3ac556637919742fcbe899ee3fdfac38bb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/zork/var/shuboz: adjust telemetry settingsKane Chen
According to stardust test tracking report to adjust telemetry setting. VDD Slope : 30518 -> 30595 VDD Offset: 435 -> 77 SOC Slope : 22965 -> 24063 SOC Offset: 165 -> 105 BUG=b:182399760 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie7e6af77bdaad6cc964ac206a69ccb854aae869f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-18mb/prodrive/hermes: Disable HDA codec Port E by default on R04+Angel Pons
If the board settings aren't valid, Port E uses the settings for earlier board revisions, which is undesired. Disable Port E by default on R04+. Change-Id: I03bd50b915a2120283b77179debaa735bb7ef027 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51529 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP initArthur Heymans
Tested with and without -enable-kvm, with -smp 1 2 and 32. Change-Id: I612cebcd2ddef809434eb9bfae9d8681cda112ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48262 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()Julius Werner
In pursuit of the goal of eliminating the proliferation of raw region devices to represent CBFS files outside of the CBFS core code, this patch removes the get_spd_cbfs_rdev() API and instead replaces it with spd_cbfs_map() which will find and map the SPD file in one go and return a pointer to the relevant section. (This makes it impossible to unmap the mapping again, which all but one of the users didn't bother to do anyway since the API is only used on platforms with memory-mapped flash. Presumably this will stay that way in the future so this is not something worth worrying about.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Replace more instances of cbfs_boot_locate() with newer APIsJulius Werner
In pursuit of the eventual goal of removing cbfs_boot_locate() (and direct rdev access) from CBFS APIs, this patch replaces all remaining "simple" uses of the function call that can easily be replaced by the newer APIs (like cbfs_load() or cbfs_map()). Some cases of cbfs_boot_locate() remain that will be more complicated to solve. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17mb/google/kukui: Add new config 'cozmo'Lucas Chen
New board 'cozmo'. BUG=b:181144502 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Ia0ec1d89444d2634bfcfb3475a422f4e4ae92b7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-17mb/google/dedede/var/sasukette: Enable ALC1015 AMP (Auto Mode) driverwuweimin
Enable gpio mode driver for ALC1015 AMP Auto Mode. BUG=b:176956779 BRANCH=dedede TEST=ALC1015Q-VB drive speaker OK Change-Id: Iaa5650e120362e81fa36530f6a207c9c07e1139a Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-17mb/google/dedede/var/lantis: Update DPTF parametersTony Huang
DPTF paramerters from thermal team. 1. PL2 =15W 2. Add TSR sensor charger, 5V regulator BUG=b:177249297 BRANCH=dedede TEST=build image and verified by thermal team. Change-Id: Ia5f6cc2a4564bb5558cbaca8daf31ee70145019f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-17mb/intel/shadowmountain: Update HDMI audio mode to 8TSugnan Prabhu S
This patch sets the HDMI audio mode to 8T as required by the latest FSP version v2081_02 TEST: HDMI audio codecs detection is failing without this change. Change-Id: Ie5a825da7d199c9ee61e64d8f4ee7dec28fdaacd Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-17mb/intel/shadowmountain: Disable xDCISugnan Prabhu S
This patch disables the xDCI which is causing PC8 to PC10 state transitions during sleep. TEST: Confirmed that the transition is happening with this change. Change-Id: I9bbf7b52c36954600d7e66f9b03fad39b8881a5f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-03-17sar: Fix semantics of `get_wifi_sar_cbfs_filename()`Furquan Shaikh
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then `get_wifi_sar_limits()` assumes that the default filename is used for CBFS SAR file. This prevents a board from supporting different models using the same firmware -- some which require SAR support and some which don't. This change updates the logic in `get_wifi_sar_limits()` to return early if filename is not provided by the mainboard. In order to maintain the same logic as before, current mainboards are updated to return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default case. Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17drivers/wifi, mb/google: Drop config `WIFI_SAR_CBFS`Furquan Shaikh
Now that SAR support in VPD is deprecated in coreboot, there is no need for a separate Kconfig `WIFI_SAR_CBFS` as the SAR table is only supported as a CBFS file. This change drops the config `WIFI_SAR_CBFS` from drivers/wifi/generic/Kconfig and its selection in mb/google/.../Kconfig. wifi_sar_defaults.hex is added to CBFS only if CONFIG_WIFI_SAR_CBFS_FILEPATH is not empty because current mainboards do not provide a default SAR file in coreboot. Thus, CONFIG_WIFI_SAR_CBFS_FILEPATH is updated to have a default value of "". BUG=b:173465272 Cq-Depend: chromium:2757781 Change-Id: I0bb8f6e2511596e4503fe4d8c34439228ceaa3c7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-16AGESA,binaryPI boards: Drop invalid MP table filesKyösti Mälkki
If we spot any error in the file, treat it as untested and broken copy-paste. Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16AGESA,binaryPI boards: Move IRQ table programmingKyösti Mälkki
IRQ programming should be done outside (obsolete) MP table generation. Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38564 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16mb/google/dedede/var/storo: Add USB Port ConfigurationZanxi Chen
Add USB Port into devicetree for storo BUG=b:177389444 BRANCH=dedede TEST=built firmware and verified USB3.0 function is OK Change-Id: I4d5160ff23d2bd386cb33164b580e6d6f3bf30fd Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Add camera supportZanxi Chen
Add camera support in devicetree and associated GPIO configuration. BUG=b:181729304 BRANCH=dedede TEST=built blipper firmware and verified camera function is OK Change-Id: I806ec207a454d4383aca093159553b7e618e16b2 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Add codec and speaker amplifier supportZanxi Chen
Add audio codec and speaker amplifier support into devicetree BUG=b:181732574 BRANCH=dedede TEST=built blipper firmware and verified audio function is OK Change-Id: Id4633649b5e0595ed99a40ae35eb54b005154604 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Enable touchscreen for blipperZanxi Chen
Add G2 and ELAN touchscreen into devicetree for blipper. BUG=b:181098785 BRANCH=dedede TEST=built blipper firmware and verified touchscreen function is ok Change-Id: Ie0bfc2972fc1a33a6f02495d3976b816209e956b Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/sasuke: Configure GPP_B7 as GPO_HIGHSeunghwan Kim
Configuring GPP_B7 as GPO_HIGH. Sasuke doesn't have SAR sensor, GPP_B7 is routed to the LTE module and is kept high so that the LTE module uses the default emission power. BUG=b:180492044 BRANCH=firmware-dedede-13606.B TEST="FW_NAME=sasuke emerge-dedede coreboot" Change-Id: Ib38c649830db2291b3a2a771f5c884acf37dcbeb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51049 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16mb/google/asurada: fix boot failure when reading SKU IDHung-Te Lin
The SKU IDs also need mapping table when reading voltages. BUG=None BRANCH=asurada TEST=emerge-asurada coreboot Change-Id: Ice91961d6c33cfa27254221663edca1547c9ddcc Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16mb/google/guybrush: Add initial fch irq routingMathew King
BUG=b:181972598 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1abb070324254e21b03bfe00d6eee3b70120564c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-15mb/google/guybrush: Enable eSPI VW SCI eventsMathew King
Guybrush does not have a dedicated SCI pin so it uses VW. BUG=b:181134664 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I12fb7c23718ad2350478b89b321e9f0aa099e53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/magolor: Fix DPTF passive and critical policiesKarthikeyan Ramasubramanian
Some of the temperature sensors defined in baseboard do not exist in magolor. With the format the DPTF policies are defined in magolor, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=None BRANCH=dedede TEST=Build and boot to OS in magolor. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I43f0b188e49e24657db055ce898ce159d499a22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 12:32:29 +0000