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2015-04-10Add google/veyron_mighty boardKatie Roberts-Hoffman
Essentially a copy of veyron_jerry for now. BUG=chrome-os-partner:33269 TEST=build Change-Id: Ie2d115d57fe4b6359fa6bb16a2e85e88ec99e991 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9ec25b9cf2985786e55f0b85c3849ccbd42bddd4 Original-Change-Id: Icc45c8f8bf9f6916ba7187dde277d15cc60df8a2 Original-Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230961 Original-Commit-Id: 407b8b74a068220d8051dd0d85d9c4ec3ea14d51 Original-Change-Id: I546dbc41ccd191159e96b851424fcb37902a57ec Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231691 Reviewed-on: http://review.coreboot.org/9554 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10rockchip: support displayhuang lin
Implement VOP and eDP drivers, vop and edp clock configuration, framebuffer allocation and display configuration logic. The eDP driver reads panel EDID to determine panel dimensions and the pixel clock used by the VOP. The pixel clock is generating using the NPLL. BUG=chrome-os-partner:31897 TEST=Booted Veyron Pinky and display normal BRANCH=None Change-Id: I01b5c347a3433a108806aec61aa3a875cab8c129 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e4f863b0b57f2f5293ea8015db86cf7f8acc5853 Original-Change-Id: I61214f55e96bc1dcda9b0f700e5db11e49e5e533 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219050 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9553 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: select VIRTUAL_DEV_SWITCHDavid Hendricks
Like most newer Chromebooks, Pinky and Jerry do not have physical dev switches. BUG=chrome-os-partner:33395 BRANCH=none TEST=built and booted on Pinky, crossystem prints a valid value for devsw_cur instead of an error. Change-Id: If97ffa6f99eb31c05915f3ee82aaf6bd252d29e4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db302d7286d3e7df9442928dac1d611a2c103163 Original-Change-Id: I186518a59699d293c7938221b3ae45b27361c255 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229680 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9552 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Adapt to new board revisionsJulius Werner
This patch adds support for Pinky rev3 (board ID 2) and Jerry rev2: the power button GPIO changed polarity to low, the 5V_DRV pin for USB power was moved to the AP again (welcome back!), and the EMMC_RST_L is now finally on a port with the right IO voltage so we don't need any weird pull-up tricks anymore. Since there are very few Jerry rev1s around, we'll just move it over to the new code directly without introducing board ID differences (also, because I have no idea how they stuffed it this time... is this one actually called rev2?). BRANCH=None BUG=None TEST=Still boots on my Pinky rev2, though that doesn't say much. Change-Id: Id11044cedcaac5a4ae07e696893823925107a6db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 55344a9518ff04edcef01bcd40817e9e4b613717 Original-Change-Id: Iddee360fbda357ecde4ae5fbb5c3a01fe0c22474 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229010 Original-Reviewed-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9551 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron_jerry: Port CPU overshoot preventionJulius Werner
This patch ports commit 567f616f (rk3288: slowly raise to max cpu voltage to prevent overshoot) to Veyron_Jerry. It also fixes include ordering and some comment grammar in the affected code. BRANCH=None BUG=chrome-os-partner:32716 TEST=None Change-Id: I4ac14a38e4b3acc4926d4f51f409ff12d9c841cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 679014bc843788e8d4d5f5c7470ae76f8be5e942 Original-Change-Id: I9c0aba40ddd8a0852391df184034baa740d063df Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228938 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9550 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: sdram_get_ram_code() -> ram_code()David Hendricks
This enables RAM_CODE_SUPPORT for veyron* platforms and uses the generic gpio_get_binaries() function to read RAM_ID GPIOs. BUG=chrome-os-partner:31728 BRANCH=none TEST=built and booted on pinky Change-Id: I7a03e42a270bec7036004375d36734bfdfe6e528 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a325b204ff88131dfb0bdd3dfedb3c007cd98010 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ibc4c61687f1c59311cbf6b48371f9a9125dbe115 Original-Reviewed-on: https://chromium-review.googlesource.com/227249 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9549 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron*: use gpio_base2_value() in board_id()David Hendricks
This makes board_id() use the generic gpio_base2_value() function to obtain the value of the board ID straps. BUG=none BRANCH=none TEST=tested on pinky Change-Id: I15c1310889b989c34638fd342011aef5fe7bcec1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcbb8a6998a66531326afe16b232395d49fee64d Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I5847bf1c5b26bcaf7d36103f31bb255b31ff8185 Original-Reviewed-on: https://chromium-review.googlesource.com/228370 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Change VCC10_LCD_PWREN_H to allowed maximum of 2.5VJulius Werner
LDO7 (VCC10_LCD_PWREN_H) is essentially just a glorified GPIO that turns the real VCC10 regulator on or off. We tried setting it to 3.3V since it matches the VCC33_SYS voltage on the input of that regulator. However, we didn't notice that the LDO only supports going up to 2.5V. This patch changes the voltage to the allowed maximum, which should still work fine as an enable line (and is the same value used by the kernel). This removes an assertion error in the ramstage. Also change the PMIC driver to assert maximum VSEL values based on the LDO, because the lower-voltage ones support one more setting. (LDO3 is actually listed to only go up to 0b1111 in the manual, and has a weird jump from 0b1101 -> 2.2V (skipping over 0b1110) to 0b1111 -> 2.5V. I don't know if that's a documentation error or what they were smoking when they designed that, but we don't need to care for now.) BRANCH=None BUG=None TEST=Booted on Pinky, no more ASSERTION FAILED. Change-Id: I38bf99e38822fd0883fd4d0bd9a1b01143545a95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 70f3149efbc3aa9a03ab3fd5be99d17d9c5e1c87 Original-Change-Id: I68a3bb882cf25d98aca8922ede2a17e1ef6524de Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228292 Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: Jerry Parson <jwp@chromium.org> Reviewed-on: http://review.coreboot.org/9547 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron_jerry: Remove board ID based assumptionsJulius Werner
The veyron_jerry board code was just copied over from veyron_pinky 1-to-1. The Jerry board IDs start at 1, but there has never been a Jerry rev0 so we can remove the code for board ID 0 from it. BRANCH=none BUG=None TEST=Booted Jerry image on a Pinky rev2, worked fine. Change-Id: I0f2ffdc577934c1695e8d2dcf71512696ac1d5a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aa36da69ac584b845e15282dae100eec27fc7f12 Original-Change-Id: I45a18b288c8d8b1399ceedf582addcce1c7e857d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228254 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9546 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10veyron: Change eMMC enable pin to be pulled (not driven) highDoug Anderson
The eMMC enable pin is in a 3.3V IO domain. Unfortunately the eMMC expects this pin to be 1.8V. The way we were driving this pin would cause the eMMC to pull power through this pin and that was causing current leaks. In future revisions of hardware we should move this pin somewhere more legit. However, in the current hardware we can get things working pretty well by using a pullup to "drive" this pin. This will work in conjunction with the external 100K pullup to give a somewhat reasonable voltage. The eMMC will also not be able to pull much current through this pin, so it can't leak too badly. BRANCH=none BUG=chrome-os-partner:33319 TEST=Boot a kernel that doesn't touch the mux/pulls and see no leak: dut-control --port=${SERVO} vcc_flash_ma -t 5 Change-Id: Ibc25cd090d826c8215be24a0b5c11d97b5281700 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 26e7a9d7e067ed4dd859387ee63bf654ab9dc529 Original-Change-Id: Iadfc1477cd478773cc9d159e3fbc22b66b8f0f78 Original-Signed-off-by: Doug Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226039 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9545 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10Add google/veyron_jerry boardKatie Roberts-Hoffman
This is essentially a copy of veyron_pinky for now. BUG=chrome-os-partner:33269 TEST=build and boot Change-Id: I151c82f54ece4620953d0db5aedf027a3293926f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 267611f2354be4384de3f05d2459a4e421ee6b4f Original-Change-Id: I0d473361e0850ee3b11da5a809f8396826ccdad6 Original-Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225301 Reviewed-on: http://review.coreboot.org/9544 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10storm: copy WiFi calibration data in the CBMEMVadim Bendebury
Invoke the function which copies WiFi calibration data in a CBMEM table. BRANCH=storm BUG=chrome-os-partner:32611 TEST=verified that the WIFI entry is added to CBMEM when the calibration data is present in the VPD. Change-Id: Icab0a2343e88e1d44575eeb608fdf6588aff255b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 68b96f158633cb3a1f157b5a19da39fa7e78f975 Original-Change-Id: I5fa77da98e37b88da01fb7884e713535fc178006 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225272 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9543 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Make non-vboot2 memlayout more usefulFurquan Shaikh
Update non-vboot2 memlayout: 1) Add timestamp region 2) Increase ramstage size 3) Change name from memlayout_vboot.ld to memlayout.ld so that any non-vboot upstream board can also use this layout. BUG=None BRANCH=None TEST=Compiles and boots to kernel prompt on ryu with vboot selected instead of vboot2. Change-Id: Idced98f9df7cdbab5f62cd1e382c6046ade1d867 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20fffa282b20fb32ce2ff687f4479be630f90fcf Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I91accd54efc53ab563a2063b9c6e9390f5dd527f Original-Reviewed-on: https://chromium-review.googlesource.com/231547 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9536 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Add speaker amp config for AD4567 on P0/P1Tom Warren
A couple of regs need to be poked to allow audio output from this part on Ryu P0/P1. It will be replaced by two non-configurable amps on P3. BUG=none BRANCH=none TEST=Build/flashed on Ryu P1, dumped AD4567 (I2C6 dev 0x34) regs and confirmed settings. Change-Id: Ie602b056fb1488546ab233f8f81cfacb96624ebb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 75dabe378b561e939381e2ef5113a2b28bfcedf8 Original-Change-Id: I8999843646927dbd07a179ede973ba5f1eb97167 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Remove long delay when turning on AVDD_DSI_CSIJimmy Zhang
Based on TPS65913, the max LDO turn on time is 500us. Since it is requested the default delay of 500us when calling function pmic_write_reg(), it is safe to remove this 100ms delay. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I2cfda38728db223c26f9122b70d37e828921459a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 271b7e95f66f4b8611a0d408e59f428c315074f3 Original-Change-Id: I53aecc273484edfa502231b44f6bcd7f5d8f9331 Original-Reviewed-on: https://chromium-review.googlesource.com/231170 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9529 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: audio: Setup clocks for AHUB, I2S1, codec, etc.Tom Warren
The Ryu RT5677 audio codec uses EXTPERIPH1 clock (12MHz) for MCLK1, I2S1 for input. AHUB needs all of its child peripherals taken out of reset and enabled, too. This just sets up the audio clocks. More work still to be done in the codec driver, and some kind of stub needs to be created/hacked to set up the AD4567 speaker amp regs for mono output on P1. BUG=chrome-os-partner:32582 BRANCH=none TEST=Dumped clock regs and saw correct values Change-Id: Ifb6551f1e09b38f440f3bb7c759b5e6c0b9e4e44 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 48f989a0291044f5fb4340cc89546325d819d82f Original-Change-Id: I6c9e760ac39def92a6054d673f781facdbfd70a2 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229993 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9523 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: devicetree: Add framebuffer resolution settingsJimmy Zhang
When displaying a 800x600 bitmap on 2560x1800 panel, the image is shown very small. So, set the fb to 1280x800 (based on tegra dsi driver default mode setting), a 800x600 image can be shown relatively proportional to panel size. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I1e360aeaec97b9df5d86e46951ab1326610260d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c2a381322721a24b1b7f9ac366073b7e3c490c Original-Change-Id: I62cbe9de1d1002293df20f8b1d752905c6ef33aa Original-Reviewed-on: https://chromium-review.googlesource.com/229912 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9521 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Pass panel spec to lib_sysinfoJimmy Zhang
panel spec such as resoultion, bits per pixel are needed to pass to depthcharge/payload for displaying bitmap onto panel. Enable display code only if mainboard selects MAINBOARD_DO_NATIVE_VGA_INIT. Otherwise build breaks for boards that do not support display init yet. BRANCH=none BUG=chrome-os-partner:31936 TEST=Compiles for both rush and ryu. Display comes up for ryu in both normal and dev mode. Change-Id: I81b4d289699e7b0c2758ea1a009cbabaf8a2ce28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b9b42486f203d332f6068ccd6f4a1a982d327a6b Original-Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Id: ce2883b21d3fbfd54eac3a355fb34ec70e9f31ad Original-Change-Id: Ib4a3c32f1ebf5c6ed71c96a24893dcdee7488b16 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/9519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: devicetree: Add dsi panel mode settingsJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I2bd1b2c2b1bfe75702a12129ca57b3afa6542575 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6aac5ecb014ab213f465b9aa78f587994c6b3624 Original-Change-Id: I64f2df49a258b4dd024305a9757704a823265e99 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229911 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9516 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: dsi: Enable panel related vdd and clocksJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: Ia10bf7ae3bde389e883970f9a6ee931c32b8172b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f26902364b6a453adb850abfb0c4ce9686e99b5d Original-Change-Id: I68b92608098959cca14324bfc7e1e58389205989 Original-Reviewed-on: https://chromium-review.googlesource.com/226905 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9514 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Disable EC SW sync for proto boards before proto3Furquan Shaikh
BUG=chrome-os-partner:33583 BRANCH=None TEST=No EC SW sync messages seen in depthcharge boot flow. Change-Id: I62b7061a833ba607457a580fb2b217b9c2df0e74 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 552b1d19bacd6692ffb6257fc81220ba0ed89344 Original-Change-Id: I5c1df5a23977f461011a2937adda5770b4742378 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229081 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9513 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10urara: support building with CHROMEOS enabledVadim Bendebury
Chrome OS support needs to be enabled on urara. This patch adds a placeholder file to keep Chrome OS support code. BRANCH=none BUG=chrome-os-partner:31438 TEST=none Change-Id: I0731469934f04bd68914f09db5d64758c5d01545 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 169c62c9443c3b9fcab23b312b5cb18ba79437f4 Original-Change-Id: I8ec328d4f965ff80d17847f2f8ce62b402c42a46 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226179 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Log EC panics to eventlogShawn Nematbakhsh
Log the new EC panic host event. BUG=chrome-os-partner:36985 TEST=Manual on Samus. Trigger EC panic, verify that "Panic Reset in previous boot" is seen in /var/log/eventlog. BRANCH=Samus Change-Id: If59c522bd06f308a7ee6c5ff69ea427fcea361c9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: dae4eb50b3607c5141a77fce6709107283f5dc36 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: I89b358a81a962fd463101d84b6bcf3b0a12830c7 Original-Reviewed-on: https://chromium-review.googlesource.com/252391 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: http://review.coreboot.org/9508 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Enable vr_slow_rampShawn Nematbakhsh
Enable slow ramp rate to reduce idle noise / crackle. BUG=None TEST=Performance/noise/power tested by others. BRANCH=Samus Change-Id: I3b0083bdb19f96fc018356bd744fdff3baaf8962 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 041fca21b863d3fd94dd5bebf89fe48f5ac74285 Original-Change-Id: Id7e55f3710304369a79150129db18300ae38f93a Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248791 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9506 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Use codec internal 1.8V as DACREF sourceBen Zhang
This is needed for audio playback after we disconnect PP1800_CODEC from DACREF to avoid noise coupled on PP1800_CODEC, which makes recording noisy. For recording, DACREF comes from mic vref pump voltage. For playback, DACREF comes from internal 1.8V. BUG=chrome-os-partner:32953 BRANCH=samus TEST=Set MICBIAS to 2.970V on Samus, playback/recording is clean Change-Id: I65fb6dbfab54c7c4de6496fd4a0d666baead28ec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3e62a61f6cf6042f6d653a827698b55ac86e2d2b Original-Change-Id: I27430691e469dd7f4056d99438ce080062b58b9a Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241179 Reviewed-on: http://review.coreboot.org/9500 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Set MICBIAS1 to 2.970VBen Zhang
The default micbias1 voltage is 1.476V (1.8V * 0.82) which does not match what's specified on the schematic. This patch sets the voltage to 2.970V (3.3V * 0.90) according to the schematic. BUG=chrome-os-partner:32953 BRANCH=samus TEST=Set MICBIAS to 2.970V on Samus and verified with a scope Change-Id: I1ced834a5afe2de3fccf4bcff8ec9c8e5718f60a Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 176f9272801a3de5ed6fc05ade06042e2a2c0a5c Original-Change-Id: Icdbc1b5f65fe28591d54544372bdc2dacb50e9c1 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241178 Reviewed-on: http://review.coreboot.org/9499 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Adjust SATA Gen3 TX voltage amplitudeDuncan Laurie
Reduce the SATA Gen3 TX voltage amplitude by 210mV based on the provided test results to help with SATA validation. BUG=chrome-os-partner:34121 BRANCH=samus TEST=build and boot on samus and ensure SATA is still working, firmware image will be provided for full validation. Change-Id: I574d2f457b7b6831a339602a4165e959a0e2ee7d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9500ec152d8f9c90513811b1a92d1a8c155f514a Original-Change-Id: I233fa1a9a7f2877a97ef6834304680f82b958e82 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241800 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9496 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add clear_recovery_mode_switch functionDuncan Laurie
In order for recovery request to be cleared with software sync disabled we need to implement this function in the mainboard. BUG=chrome-os-partner:28234 BRANCH=samus TEST=boot in recovery with software sync disabled, ensure that the next boot will not boot in recovery again. Change-Id: Ie9c845396dfc6ab65296b2f18a86e23590c833d6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 430f85608cc3b59a68a86dba64ffe428bfc216a9 Original-Change-Id: Iac15b6a1b23cc971231339439bceb013f4a031bd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241052 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9492 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Set current backlight PWM valueDuncan Laurie
With recent changes in the 3.14 kernel and the switch to not using X the panel backlight is not geting turned on until chrome is started which means the splash screen is not visible. If we set the backlight PWM in coreboot then it will at least turn on for the early boot process. BUG=chrome-os-partner:31549 BRANCH=samus TEST=boot on samus in normal mode and see the boot splash logo Change-Id: I81e6b90617acb181b4de3365f8f56ec3b846b78b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f850fe3faff268a64f18e6bd176ec1126b921e3b Original-Change-Id: I622bef8af9bb6b753fe228b33ecdc4aae76af131 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240853 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9491 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add ACPI binding for rt5677 codec SPIBen Zhang
We'll need to find a real ACPI device ID for the rt5677 SPI driver. "RT5677AA" is temporary. BUG=chrome-os-partner:33495 BRANCH=samus TEST=load firmware via SPI; hotword detection works Change-Id: I6dc55c4641c27a38570debe841a6afeb048eb868 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f0d7013b62c78deb82db1a431f079c79eded5270 Original-Change-Id: Ifb4a1b12776669e21c0b7c4679246717d72981ad Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235902 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9486 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add RT5677 ACPI/DT bindings with _DSDDuncan Laurie
To support the ACPI device specific properties that conform to the existing devicetree bindings for this codec (in upstream kernels) add a _DSD object to the existing codec device. BUG=chrome-os-partner:29649 BRANCH=samus TEST=build and boot on samus Change-Id: Ice808ba7bf2f0378ac5a38afd27dbf6c8cac0da5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b3fc2d7e5a5878b1fff7627f803b883b38fea28d Original-Change-Id: I344636171a3086a72087314503bfc99de5945b1f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238857 Original-Reviewed-by: Ben Zhang <benzh@chromium.org> Reviewed-on: http://review.coreboot.org/9483 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Move board version to a separate fileDuncan Laurie
This combines the board version reading and parsing to a separate file that is compiled in both romstage (for early serial output) and ramstage (for smbios tables). It also adds a new board version that is wrapped back to number zero as we are running out of available IDs. BUG=chrome-os-partner:32895 BRANCH=samus TEST=build and boot on samus EVT1 and EVT2 and check for proper board versions reported in console and smbios. Change-Id: I8c8f17708ced7167277a98529ff4597589f53095 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3ab8bba1021a8dd41dd2210ba73efd2231eb596c Original-Change-Id: I2aa03e7486a9581f94dc4e12f6f29eb0c5b3bdbb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229041 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10vboot: add physical recovery switch supportDaisuke Nojiri
PHYSICAL_REC_SWITCH is set n by default and y for panther and stumpy. BUG=none BRANCH=ToT TEST=Built nyan_blaze using vboot1/2. Built falco, lumpy, nyan, blaze, parrot, rambi, samus, storm, pinky with default configuration. panther and stumpy are not tested because they currently don't build on ToT. Original-Change-Id: Ic45f78708aaa7e485d2ab459fd1948524edb412f Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227940 Original-Reviewed-on: https://chromium-review.googlesource.com/229602 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit edb2ba347b48887ffe450586af0351e384faad59) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I277f665cd4f3e1c21745cdc5c7a2cfe148661abe Reviewed-on: http://review.coreboot.org/9444 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot: move vboot files to designated directoryDaisuke Nojiri
This moves vboot1 and vboot2 files to their designated directory. Common code stays in vendorcode/google/chromeos. BUG=none BRANCH=none TEST=built cosmos, veyron_pinky, rush_ryu, nyan_blaze, samus, parrot, lumpy, daisy_spring, and storm. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia9fb41ba30930b79b222269acfade7ef44b23626 Original-Reviewed-on: https://chromium-review.googlesource.com/222874 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit cbfef9ad40776d890e2149b9db788fe0b387d210) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia73696accfd93cc14ca83516fa77f87331faef51 Reviewed-on: http://review.coreboot.org/9433 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10mainboard/biostar: Add support for Biostar AM1ML ver7.xSergej Ivanov
Adds AM1ML board. This board has AM1 Socket and supports all new AM1 APUs from AMD. Based on asrock/imb-a180 board. Successfully tested with SeaBIOS and Linux 3.8.x and Windows XP. Successfully tested audio, video, network, PS/2 keyboard and mouse, PCIe x16, COM port, SATA and USB. LPT port is not tested yet and it’s unknown if it’s work. Change-Id: I9ebb9acc590d38e47579adc263f45ae3f607684e Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: http://review.coreboot.org/9293 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-10google/cosmos: don't enable CHROMEOS by defaultPatrick Georgi
This isn't done in upstream. Change-Id: Ief1fea0f231d609372f065f6f6aee7bceaf31efc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9458 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush: Add I2C1 init and audio clock enable/resetsTom Warren
This should allow the max98090 codec to play beeps via AHUB/I2S1 thru the depthcharge sound driver. BUG=none BRANCH=none TEST=Saw max98090 codec init signon and register dump. No sound yet. Change-Id: I1ee0b61f5cbfe587ebd16b7dd9dce08d9d62c2c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4ee2ce3704711a9e00531b7599a1bcf194203ec Original-Change-Id: I0bc8401e76b2c80a01083ac933a39f6cd4d1b78a Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229496 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/9429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Add support for event logFurquan Shaikh
BUG=chrome-os-partner:33764 BRANCH=None TEST=Event logs verified on ryu across multiple boots. Change-Id: Iff4a60b3904ef0fcdd2513df579db8f5877808de Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbe6290de7eaed0d66a26cc2389181a8d38a59d6 Original-Change-Id: I50d052bb15ec6616b0bf82bf1f1acf9080f4c54b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229415 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9426 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10ryu: Enhance pmic access functionsJimmy Zhang
1. Add page address, an i2c address, into register address table 2. Add pmic read function 3. Add more registers and setting values. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: Ieef0737205b20add3ff8990f62dd8585a4e8c557 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6dcf42c299e25023991be331b724acd0fd9f32c2 Original-Change-Id: I227b3e9390e6fc020707d4730c19945760df6ca2 Original-Reviewed-on: https://chromium-review.googlesource.com/226902 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9420 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10ryu: audio: Enable RT5677 audio codecTom Warren
Take codec out of reset (GPIO_PH1 aka CODEC_RST_L) and enable LDO2 (GPIO_PR2/KB_ROW2 aka AUDIO_ENABLE). Muxes are setup and the two GPIOs are set to output and driven high. BUG=chrome-os-partner:32582 BRANCH=none TEST=RealTek ALC5677 codec shows up in I2C6 scan at address 0x2D, can read/write registers. Change-Id: I236850452d401fd89b4f59eb03f132c0be32fb20 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fe3b0c1a3f5d6264b83d7a7e2363dc3f3235cbf Original-Change-Id: Iedce7bb9f8e61d3b8cd693fc5e567323d89f8046 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228920 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10ryu: Select pwr btn polarity based on board idFurquan Shaikh
Proto 0,1,2 boards had pwr btn active high. Proto 3 onwards boards will have pwr btn active low. Thus, select power btn polarity based on board id. BUG=chrome-os-partner:33545 BRANCH=None TEST=Compiles successfully and boots to kernel prompt on ryu proto 1. Change-Id: I9b06b10358b91d40cfdb418ef8cf4da1ae833121 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7100a42b53a09ed4cb298f88d6f804f46fecacb5 Original-Change-Id: Icdf51b9324385de00f5787e81018518c5397215f Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229011 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9418 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10gpio: decouple tristate gpio support from board IDDavid Hendricks
This deprecates TERTIARY_BOARD_ID. Instead, a board will set BOARD_ID_SUPPORT (the ones affected already do) which will set GENERIC_GPIO_SUPPORT and compile the generic GPIO library. The user is expected to handle the details of how the ID is encoded. BUG=none BRANCH=none TEST=Compiled for peppy, nyan*, storm, and pinky Change-Id: Iaf1cac6e90b6c931100e9d1b6735684fac86b8a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93db63f419f596160ce2459eb70b3218cc83c09e Original-Change-Id: I687877e5bb89679d0133bed24e2480216c384a1c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228322 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9413 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10gpio: cosmetic changes to tristate_gpios.cDavid Hendricks
This patch makes a few cosmetic changes: - Rename tristate_gpios.c to gpio.c since it will soon be used for binary GPIOs as well. - Rename gpio_get_tristates() to gpio_base3_value() - The binary version will be called gpio_base2_value(). - Updates call sites. - Change the variable name "id" to something more generic. BUG=none BRANCH=none TEST=compiled for veyron_pinky and storm Change-Id: Iab7e32f4e9d70853f782695cfe6842accff1df64 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c47d0f33ea1a6e9515211b834009cf47a171953f Original-Change-Id: I36d88c67cb118efd1730278691dc3e4ecb6055ee Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228324 Reviewed-on: http://review.coreboot.org/9411 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10rk3288: slowly raise to max cpu voltage to prevent overshoothuang lin
slowly raise to max cpu voltage to prevent overshoot, and in our experience,when cpu run in 1.8GHz,the vdd_cpu must up to 1.4V BUG=chrome-os-partner:32716, chrome-os-partner:31896 TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1400mv and measure the overshoot is 1440mv Change-Id: I759840bd8cf57a5589bf1862d04803f80f804164 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 567f616ff091883ed3275b407859c9399db981b2 Original-Change-Id: I9bb739b49ae4b4f7a60133fa38b0fe51b95c0d78 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226753 Original-Reviewed-by: Doug Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9408 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10ryu: update board id definitionsAaron Durbin
There are changes in upcoming board revs that need to take different action depending on board revision. Update the enumeration to reflect upcoming reality. BUG=chrome-os-partner:33578 BRANCH=None TEST=Built and booted. Change-Id: Ib51393e04d3255bbd44e5d77a2a7903109beebf4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de8d629678c0ae17af9f7145e04d95f43c927ee0 Original-Change-Id: I64cdeab806e7a665051f1d47bbf044413f7a1196 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227681 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9407 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-10ryu: remove board id normalizationAaron Durbin
The gpio_get_tristates() function prints out the values observed while processing the GPIOs. Additionally, the values for the normalization were completely consecutive. Therefore, this indirection can be removed. BUG=chrome-os-partner:33578 BRANCH=None TEST=Built and booted. Change-Id: I088a2f1c7601c014a7f8a9eb228efa9bb80f1e01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 02e52554b9cbf85034feb9aedc50f09b70893e32 Original-Change-Id: I17d85891087e3128790329a5f05cbdab4cbc950e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227680 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9406 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/storm: Minor board ID changesDan Ehrenberg
- Add the Whirlwind board ID to the enum - Replace comparisons of the board ID with 0 to the proto0 constant TEST=Booted Storm with this coreboot version BUG=none BRANCH=none Change-Id: I53be0b06c3444936a8bd67653e03b93bcb87e328 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e055ef27ef1e07be09d80b2298384889214bf0d Original-Change-Id: I75c7c98732c3d4569611de54d7aa149dd3b0fb7d Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225460 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9404 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10storm: Initialize clock, pinmux for NAND if present on boardDan Ehrenberg
This patch runs basic NAND initialization code on Proto 0.2 boards which have been reworked for NAND. It makes sense to do this in coreboot for two reasons: - In general, it is reasonable for coreboot to initialize clocks and such in preparation for depthcharge's use. Waiting times can be pooled, and the initialization itself here is very fast. - There is a kernel bug which requires that the clock is already initialized before the kernel loads NAND support. coreboot is a more sensible place to put a workaround than depthcharge because depthcharge initializes things lazily, but when booting from USB, depthcharge won't need to look at NAND. This change involves bringing in an additional header file, ebi2.h, from U-Boot. TEST=Booted a kernel from USB and verified that NAND came up without any depthcharge hacks, whereas previously a USB-booted kernel would be unable to access NAND even with the same drivers compiled in due to an initialization failure. BUG=chromium:403432 BRANCH=none Change-Id: I04e99cb39d16848a6ed75fe0229b8f79bdf2e035 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9be29da5ccad9982f146ae00344f30598ef2371c Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Change-Id: I1760ecb4e47438311d80e34326e45578c608481c Original-Reviewed-on: https://chromium-review.googlesource.com/225277 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9402 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10gpio: Remove non-ternary tristate mode, make ternaries easierJulius Werner
The function to read board IDs from tristate GPIOs currently supports two output modes: a normal base-3 integer, or a custom format where every two bits represent one tristate pin. Each board decides which representation to use on its own, which is inconsistent and provides another possible gotcha to trip over when reading unfamiliar code. The two-bits-per-pin format creates the additional problem that a complete list of IDs (such as some boards use to build board-ID tables) necessarily has "holes" in them (since 0b11 does not correspond to a possible pin state), which makes them extremely tricky to write, read and expand. It's also very unintuitive in my opinion, although it was intended to make it easier to read individual pin states from a hex representation. This patch switches all boards over to base-3 and removes the other format to improve consistency. The tristate reading function will just print the pin states as they are read to make it easier to debug them, and we add a new BASE3() macro that can generate ternary numbers from pin states. Also change the order of all static initializers of board ID pin lists to write the most significant bit first, hoping that this can help clear up confusion about the endianness of the pins. CQ-DEPEND=CL:219902 BUG=None TEST=Booted on a Nyan_Blaze (with board ID 1, unfortunately the only one I have). Compiled on Daisy, Peach_Pit, Nyan, Nyan_Big, Nyan_Blaze, Rush, Rush_Ryu, Storm, Veryon_Pinky and Falco for good measure. Change-Id: I3ce5a0829f260db7d7df77e6788c2c6d13901b8f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2fa9545ac431c9af111ee4444d593ee4cf49554d Original-Change-Id: I6133cdaf01ed6590ae07e88d9e85a33dc013211a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219901 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9401 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10gpio: Extend common GPIO header, simplify function namesJulius Werner
We've had gpiolib.h which defines a few common GPIO access functions for a while, but it wasn't really complete. This patch adds the missing gpio_output() function, and also renames the unwieldy gpio_get_in_value() and gpio_set_out_value() to the much easier to handle gpio_get() and gpio_set(). The header is renamed to the simpler gpio.h while we're at it (there was never really anything "lib" about it, and it was presumably just chosen due to the IPQ806x include/ conflict problem that is now resolved). It also moves the definition of gpio_t into SoC-specific code, so that different implementations are free to encode their platform-specific GPIO parameters in those 4 bytes in the most convenient way (such as the rk3288 with a bitfield struct). Every SoC intending to use this common API should supply a <soc/gpio.h> that typedefs gpio_t to a type at most 4 bytes in length. Files accessing the API only need to include <gpio.h> which may pull in additional things (like a gpio_t creation macro) from <soc/gpio.h> on its own. For now the API is still only used on non-x86 SoCs. Whether it makes sense to expand it to x86 as well should be separately evaluated at a later point (by someone who understands those systems better). Also, Exynos retains its old, incompatible GPIO API even though it would be a prime candidate, because it's currently just not worth the effort. BUG=None TEST=Compiled on Daisy, Peach_Pit, Nyan_Blaze, Rush_Ryu, Storm and Veyron_Pinky. Change-Id: Ieee77373c2bd13d07ece26fa7f8b08be324842fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9e04902ada56b929e3829f2c3b4aeb618682096e Original-Change-Id: I6c1e7d1e154d9b02288aabedb397e21e1aadfa15 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220975 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10storm: retrieve MAC address from VPDVadim Bendebury
Retrieving MAC address from VPD should be the board responsibility, add a call to the recently introduced function. BRANCH=storm BUG=chromium:417117 TEST=verified that MAC addresses still show up in the device tree on storm Change-Id: Ib8ddc88ccd859e0b36e65aaaeb5c9473077c8c02 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 285cb256e619ef41c7f11680b3fa5310b1d93cf1 Original-Change-Id: I3913b10a425d8e8621b832567871ed4861756381 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223797 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9399 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-09bg4cd: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns bg4cd to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Cosmos. Change-Id: I32a4407f7deb2b1752b6220a140352724f320637 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b6bb6990417863010258632374c3f5ac19350c9 Original-Change-Id: Ia5299659ad186f2e7d698adfa7562396e747473f Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224506 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9358 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-09bg4cd, cosmos: use SPI_WRAPPER configuration modeVadim Bendebury
The SOC code should include the SPI controller driver when configured. Enable SPI support for cosmos. BRANCH=none BUG=chrome-os-partner:32631 TEST=cosmos builds Change-Id: I8212f191b7d80f0bee86f746813edaf8e5ee6db1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd4853be5157247bb73fc22b9d4f8300228fe6ce Original-Change-Id: If7e12e2fb04e63c36d9696d13e08397b91a77a8c Original-Commit-Id: 7b1d095e5df6a864d3564bbf7a20cc211f75629a Original-Change-Id: If9dd80cb96120d34a0865f7882cd62e45fed749d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223750 Original-Reviewed-on: https://chromium-review.googlesource.com/223752 Reviewed-on: http://review.coreboot.org/9356 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-09pistachio: add SOC descriptorVadim Bendebury
With this descriptor added ramstage properly allocates memory resources and creates entries in coreboot table. This also allows to proceed to booting depthcharge, as it now can be loaded into the existing memory. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the set of patches applied the firmware properly finds depthcharge in CBFS, uncompresses it and attempts to start: ... Booting payload fallback/payload from cbfs Loading segment from rom address 0x9b000058 code (compression=1) New segment dstaddr 0x80124020 memsize 0x2099a0 srcaddr 0x9b000090 filesize 0xbbe Loading segment from rom address 0x9b000074 Entry Point 0x80124038 Loading Segment: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe lb: [0x0000000080000000, 0x0000000080013858) Post relocation: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe using LZMA [ 0x80124020, 8012596c, 0x8032d9c0) <- 9b000090 Clearing Segment: addr: 0x000000008012596c memsz: 0x0000000000208054 dest 80124020, end 8032d9c0, bouncebuffer 8ffd4f50 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 129 run 34579421 exit 129 Jumping to boot code at 80124038 ERROR: dropped a timestamp entry CPU0: stack: 9a00c800 - 9a00d800, lowest used address 9a00d498, stack used: 872 bytes entry = 80124038 Change-Id: I15809e146407d66b04f2a97c47c961fdccb8e175 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a1577c5532a064426a3ea88b6f7f30ccdae24eaf Original-Change-Id: Ifed5550f2c18430e9ae06ad1ecacaa13191b5995 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232571 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9192 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-09pistachio: allow more room for bootblockVadim Bendebury
32K is a more appropriate room for Pistachio bootblock. BRANCH=none BUG=chrome-os-partner:31438 TEST=there is no bootblock overflow even when compiled with -O0. Change-Id: I454746ce0b9daabc93ccbf3316655fac836af8ff Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 56adf22ba12f5a7c69d11c0c720996de32ca9149 Original-Change-Id: I74b6674aea95b1138e2168527239e2cfb4a7ad42 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232291 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-09cosmos: add template for soc and board filesDaisuke Nojiri
This adds board and soc files as a template for cosmos. BUG=chrome-os-partner:32772 BRANCH=none TEST=Built coreboot for cosmos and veyron_pinky. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I6e17058afaa629c6aa70c2d195230dba782af526 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd9dbcf1023a79921c8501bbe09969d65ca9e742 Original-Change-Id: I676bdf460f5dd996dcce1fc422a69882798bc112 Original-Reviewed-on: https://chromium-review.googlesource.com/222050 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9351 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08rush: Add vboot2 supportFurquan Shaikh
CQ-DEPEND=CL:221601, CL:*178568 BUG=chrome-os-partner:32684 BRANCH=None TEST=Compiles successfully Original-Change-Id: I50d0475dbe1390b640a726c259364f36abcbebe0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221579 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 14e348721399f13a52258faa16769b0ebb5b511f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I2683cb29c7a93f3f4aba0d7b9a56a1ca209518a0 Reviewed-on: http://review.coreboot.org/9432 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-08ryu: Add vboot2 supportFurquan Shaikh
CQ-DEPEND=CL:221598, CL:*178568 BUG=chrome-os-partner:32684 BRANCH=None TEST=Compiles and boots to kernel prompt Original-Change-Id: If7c725333b45a92f951ab674c3e4bd6a51c180c2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221577 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 9f5a6ae8cb6e7136ab0f0158a864dfc8ccf5c24f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If83dece2b4f2aa7d1457c723131efaa9b1169009 Reviewed-on: http://review.coreboot.org/9431 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-08t132: Add vboot2 supportFurquan Shaikh
BUG=chrome-os-partner:32684 BRANCH=None TEST=Compiles successfully and boots to kernel prompt using vboot2 Original-Change-Id: Ibf7666d273e4d1af719c60d3f02bddcb4461f4bd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221576 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 8335915940ae9ba9e51e360df6963a27b05d6324) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7d3d5cda4c4be945931d9133ab18680dac1dcefe Reviewed-on: http://review.coreboot.org/9430 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-08tegra124: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns tegra124 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Nyan, Nyan_Big and Nyan_Blaze. Change-Id: Ia82ab86b2af903690cc6c9d310f7bdda3425ea7c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d23774e071ec22781991ff20fbf63802f620c88 Original-Change-Id: Ia126cff8590117788d1872e50608c257d2659c1f Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224504 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9326 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08ipq806x: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns ipq806x to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Storm. Change-Id: Icb81a77e6f458625f5379a980e8760388dd3a1f9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bf23774c9ffa5d08c211f3658d39adcfa47b339 Original-Change-Id: I283cc7e6094be977d67ed4146f376cebcea6774a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224502 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9368 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Patrick Georgi <pgeorgi@google.com>
2015-04-08rk3288: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch is the start of a series to change all non-x86 SoC-specific headers to be included as <soc/header.h> instead of the old <soc/vendor/chip/header.h> or "header.h". It will add an include/soc/ directory under every src/soc/vendor/chip/ and append the .../include/ part of that to the global include path. This matches the usage of <arch/header.h> for architecture-specific headers and had already been done for some headers on Tegra. It has the advantage that a source file which does not know the specific SoC used (e.g. Tegra files common for multiple chips, or a global include file) can still include SoC-specific headers and access macros/types defined there. It also makes the includes for mainboard files more readable, and reduces the chance to pull in a wrong header when copying mainboard sources to use a different-related SoC (e.g. using a Tegra124 mainboard as template for a Tegra132 one). For easier maintainability, every SoC family is modified individually. This patch starts out by changing Rk3288. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Whole series: compared binary images for Daisy, Nyan_Blaze, Rush_Ryu, Storm, Urara and Veyron_Pinky. Confirmed that they are byte-for-byte identical except for timestamps, hashes, and __LINE__ macro replacements. Compile-tested individual patches. Change-Id: I4d74a0c56be278e591a9cf43f93e9900e41f4319 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4ad8b6d2e0280428aa9742f0f7b723c00857334a Original-Change-Id: I415b8dbe735e572d4ae2cb1df62d66bcce386fff Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222025 Reviewed-on: http://review.coreboot.org/9349 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08rk3288: support tsadchuang lin
check the cpu and gpu temperature in romstage, if over 120 degrees celsius,shut down the device. BUG=None Test=Boot on veyron_pinky rev2, write value 3421(125 celsius) to grf_tsadc_testbitl register, the device will be shut down Change-Id: I275d643ce8560444a9b42ee566d5fd63ebcda35e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e0c597489dc0637ffa66ee9db0c4f60757f8889f Original-Change-Id: If406d6a4f6201150f52ea7fc64cd50b45778d7aa Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223259 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9348 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08rk3288: configure l2ctlr in romstagehuang lin
Data RAM write latency: 2 cycles Data RAM read latency: 2 cycles Data RAM setup latency: 1 cycle Tag RAM write latency: 1 cycle Tag RAM read latency: 1 cycle Tag RAM setup latency: 1 cycle BUG=None TEST=Boot Veyron Pinky Change-Id: I1d710f65114be6a976aa3fe23b076e89c14ac8b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 421c2e5ba44f1693f8b3c869289fc93ab9ef5965 Original-Change-Id: Ic9c909b7913d434bd40016c6a820ddff7e991634 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223713 Original-Reviewed-by: Doug Anderson <dianders@chromium.org> Original-Commit-Queue: Doug Anderson <dianders@chromium.org> Reviewed-on: http://review.coreboot.org/9347 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08tegra132: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns tegra132 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Rush_Ryu. Change-Id: I5cdf4008a65db84f15c937ef53aab5e4d3ef24c4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5c5c63d7b6399d3eb8a211b15d47829fe93a591 Original-Change-Id: Ifafd4d42d4fb04a1c37e8a5f23877c2b550cf44c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224505 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9369 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08rk3288: Add early SRAM mappingJulius Werner
Solving the DACR bug will mean that XN bits suddenly become enforced on non-LPAE systems, and we will no longer be able to execute out of a region mapped DCACHE_OFF. When we enable the MMU in romstage we are still executing out of SRAM, so we would instantly kill ourselves. Solve this issue by enabling the MMU earlier (in the bootblock) and mapping the SRAM regions as DCACHE_WRITETHROUGH. They should really be DCACHE_WRITEBACK, but it looks like there might be hardware limitations in the Cortex-A12 cache architecture that prevent us from doing so. Write-through mappings are equivalent to normal non-cacheable on the A12 anyway, and by using this attribute we don't need to introduce a new DCACHE_OFF_BUT_WITHOUT_XN_BIT type in our API. (Also, using normal non-cacheable might still have a slight speed advantage over strongly ordered since it should fetch whole cache lines at once if the processor finds enough accesses it can combine.) CQ-DEPEND=CL:223783 BUG=chrome-os-partner:32118 TEST=None (depends on follow-up CL) Change-Id: I1e5127421f82177ca11af892b1539538b379625e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7b079f4b6a69449f3c7cc18ef0e1704f2006847 Original-Change-Id: I53e827d95acc2db909f1251de78d65e295eceaa7 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223782 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9342 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07pistachio: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns pistachio to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Urara. Change-Id: I0609b307695ba6a922384ac34dd604bffcb20692 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a577918babf26adf10baa0f56a7065f5659d285 Original-Change-Id: I3ed405a3efdeec28965538d19a22f2b5b8204f01 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224503 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07exynos5420: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns exynos5420 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Peach_Pit. Change-Id: If97b40101d3541a81bca302a9bd64b84a04ff24a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 570ca9ed6337d622781f37184b2cd7209de0083f Original-Change-Id: I338559564e57bdc5202d34c7173ce0d075ad2afc Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224501 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9324 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07exynos5250: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns exynos5250 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Daisy. Change-Id: I39805c0346e117a0f9b2667763ecaa428f0f55a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db6762f0c8425371d9860f908a5cefdeee8d1abc Original-Change-Id: Ic358061ddcbbe7d83a95ca11247b8b505b20491d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224500 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9323 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07broadwell: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns broadwell to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Auron and Samus. Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224507 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-07baytrail: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns baytrail to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Rambi. Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083 Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222026 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-06global: Refactor get_option usageVarad Gautam
Restructure get_option() calls to avoid unnecessary return value checks by pre-assigning defaults to the options being retrieved. Change-Id: I9159afe149a8eeed0785d1efd6eee8420b88b8f4 Signed-off-by: Varad Gautam <varadgautam@gmail.com> Reviewed-on: http://review.coreboot.org/8631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-05mainboard/lenovo/x201: correct sata_port_mapAlexander Couzens
x201 has 2 sata ports. 1 port for hard drive and 1 port for the dock. Tested on x201 with hdd in port 1 + cdrom in port 2. Change-Id: I1ee8c547392257d4f2e00a5d48e21447a84f79c0 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8657 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-04-05intel/nehalem: rename copypasted smi finalizer functionAlexander Couzens
The nehalem smi finalize handler was just copied from sandybridge, without even changing the function name. TEST=Built and tested on x201t with additional patch to use finalizers Change-Id: Ifb44eeaaa6e03556deeb5d12ed1147e02d6d6eb9 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8292 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-04-04rk3288: set cpu frequency up to 1.8GHzhuang lin
before the rkclk_init(), we must set rk808 buck1 voltage up to 1300mv BUG=chrome-os-partner:32716, chrome-os-partner:31896 TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1300mv and check the cpu frequency up to 1.8GHz Original-Change-Id: I6a8c6e35bd7cc6017f2def72876a9170977f206e Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222957 Original-Reviewed-by: Doug Anderson <dianders@chromium.org> (cherry picked from commit 2e7e7c265691250d4a1b3ff94fe70b0a05f23e16) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iff89d959456dd4d36f4293435caf7b4f7bdaf6fd Reviewed-on: http://review.coreboot.org/9260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04veyron_pinky/rk3288: Use KHz, MHz and GHz constantsJulius Werner
Use the previously added frequency constants in patch titled 'stddef: Add KHz, MHz and GHz constants'. BUG=None TEST=Compiled Veyron_Pinky. Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I37a610d57f1a3d44796bf80de5104c2b5b3f3dac Reviewed-on: http://review.coreboot.org/9254 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04samus: Disable USB Port 5Duncan Laurie
This device is not used in current builds and should be disabled to help EMI. BUG=chrome-os-partner:34117 BRANCH=samus TEST=build and boot on samus Change-Id: I5c34f1f6c84d9de04a42e16fa32f57d4f9d1e478 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 00a9b2ad8512f84beff7358dad0ec028478c57d2 Original-Change-Id: I62541e343dcaa3cd31c81b73d8c27a5efcf3ad60 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234403 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9282 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add new memory typeDuncan Laurie
Add a new memory type for the next build, and rename the existing ones to drop the Gb suffix. BUG=chrome-os-partner:33924 BRANCH=samus TEST=build and boot on samus Change-Id: Iedcd3823aa80c93fc2aadbc486d74b40c9bd4279 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bcc9827965182a7d0d5325189d55eb76f5c2f0e7 Original-Change-Id: I47d2b7e58f51f3ee00cd7797da3f8353f509f8b5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230769 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9278 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Set codec PDM clock output to 3MHzBen Zhang
Currently the rt5677 codec outputs 6MHz PDM clock which is out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS pin is pulled down to PGND with a 47k resistor, so the expected PDM clock is 64*FS (~3MHz) according to its datasheet. The corresponding kernel patch that adds the PDM clock config option is https://chromium-review.googlesource.com/#/c/230303/ BUG=chrome-os-partner:33303 BRANCH=samus TEST=flash coreboot with this patch and see PDM CLK went from 6MHz to 3MHz on samus with a scope. Change-Id: Icf2c61930175bede1ee8ebc2b0fb17c2938b806c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b9ba4597515b2fbcc72fa22e296357c454175648 Original-Change-Id: I09acdf47bab4f641981491a84197de234918435e Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230344 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9277 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Change touchscreen bootloader mode i2c addressDuncan Laurie
This value apparently changed to 0x27 in the hardware but was never adjusted in firmware. BUG=chrome-os-partner:33790 BRANCH=samus TEST=build and boot on samus Change-Id: Ib610fc6522715e3c841c337d420ec63563bec798 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e01d3b47bf49861e9d53fc8db41890fe4c91ff9b Original-Change-Id: I10ca7b77068491e143f8bf2463b481eada910618 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable GSPI0 interfaceDuncan Laurie
This will be connected to the coded for firmware upload. BUG=chrome-os-partner:33495 BRANCH=samus TEST=build and boot on samus, check that GSPI driver is loaded Change-Id: Ife41394e31af9dab03495b34609cb119525f9b19 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bbf26154da675845251c54f71d1df9df8d2a4fd5 Original-Change-Id: I25c91145aef8ca2aef229ffb27e8a45df659982e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228835 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9273 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable GPIO9 as touchpad wakeDuncan Laurie
With EVT2 systems GPIO9 is now used for touchpad wake. BUG=chrome-os-partner:32232 BRANCH=samus TEST=suspend/resume by touchpad on samus, with kernel workaround to disable setting of T19 in atmel driver mxt_suspend() 51 | 2014-11-03 12:41:34 | ACPI Enter | S3 52 | 2014-11-03 12:41:37 | ACPI Wake | S3 53 | 2014-11-03 12:41:37 | Wake Source | GPIO | 9 Change-Id: I67c1a6591dc287fc780889950e78c731a5a65d44 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8512a6e5266edaf77d300f47bd26c501f00361d7 Original-Change-Id: I8120747986e694b64d464826f87c9afa68af157a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227157 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Update thermal max for broadwellDuncan Laurie
Broadwell Tj_max is 105C, update accordingly. BUG=chrome-os-partner:28234 BRANCH=samus TEST=build and boot on samus Change-Id: I001e17287ebbcbfdd909428e149a95878734dab9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fb1de7a9e1d84f592b785a1b495e4aaf434f23a2 Original-Change-Id: If6a3fd682f4ee9b8010982870a61b76e33010fd4 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226952 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9270 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Assign GPIO2 to HP_AMP_SHDN_LBen Zhang
BUG=chrome-os-partner:29649 BRANCH=samus TEST=Audio playback to headphone works Change-Id: I35efa3b97abbba50cbee4c25acfaeb155fc1238f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e2c0ede19c6b700c8d0bf01ff9d3a54984c5d784 Original-Change-Id: Ib51aace52026688dc8972047e5d934c80138ff80 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221294 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9269 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Make codec interrupt active highBen Zhang
The codec interrupt needs to be active high because multiple interrupt sources share this line: 1) Headphone plug detect 2) Mic present 3) Hotword detect These interrupt sources are OR-ed together. BUG=chrome-os-partner:29649 BRANCH=samus TEST=Jack detection works on samus Change-Id: If35fe8493ab30d878d9fac2251acee62c776b0eb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 348608fe61f7848db2bfd22502a0c259d24f8980 Original-Change-Id: Ief0a291d9455f2d03789198153781ff8133aa1ce Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220588 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add codec platform data for jack detectBen Zhang
GPIO IRQ support has been added in upstream rt5677 driver, with new jack detect platform config options. BUG=chrome-os-partner:29649 BRANCH=samus TEST=headphone and mic detect works on Samus Change-Id: I68a675ccd1fec3e5329d57aadad3229053092026 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4b90fa2f557f603661e25c9e1b4712eea15c8502 Original-Change-Id: I379087b8acdb13e65776a18c9ee3a58d4cb4e73c Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224513 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9266 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Change GPIO controller label to INT3437:00Duncan Laurie
This matches the label exported by the GPIO controller in the kernel and allows more speicific matches if there are other devices that also export GPIOs. BUG=chrome-os-partner:33098 BRANCH=samus TEST=crossystem wpsw_cur returns 1 Change-Id: I96f8d0f7f9fd584be4a6f14d13e04db0a88951a8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 736679136a0a72874304eaeae1ac58633cd2ce14 Original-Change-Id: I655549d0f0eca341581bfbf845162d8b9f5e993d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224136 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable update screen for software syncDuncan Laurie
Since the PD software sync is slow enable support for displaying a screen telling the user that something is happening. BUG=chrome-os-partner:32379 BRANCH=samus TEST=manual testing: 1) in normal mode, with EC/PD in RW, ensure that they are rebooted to RO and the VGA Option ROM is loaded and the wait screen is displayed, and then the system is rebooted at the end and the VGA Option ROM is not loaded. 2) same as #1 with EC/PD in RO already, same result 3) same as #1 with system in developer mode, same result except there is no reboot at the end of software sync 4) same as #1 with system in developer mode and EC/PD in RO, ensure that there is no extra reboot at the beginning or end of software sync. Change-Id: Ib6c4cc03952768ece76832efc84f665c52191ffb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6971d74ff50ced0ef94d5fec26c0e6a071d207b2 Original-Change-Id: I125744f58c6b84df1af3943d9be98fe55c7117d5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223850 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9264 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add smbios_mainboard_version to define board versionDuncan Laurie
Instead of having this in mosys just have coreboot report the board version in SMBIOS tables. BUG=chrome-os-partner:32359 BRANCH=samus TEST=build and boot on samus, check /sys/class/dmi/id/product_version Change-Id: I09d235752f4c870f99fb8c6a280e2bf9aba7e137 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 08413589ba84b07ff64c9116ca5fcc991cee3b89 Original-Change-Id: Ib851d2e79ed721dcbc1c2f2eda6da50cac064cf3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223096 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9263 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add codec platform info in ACPIDuncan Laurie
This is the specific codec setup platform data for samus. BUG=chrome-os-partner:29649 BRANCH=samus TEST=emerge-samus coreboot Change-Id: I00d4a2f73810f5f7bad49922321fb1c340289770 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 813c45bc3fdd7a2fb84df0e24bd470003bf4eafa Original-Change-Id: I5e2a8fad58bb8a3d02ccece0b1f6fe52f56c94ea Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221539 Original-Reviewed-by: Ben Zhang <benzh@chromium.org> Reviewed-on: http://review.coreboot.org/9261 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Drop (empty) google/snow mainboard directoryStefan Reinauer
Snow was renamed to daisy a long time ago. The only reason, it seems, the directory was still there, was a stray board_info.txt file that probably went in shortly after the rename. Change-Id: Iba08665e8486fcfeb214fcd05206a5f5683aea82 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9302 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04rk3288: Pass SPI bus speed in as parameter to init functionDavid Hendricks
This re-factors rockchip_spi to remove speed_hz which will instead be passed in via rockchip_spi_init(), thus making it easier to support other boards which may have different slave devices attached. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10 Original-Reviewed-on: https://chromium-review.googlesource.com/220411 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c Reviewed-on: http://review.coreboot.org/9245 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-02pinky: Move some init to mainboard bootblockDavid Hendricks
This patch moves init for I2C, SPI, ChromeOS GPIOs to the board-specific bootblock init function on Pinky, the idea being to isolate SoC code so that it's more readily adaptable for different boards. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I75516bbd332915c1f61249844e18415b4e23c520 Original-Reviewed-on: https://chromium-review.googlesource.com/220410 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 0a7dec2fe70679c3457b0bfc7138b4a90b6217c8) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib2c2e00b11c294a8d5bdd07a2cd59503179f0a84 Reviewed-on: http://review.coreboot.org/9243 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2015-04-02rk3288/pinky: Move uart address to mainboard KconfigDavid Hendricks
Since the UART which is used for the serial console may change from board-to-board, this moves CONSOLE_SERIAL_UART_ADDRESS from rk3288's Kconfig into Pinky's Kconfig. BUG=none BRANCH=none TEST=built and booted on pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I29837a72d8cf205a144494a6c8ce350465118b34 Original-Reviewed-on: https://chromium-review.googlesource.com/221438 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 53bff629f2e9865656beabd81e6ce1eab7c728a9) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I65835c07a49dc3a3518c6bb24a29bc6ae7dd46c9 Reviewed-on: http://review.coreboot.org/9242 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-02Nyans: replace cpu_reset with hard_resetDaisuke Nojiri
The existing cpu_reset does board-wide reset, thus, should be renamed. BUG=none BRANCH=none TEST=Built firmware for Nyans. Ran faft on Blaze. Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9 Original-Reviewed-on: https://chromium-review.googlesource.com/212982 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 29753b9c1dfe7ecd156042d69b74e9fe4244f455) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I98eca40c50637bda01a9029a904bca6880cd081f Reviewed-on: http://review.coreboot.org/9179 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-02urara: Configure UART line control to 8N1Ionela Voinescu
8bit, 1 stop bit, no parity BUG=chrome-os-partner:31438 TEST=built urara bootblock and ran it on the Pistachio FPGA, observed expected console output. BRANCH=none Change-Id: Iface623f0b267f851e6d162d0321d56e3713a785 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4122ae983dba907c10d0d0980863ae7bf94eda5e Original-Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226551 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9185 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhzjinkun.hong
Add ddr3-samsung-2GB config and modify 533mhz linit. Support ddr3 freq up to 800mhz. Enable ODT at LPDDR3. BUG=None TEST=Boot Veyron Pinky Original-Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220113 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: I867753bc5d1eb301eb4975f5a945bfdba9b8f37d (cherry picked from commit e6689cbb0ec50317672c8ebe4e23555ca2f01005) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02rockchip: support pwm regulatorhuang lin
BUG=None TEST=Boot Veyron Pinky and test the VDD_LOG Original-Change-Id: Ie2eef918e04ba0e13879e915b0b0bef44aef550e Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219753 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: I444b47564d90b3480b351fdd8460e5b94e71927c (cherry picked from commit 4491d9c4037161fd8c4cc40856167bf73182fda6) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9240 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-02rockchip: support i2c clock settinghuang lin
BUG=None TEST=Boot Veyron Pinky and measure i2c clock frequency Original-Change-Id: I04d9fa75a05280885f083a828f78cf55811ca97d Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: Ie7ac3f2d0d76a4d3347bd469bf7af3295cc454fd (cherry picked from commit 4b9b3c2f8b7c6cd189cb8f239508431ee08ebc52) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)