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2016-12-13vendorcode/google/chromeos: Fill in firmware ID regionsPatrick Georgi
Chrome OS images have three firmware ID regions, to store version information for the read-only and the two read-write areas. Fill them with a suitable default and allow configuring a different scheme. There's already an override in google/foster and google/rotor to match the naming scheme used so far (in depthcharge). BUG=chromium:595715 BRANCH=none TEST=/build/$board/firmware/coreboot.rom has the expected values in the regions. Change-Id: I5fade5971135fa0347d6e13ec72909db83818959 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2e3be81faa8d21f92325294530714a4b18a1b3e Original-Change-Id: I2fa2d51eacd832db6864fb67b6481b4d27889f52 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/417320 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/17788 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-13lenovo: Don't use extern with functionsKyösti Mälkki
Change-Id: I8313ba1d93922297e5061701dad47d07617d1dcd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17804 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13mb/lenovo/*00: Remove Roda/RK9 specific codeNico Huber
Change-Id: Iacf2e1c0b8003a3588ccbf79e17500ed12f39503 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17786 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-12google/pyro: Set PL2 override to 15000mWKevin Chiu
This patch sets PL2 override value to 15W in RAPL registers and sets DPTF PL2 Max to 15W BUG=none BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17779 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11nb/intel/i945: Make pci_mmio_size a devicetree parameterArthur Heymans
Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. A safe minimum of 768M is also defined since using anything less causes problems (if 4G of ram is used). Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16856 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-11intel/nehalem: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17676 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel/i945: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Scratchpad register was read too late in ramstage so acpi_is_wakeup_s3() did not evaluate correctly. This fixes low memory corruption at 0x1000-0x102c and the lack of coreboot tables (util/cbmem not working) after S3 resume. This also fixes console log from reporting early in ramstage "Normal boot" while on "S3 resume" path. Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17675 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel/gm45: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setupKyösti Mälkki
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With this change, CBMEM region is set early-on as WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09mainboard/google/reef: fill in NHLT ACPI OEM header fieldsAaron Durbin
Fill in the NHLT ACPI OEM header fields to differentiate different audio solutions on a per board basis. This handles boards that share a firmware that are differentiated by the SKU id and boards that have their own firmware. For the latter, the Oem Table ID uses the VARIANT_DIR to differentiate. "reef" is always used for Oem ID which is treated as more of family in this case. iasl -d shows the following on reef: [00Ah 0010 6] Oem ID : "reef" [010h 0016 8] Oem Table ID : "reef" [018h 0024 4] Oem Revision : 00000008 BUG=chrome-os-partner:60494 BRANCH=reef Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17772 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-09mainboard/google/reef: add board SKU'ing supportAaron Durbin
There are 2 gpios on reef-like boards that can be composed into a SKU. Add support for identifying the SKU value using the base 3 gpio logic. Also export the SKU information to the SMBIOS type 1 table. BUG=chrome-os-partner:59887,chrome-os-partner:60494 BRANCH=reef Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17771 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-08google/eve: Add ASL code to describe SPI FPC1020 controllerDuncan Laurie
There is ongoing work to link SPI bus and devices in to the devicetree so this can be generated, but for now put in the raw ASL code to describe this controller so it can be used by the factory. BUG=chrome-os-partner:55538 TEST=successfully load fpc1020 kernel module on eve board Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17776 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08mainboard/google/reef: Set PL2 override to 15000mWSumeet Pawnikar
This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17730 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08google/beltino, tidus: simplify led_power_on() functionMatt DeVillier
Simplify set_power_led() by consolidating switch and setting values as needed inline based on LED state. Remove unnecesary function param, includes for Tidus. Change-Id: I28e6fac5f8d7e2ff419002db714ce88697895faf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17744 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07google/beltino: fix LED, simplify function for Tricky variantMatt DeVillier
Simplify set_power_led() by consolidating switch and setting values as needed inline based on LED state. Fix non-off LED polarity for Tricky using correct value from Chromium source TEST: power on Tricky, observe LED lit / solid Change-Id: I8bc7c4ae3f83d3f37b76fd5c90a4faed7057ebee Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17719 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07mainboard/google/reef: adjust chromeos.fmd regionsAaron Durbin
- Drastically reduced RW_MRC_CACHE size to hold one update. Now that this area isn't changing after every S5 entry there's no need make it so large. - ELOG area reduced by 4KiB for subsequent area alignment. In practice this doesn't matter because the elog library only uses 4KiB bytes. 16KiB->12KiB is a nop. - Moved RW_NVRAM for subsequent alignment. - Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries and sized to 64KiB multiples. This ensures updates don't need a read-modify-write that could force a system into recovery if an inopportune power event occurred. BUG=chrome-os-partner:60492 BRANCH=reef Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17727 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-06Bob: Update the memory ramid of bobShasha Zhao
Update the memory ramid. Move to one CA training pattern. BUG=chrome-os-partner:59454 BRANCH=firmware-gru-8785.B TEST=Build firmware passed Change-Id: Ic05cbc1700a13e372f63d5202459add0e984f9d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1030a78af3d489d13508f17a79df1e65bd5afa3b Original-Change-Id: Ibe8acb5b698cec1adcdddbb13d35a5e20a5b8c0d Original-Reviewed-on: https://chromium-review.googlesource.com/414664 Original-Commit-Ready: Shasha Zhao <Sarah_Zhao@asus.com> Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Change-Id: I0ae46e496cd18492a2b6c7167081798c2f2479b1 Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411645 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17679 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06Bob: add bob in corebootShasha Zhao
Add bob in coreboot and update as necessary. 1. Add bob HWID 2. Add supported memory source BUG=chrome-os-partner:59454 BRANCH=firmware-gru-8785.B TEST=Build firmware passed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: Iad03a293bdbbb89450f0fea0822e34a4be7064bf Original-Commit-Id: bff788c71a43403bff2c23b38e69cc27fb869559 Original-Change-Id: I0dcf47eb911337b176f73759a2c70a9dbf4dc68b Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411083 Original-Reviewed-by: Philip Chen <philipchen@chromium.org> Original-(cherry picked from commit c5925dfcf59ac755a26182744b2bde59e41a37cf) Original-Reviewed-on: https://chromium-review.googlesource.com/413744 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17678 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06rockchip/rk3399: sdram: use register to calculate sdram sizesLin Huang
We may support different sdram sizes on one board in future, so we need to calculate sdram sizes from sdram drvier. BRANCH=None BUG=None TEST=boot kevin Change-Id: I43e8f164ecdb768c051464b4dbc7d890df8055d0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c4d8b3cb647b2f9cebc416c298817c16d49330e Original-Change-Id: I95d5ef34de9d79ebca3600dc7a4b9e14449606ff Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411600 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17629 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06google/gru: Power-cycle USB ports in developer/recovery modesJulius Werner
Gru only uses USB 2.0 in firmware to avoid all the madness associated with Type-C port orientation and USB 3.0 tuning. We do this by isolating the SuperSpeed lines in the Type-C PHY so it looks like they aren't connected to the device. Unfortunately, some devices seem to already get "locked" into SuperSpeed mode as soon as they detect Rx terminations once, and can never snap out again on their own. Since the terminations are already connected during power-on reset we cannot disable them fast enough to prevent this, and the only solution we found to date is to power-cycle the whole USB port. Now, Gru's USB port power is controlled by the EC, and unfortunately we have no direct host command to control it. We do however have a command to force a certain USB PD "role", and forcing our host into "sink" mode makes it stop sourcing power to the port. So for lack of a saner solution we'll use this to work around our problem. BRANCH=gru BUG=chrome-os-partner:59346 TEST=Booted Kevin in recovery mode, confirmed that my "problem stick" gets detected immediately (whereas previously I had to unplug/replug it). Booted Kevin to OS in both developer and normal mode and confirmed that USB still seems to work. Change-Id: Ib3cceba9baa170b13f01bd5c01bd413be5b441ba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd695eda33299e50362f1096c46f2f5260c49036 Original-Change-Id: I2db3d6d3710d18a8b8030e94eb1ac2e931f22638 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/413031 Reviewed-on: https://review.coreboot.org/17628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06cpu/amd/mtrr.h: Drop excessive includesKyösti Mälkki
Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17736 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/cpu.h: Drop excessive includesKyösti Mälkki
Change-Id: Ifeef04b68760522ce7f230a51f5df354e6da6607 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17734 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Move SMM prototypes under x86Kyösti Mälkki
Change-Id: Iefbc17dcfcf312338d94b2c2945c7fac3b23bff6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17732 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17529 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06mb/lowrisc/nexys4ddr: Read RAM information from the config stringJonathan Neuschäfer
Change-Id: I9147eca0b536b6267d58f6e8baa37b6950b35160 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17710 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06mb/lowrisc/nexys4ddr: Initialize CBMEM in romstageJonathan Neuschäfer
Change-Id: Ic1706ae8ab3cbef8f445d70cb78fa9d3301d87be Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17707 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missingWerner Zeh
Do not abort the initialization of PTN3460 if HW-ID could not be retrieved and just assume that the HW-ID does not match 7.9.2.0. In this case PTN3460 will be setup to a working condition even if this field is missing. This makes this driver more robust with faulty blocks. Change-Id: I301fb165a7924768e44182d92be820294beb0280 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/17671 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-12-06AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already setKyösti Mälkki
It gets selected from CPU_AMD_MODEL10XXX. Change-Id: Iffab43edc1152b07ba2af6273d4b5eb94afe33ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17692 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05mainboard & southbridge: Clear files that are just headersMartin Roth
These headers & comments indicating a lack of functionality don't help anything. We discourage copyrights and licenses on empty files, so just clear these. Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17657 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-05Add/Combine Haswell Chromebooks using variant board schemeMatt DeVillier
Combine existing boards google/falco and google/peppy with new ChromeOS devices leon and wolf, using their common reference board (slippy) as a base. Chromium sources used: firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...] firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode] firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...] Additionally, some minor cleanup/changes were made: - I2C devices set to use ACPI (vs PCI) mode - I2C device ACPI entries adjusted as per above - I2C devices set to use level (vs edge) interrupt triggering - XHCI finalization enabled in devicetree - HDA verb entries use simplified macro entry format Existing google/falco and google/peppy boards will be removed in a subsequent commit. Variant setup modeled after google/beltino Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17621 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-05Remove boards google/falco and google/peppyMatt DeVillier
No need for these boards to exist separately once included as variants under google/slippy Change-Id: I52a476ceaadf50487d6fe21e796d7844f946d8b3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17622 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-03mainboard/intel/kblrvp: Enabling Kaby Lake RVP7Barnali Sarkar
Add support for Kaby Lake RVP7 board * Add RVP7 board support in Kconfig * Override default descriptor and ME binary paths in Kconfig since those binaries will differ for RVP3 and RVP7 * Add RVP7 board name in board_info.txt and Kconfig.name * Add devicetree.cb for RVP7 in the variants path * Add gpio.h for RVP7 in variants/include/variant path * Made board specific code for retrieving spd, i.e., in RVP7 there is non-soldered DIMMs, so SPD is read through smbus, unlike RVP3 where memory DIMMs are soldered down with board. Hence for RVP3, the spd binaries will be fixed and can be kept as binary file in cbfs. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP7 Change-Id: I6f3d17d857bad1b5cf39f0bc900c760fee72da48 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02google/pyro: set i2c bus timings by rise/fall timesKevin Chiu
Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot Change-Id: I68be9b96dc731eb0084ee5e15921866818637e73 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02mainboard/google/reef: Add all DMIC endpointsSathyanarayana Nujella
Independent of Board DMIC configuration, add all DMIC points i.e. add DMIC-1ch, DMIC-2ch, DMIC-4ch endpoints. This allows flexibility to userspace to open capture devices as needed. This is a temporary fix; once upper layers support choosing particular channels from 4-ch PCM stream, we will limit exposing only DMIC-4ch endpoint. BUG=chrome-os-partner:60444 BRANCH=none TEST=Verify All DMIC blobs are included Change-Id: I9729a3570c0668f3da4e7986291ebad6fe1de47a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17660 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01mainboard/google/reef: allow variants to modify nhlt oem revisionAaron Durbin
In order to mirror the full flexibility of the NHLT library that allows a caller to set the OEM revision field in the ACPI header modify the variant callback to override the value. Change-Id: I16e539b350a50e3c163be1439c8637b82e53a759 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17651 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-12-01lib/nhlt: add support for setting the oem_revisionAaron Durbin
In the ACPI header there's an OEM revision field that was previously just being implicitly set to 0. Allow for a board to provide a non-zero value for this field. Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17650 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01lib: put romstage_handoff implementation in own compilation unitAaron Durbin
Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17648 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17534 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01asus/f2a85-m msi/ms7721: Enable MMCONF earlyKyösti Mälkki
PCI MMCONF access only works after amd_initmmio() call. Change-Id: I5765604e178d09abdd6bb6ce7cc220bc5b35ed03 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA f14: Consolidate early P-states settingKyösti Mälkki
Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA f14: Consolidate XIP cacheKyösti Mälkki
Do this like fam15tn to reduce code duplication. Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17563 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30mainboard/artecgroup/dbe61/mainboard.c: Use tab for indentsElyes HAOUAS
Change-Id: I111ded7cc3cac21e4be6329209fdd067f313010a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17662 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-30mb/intel/kblrvp: Add Variant board support for KBLRVPBarnali Sarkar
Add support of Variant board model for existing intel/kblrvp, since there might be more RVP board supports under intel/kblrvp. Existing is for KBL RVP3 board. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP3 Change-Id: I041a07a273dbb77e422d48591f06b5f1011cd9f7 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17630 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-30mb/intel/kblrvp: Use common lib spd_bin to get spdNaresh G Solanki
Use common lib spd_bin to get spd. Change-Id: If94413fc36a98f7694f560955bbb80abefe32166 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30mainboard/intel/kblrvp: Revert back USB OC pin programmingBarnali Sarkar
With commit 2c3054c1(soc/intel/skylake: Add USB Port Over Current (OC) Pin programming) USB OC pin programming is already initiated from devicetree.cb, hence remove it from ramstage.c. BUG=none BRANCH=none TEST=Built and booted KBLRVP from USB device Change-Id: Icb47533aa57f208d5a52560db924169b908c7a88 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17635 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30mainboard/google/snappy: Tune i2c frequency to 400 KhzWisley Chen
tune i2c devices clk for snappy: I2C0: audio I2C2: TPM H1 I2C3: elan touchscreen I2C4: elan touchpad I2C5: wacom digitizer BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage, and measured on EVT. audio: Freq. 393.7kHz Rise Time 58.8ns Fall time 12.11ns TPM H1: Freq. 398.8kHz Rise Time 31.71ns Fall time 13.28ns elan touchscreen: Freq. 390.5kHz Rise Time 235.7ns Fall time 37.64ns elan touchpad: Freq. 393.7kHz Rise Time 288.8ns Fall time 51.67ns wacom digitizer: Freq. 388.8kHz Rise Time 124.1ns Fall time 21.10ns Change-Id: Ib2be9e1575d4962476423eafa80f9bb10ba40e17 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17634 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-30mainboard/reef: Add RW_VAR_MRC_CACHEAndrey Petrov
Chop off 4kb block from RW_MRC_CACHE to store variable MRC cache. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I3e19fff9c9b20d6c73cbb13bfeec49e9a274bb72 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17235 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30mb/google/oak: replace symbolic linksMartin Roth
These three files were added as symbolic links to the other files in the same directory. Delete the links, and copy the real files into their places. Because of the varied environments that coreboot is built in, we don't want to have symbolic links in the tree. These three files were the only cases of symbolic links. Change-Id: If69f40c2c4cdcabc4fdfc1d6026a91c0791756da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17632 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-30mb/gigabyte/ga-945gcm-s2c: Add mainboard using variantsArthur Heymans
This mainboard is identical to ga-945gcm-s2l except for NIC which is a Realtek RTL 8101E chip (10/100 Mbit). The schematics of ga-945gcm-s2l mention multiple NICs and ga-945gcm-s2c and ga-945gcm-s2l have a common manual further indicating that those boards are close to identical. Change-Id: Iba3d401efcf208154e639c3237b201830a5151aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17416 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-29mb/kontron/ktqm77: Enable native gfx init through libgfxinitNico Huber
Change-Id: Ie16b3236e7378a2062b3081e4530d7a4791b4b66 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17074 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-29google/gru: Tune USB 2.0 PHY to increase compatibilityWilliam wu
When testing USB 2.0 compatibility with different kinds of USB 2.0 devices on Kevin board, we find that some USB HDDs (e.g. seagate SRD00F1 1TB HDD) and some smart phones (e.g. galaxy A5 smart phone) can't be detected. And according to the error log, this issue is related to USB 2.0 PHY signal problem. For the USB HDD, error log is: [ 592.557724] usb 5-1: new high-speed USB device number 2 using xhci-hcd [ 592.847735] usb 5-1: new high-speed USB device number 3 using xhci-hcd [ 593.473720] usb 5-1: new high-speed USB device number 6 using xhci-hcd [ 594.187717] usb 5-1: new high-speed USB device number 9 using xhci-hcd [ 595.020717] usb 5-1: new high-speed USB device number 13 using xhci-hcd [ 595.284730] usb 5-1: new high-speed USB device number 14 using xhci-hcd [ 595.574816] usb 5-1: new high-speed USB device number 15 using xhci-hcd The log shows that HDD failed to high-speed handshake. For the smart phone, error log is: [ 1145.661625] usb 5-1: new high-speed USB device number 2 using xhci-hcd [ 1145.771674] usb 5-1: device descriptor read/64, error -71 [ 1145.979752] usb 5-1: device descriptor read/64, error -71 [ 1146.187721] usb 5-1: new high-speed USB device number 3 using xhci-hcd [ 1146.301754] usb 5-1: device descriptor read/64, error -71 [ 1146.509750] usb 5-1: device descriptor read/64, error -71 [ 1146.717722] usb 5-1: new high-speed USB device number 4 using xhci-hcd [ 1146.724393] usb 5-1: Device not responding to setup address. [ 1146.930795] usb 5-1: Device not responding to setup address. [ 1147.137720] usb 5-1: device not accepting address 4, error -71 [ 1147.246644] usb 5-1: new high-speed USB device number 5 using xhci-hcd [ 1147.253336] usb 5-1: Device not responding to setup address. [ 1147.459786] usb 5-1: Device not responding to setup address. [ 1147.665712] usb 5-1: device not accepting address 5, error -71 [ 1147.671789] usb usb5-port1: unable to enumerate USB device The log shows that smart phone failed to read device descriptor, error -71 may be caused by PHY signal problem. This patch aims to tune USB 2.0 PHY with the following parameters to support USB HDD, smart phone and some other potential USB 2.0 devices. 1. Disable the pre-emphasize in chirp state to avoid high-speed handshake failure. 2. Bypass ODT auto compensation to enable set max driver strength manually. (Bit[42] of usbphy_ctrl register is 1'b1 for bypass, and Bit[41:37] of usbphy_ctrl register is 5'b10000 for max driver strength). 3. Bypass ODT auto refresh, and set the max bias current tuning reference. (Bit[57] of usbphy_ctrl register is 1'b1 for bypass, and Bit[52:50] of usbphy_ctrl register is 3b'100 for max bias current tuning reference). We have done the USB 2.0 compliance test and compatibility test with this patch, it works well. BRANCH=gru BUG=chrome-os-partner:59623 TEST=plug/unplug USB HDD or smart phone in Type-C port, check if they can be detected successfully. Change-Id: I275c2236b8e469bfd04e9184d007eb095657225e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7735c514d4136978133c2299f2f58da8320bb89f Original-Change-Id: I4e6c10faa1c03af9880a89afe4731a7065eb1e4e Original-Signed-off-by: William wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/409856 Original-Commit-Ready: Eddie Cai <eddie.cai.rk@gmail.com> Original-Tested-by: Cindy Han <cindy.han@samsung.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17566 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-29google/pyro: disable unused devicesKevin Chiu
The following devices i2c5, i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: I3b7b96e72b82af1885926800ee99beff07755bbc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17589 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-29mainboard/google/snappy: Add digitizer device to devicetreeWisley Chen
BUG=chrome-os-partner:59034 BRANCH=none TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ib99ae5357274ad0824d0989888dfddcb32ace7e2 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29mainboard/google/reef: Set DPTF CPU passive temperature trip point to 95CSumeet Pawnikar
This pach sets the DPTF passive temperature trip point for CPU back to 95 degree celsius from 61 degree celsius as per previous thermal optimizations (https://review.coreboot.org/#/c/16766/). BUG=chrome-os-partner:60038 BRANCH=master TEST=built, booted on Reef and verified the passive trip point funtionality. Change-Id: I83ce69b19a94e4ea8ebedfc06f259579ed6dd5d3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17598 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29google/oak: Add DRAM configuration for Samsung K4E8E324EBPH Hsu
Add the configuration for Samsung K4E8E324EB and assign it to RAM_CODE 5. BUG=chrome-os-partner:58983 TEST=verified on Hana EVT. Change-Id: Iea55eb393b21e37f36d454706531f588101ee651 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38d34ed0a0b420e1ab300a47b99035153be5b5d0 Original-Change-Id: I28724c1cf5cf12f47911a571c20280ddab4500d5 Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/410926 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-28mb/gigabyte/ga-945gcm-s2l: Configure SuperIO ECArthur Heymans
Change-Id: Id7c2b656f500c14f39d4492667ea461b9ca353b0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17613 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-28soc/intel/skylake: Add USB Port Over Current (OC) Pin programmingSubrata Banik
Program USB Overcurrent pins as per board schematics definition. BUG=none BRANCH=none TEST=Build and boot kunimitsu from USB device. Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-28mb/intel/d945gclf: Add cmos.defaultArthur Heymans
With this the system falls back to sane default settings when nvram is invalid. Change-Id: Ie13fd01c4f8403cbedbd7497ad9012c30f494a69 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17042 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-11-28mainboard/google/reef: Set PL1 MAX power limit value to 12WTim Chen
Set PL1 maximum power limit value back to 12W (https://review.coreboot.org/#/c/16596/) from 6W due to Intel's and thermal team's suggestion. BUG=chrome-os-partner:60038 BRANCH=master TEST=build, boot on electro dut and verify by thermal team member Change-Id: I57ae29180962724fde72d522caa542f0f21d5922 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17574 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-28mb/gigabyte/ga-g41m-es2l: Tie in configuration for SuperIO ECDamien Zammit
Change-Id: Ifba821a7e355a0d6689f21c7f307e3901903a3fd Signed-off-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17602 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-25google/parrot: Fix keyboard interrupts, DSDTPrabal Saha
Commit 967cd9a [ChromeOS: fix Kconfig dependencies] broke keyboard interrupts on parrot by making SERIRQ_CONTINUOUS_MODE conditional on CONFIG_CHROMEOS, which it should not be; fix by moving back under main board specific options config. Additionally, Windows [8/8.1/10] fails to enumerate the keyboard when its ACPI entry is located under the SIO device since it is missing an _HID entry, so add the appropriate value per ACPI spec 5 ch. 9.7 Change-Id: Ia69e9b326001d2026b15b4ec03c94f7d03c8a700 Signed-off-by: Prabal Saha <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17017 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24mc_tcu3: Swap LVDS even and odd lanes for a certain hardwareWerner Zeh
Due to some LVDS cable constraints even and odd lanes needs to be swapped on certain hardware. The hardware ID will be used to distinguish between these two cases. The swapping itself will be done by PTN3460, which is configurable for that. Change-Id: I339b2321a8ed1bc3bbf10aa8e50eb598b14b15fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/17576 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-11-24mb/ga-945gcm-s2l: Enable EC I/O decode range.Arthur Heymans
Change-Id: I021aae6130c475cb370b891ffaec6f1ad267540b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17580 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24Add Haswell Chromeboxes/Chromebase using variant board schemeMatt DeVillier
Combine existing board google/panther with new ChromeOS devices mccloud, monroe, tricky, and zako, using their common reference board (beltino) as a base. Chromium sources used: firmware-mccloud-5827.B 65bfee7 [haswell: No need pre-graphics delay...] firmware-monroe-4921.B 1ac749d [Monroe: Disable KB/MS in ITE8772.] firmware-tricky-5829.B 2db5322 [haswell: No need pre-graphics delay...] firmware-zako-5219.B eacedef [haswell: No need pre-graphics delay...] Existing google/panther board will be removed in a subsequent commit. Variant setup modeled after google/reef Change-Id: I5d7e0c2551e8b0707841032460c35615cefb2886 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17329 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-24Remove board google/pantherMatt DeVillier
Once #17329 is committed, no reason to have google/panther exist as a separate board anymore. Change-Id: I9a11273c39423d5ff33a7d1f91c8d8cffef97ec1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17538 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-11-23google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU passive point:57, critical point:90 TSR1 passive point:55, critial point:70 TSR2 passive point:65, critial point:80 2. Update DPTF TRT Sample Period. CPU: 5s TSR0: 50s TSR1: 55s TSR2: 120s BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: Ib1b4b31a49d9396b1c5c9dd8d0b9b9998d01744f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17552 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-23veyron_*: Remove obsolete ChromeboxesDavid Hendricks
This removes brain, danger, emile, and romy from the tree. This was cherry-picked from the chromeos-2016.02 branch (CL:345574), but conflicts showed up in many files that were to be deleted anyway possibly due to some widespread refactoring that was done between then and now. BUG=chromium:612660 BRANCH=none TEST=none Change-Id: Ie37140a9a4bb9d820a3fcbad6674b2fa737e1249 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1ebe5038a82162f6345e319de7578f26ccd68b73 Original-Change-Id: I11f7e0870916871d8f146a6871370ace76ddec49 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/412424 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17569 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-11-22mainboard/ms7721: Add MSI MS-7721 (FM2-A57MA-E35)Renze Nicolai
Adds support for the MSI MS-7721 (FM2-A75MA-E35) motherboard. Tested by building coreboot with: - VGA bios (needed for onboard video) - XHCI firmware - SeaBIOS payload CPU: AMD A8-6500 APU RAM: 2x 2GB Samsung M378B5673EH1 Confirmed booting using: - USB stick with Arch Linux (kernel 4.7.5) - Gentoo live CD from SATA dvd drive - Gentoo installation from SATA harddisk (kernel 4.4.26) Change-Id: I757e011de01ca9f340fd524b10e7fa3f291d53e3 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/17495 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-22mainboard/ms7721: Copy files from "asus/f2a85-m" to "msi/ms7721".Renze Nicolai
This patch adds a copy of the Asus F2A85-M code with only minimal changes. (to ensure that the code compiles) A second commit will be published to remove the copied code parts that don't apply to the MS-7221 and to make everything else actually work on the MS-7221 board. Change-Id: I1426c0876c7bfeb264231c0d338301133c721484 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/17494 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22intel FSP sandy/ivy: Move select MMCONF_SUPPORTKyösti Mälkki
Note: Platforms have no MMCONF_SUPPORT_DEFAULT. Change-Id: I8a02ea78957fca23b1cf161a00d5e3edda73d683 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17543 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22mb/gigabyte/ga-g41m-es2l: Add MAX_CPU = 4 in KconfigArthur Heymans
This motherboard support Intel core 2 quads. Before this change SeaBIOS was not usable, due to it crashing before it got to load anything. Change-Id: Ifdaaceace04f9ba0753aab2d3b05c0519367f91f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17537 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-21mb/ga-g41m-es2l: Correctly configure PCI IRQ in ACPIArthur Heymans
Obtained from vendor bios DSDT, under "Device (HUB0), Name (_ADR, 0x001E0000)". The schematics also indicate that the INTA-D are hardwired to these PIRQ lines. Change-Id: I8e1c6cb986a2b345a5e1fddd454c7fb12fb8256a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17099 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-21lenovo/x200/board_info.txt: Add SOIC-8 to ROM packageMichał Masłowski
Some X200 use a 4 MiB SOIC-8 flash chip. Change-Id: Ie5bd359ef08cf1be369a026be376c21555d0ea18 Signed-off-by: Michał Masłowski <mtjm@mtjm.eu> Reviewed-on: https://review.coreboot.org/8391 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-21mb/siemens/sitemp_g1p1/cmos.layout: Re-add cmos_defaults_loadedNico Huber
I guess it was dropped because its concept was misunderstood. The idea is to always have it set to `Yes` in the cmos.default. Users can then ack the loading of the defaults by setting it to `No`. If the defaults ever get loaded again, they'll be notified by the default `Yes`. Change-Id: I1aa6d75bd5aa153c7b11a6b74564272eaa7cc523 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17355 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-20intel sandy/ivy: Improve DIMM replacement detectionKyösti Mälkki
When MRC cache is available, first read only the SPD unique identifier bytes required to detect possible DIMM replacement. As this is 11 vs 256 bytes with slow SMBus operations, we save about 70ms for every installed DIMM on normal boot path. In the DIMM replacement case this adds some 10ms per installed DIMM as some SPD gets read twice, but we are on slow RAM training boot path anyways. Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17491 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-11-20mainboard/google/reef: Update DPTF parameters provided from thermal teamTim Chen
Update the DPTF parameters based on thermal test result. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU passive point:61 TSR0 passive point:120, critial point:125 TSR1 passive point:46, critial point:75 TSR2 passive point:100, critial point:125 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 3W, and max to 6W Set PL2 min to 8W 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 80secs Change CPU Effect on Temp Sensor 0 sample rate to 120secs The TRT of TCHG is TSR1, but real sensor is TSR2. Change Charger Effect on Temp Sensor 2 sample rate to 120secs Change CPU Effect on Temp Sensor 2 sample rate to 120secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: I7a701812cb45f51828a3cbb3343e03817645110e Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-18ec/lenovo/h8: Add USB Always OnNicola Corna
USB AO is the internal name for the dedicated charging port on ThinkPads when in S3 or lower. AOEN (bit 0) is internal name for enabling this feature while AOCF (bits 2 and 3) is the configuration field. According to Peter Stuge, AOCF can be configured in this way: 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off 10, 01 => equivalent to 00 This commit also adds a new configuration field in the CMOS of the X220 and the X201 to activate this feature. It probably can be also added to all the ThinkPads that support this functionality. With this functionality USB devices are able to negotiate full power from the dedicated port (usually the yellow one) even in S3. Tested on a X201 and X220 with an Android smartphone: with this feature enabled it shows "Charging" when connected during S3, without it it shows "Charging slowly" (or it doesn't charge at all on the X201). For some reasons the "AC only" mode doesn't work, so it has been disabled. Change-Id: Ie1269a4357e2fbd608ad8b7b8262275914730f6e Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/17252 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-18google/chromeec: Add common infrastructure for boot-mode switchesFurquan Shaikh
Instead of defining the same functions for reading/clearing boot-mode switches from EC in every mainboard, add a common infrastructure to enable common functions for handling boot-mode switches if GOOGLE_CHROMEEC is being used. Only boards that were not moved to this new infrastructure are those that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific mechanism for reading boot-mode switches. BUG=None BRANCH=None TEST=abuild compiles all boards successfully with and without ChromeOS option. Change-Id: I267aadea9e616464563df04b51a668b877f0d578 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17449 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-11-17google/snappy: Update DPTF settingsWisley Chen
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU passive point:100, critical point:105 TSR1 passive point:48, critial point:65 TSR2 passive point:85, critial point:100 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 3W, and max to 6W Set PL2 min and max to 8W 3. Change thermal relationship table (TRT) setting. The TRT of TCHG is TSR1, but real sensor is TSR2. BRANCH=master BUG=none TEST= Compiled, verified by thermal team. Change-Id: Ib197c36eca88e3d05f632025cf3c238e1a2eae23 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17426 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17mainboard/google/reef: disable unused devicesJagadish Krishnamoorthy
The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=chrome-os-partner:59880 TEST=Boot to OS and lspci command should not list the above disabled devices. Change-Id: I819cdb34709703e6431b49446417ed9d6b3543cd Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/17441 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-17mb/intel/kblrvp: Remove unused configs in KconfigNaresh G Solanki
Remove unused drivers & nhlt in Kconfig. Change-Id: Ic1e8a98a77a0061e749019665f955b921f85975e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17427 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17mainboard/google/reef: set i2c bus timings by rise/fall timesAaron Durbin
Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58889,chrome-os-partner:59565 Change-Id: I0c84658471d90309cdbb850e3128ae01780633af Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17397 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-17google/gru: Move to one CA training patternDerek Basehore
This changes memory to only do CA training with one pattern, 0xfffff/0x00000 and to also make sure CA training waits for all of the captures during training. BRANCH=none BUG=chrome-os-partner:56940 TEST=boot kevin and run stressapptest -M 1500 -s 1000 Change-Id: I0982674b4f4415f4d7865923ced93fa09bdd877e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 75cdd911cea9c4e5744fd04505b260fa5755513c Original-Change-Id: I3b86e6d4662c6fbbf9ddef274fce191a367904e5 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/410320 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/17383 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17google/gru: Add new CA training patternDerek Basehore
This adds a new CA training pattern for all of the supported frequencies. This pattern increases the hold time on CA. BRANCH=none BUG=chrome-os-partner:57845 TEST=boot kevin and run: while true; do sleep 0.1; memtester 500K 1 > /dev/null; done for several hours Change-Id: Ie5958cf67c16247ef90ee261da9faef4ffa5b339 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8babeafe75bffcb2dab17eb007b4f5bb0eb42606 Original-Change-Id: I7f7652f88e43dc9b2f6069e60514931bf7582ed1 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/403547 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/17382 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17google/oak: Add more DRAM modules supportPH Hsu
Add support for following 3 modules. - Micro MT52L256M32D1PF / MT52L512M32D2PF - Hynix H9CCNNNBJTALAR Hana EVT was planed to add 4 DRAM modules but RAM_CODE=5 is not used in the end. This patch also unifies the naming of the RAM configurations. BUG=chrome-os-partner:58983 TEST=verified on Hana EVT. Change-Id: I7dd44525de8e9dde01f210f4730fa8ccd4baef21 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5dccd68149bcfd6fd0a83e310d43063bab645691 Original-Change-Id: I7c245c8c24be159e152f4f3cca25bf970b58425c Original-Signed-off-by: Milton Chiang <milton.chiang@mediatek.com> Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/402888 Original-Reviewed-by: Pin-Huan Hsu <ph.hsu@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Paris Yeh <pyeh@chromium.org> Reviewed-on: https://review.coreboot.org/17381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-16mainboard/google/reef: Add proper DMIC endpoints based on DMIC config pinSathyanarayana Nujella
Reef board uses GPIO_17 as DMIC config pin. This pin distinguishes board with Quad DMIC's or Mono DMIC. This patch adds necessary DMIC endpoints to support either of those configurations. CQ-DEPEND=CL:*304339,CL:409774 BUG=chrome-os-partner:56918 BRANCH=none TEST=Verify Mono and Quad Channel DMIC record Change-Id: I5b2825b5f39f8962985a129f8ec65265fb18f0b2 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17158 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-16mb/ga-945gcm-s2l: Clean up SuperioArthur Heymans
GPIO register at offset 0xfc (VID Input Register) is read-only but writing 1 to bit 0 will update initial VID input. Change-Id: Ie372e98f8e497eede382975262a63d58c16227b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17412 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-16google/eve: Fill out memory ID tableDuncan Laurie
Add the DIMM SPD data for memory types that are not used yet but are on the matrix and may be used in future builds. Also fix a typo in the part number string for one type. BUG=chrome-os-partner:58666 TEST=build and boot on eve p0 Change-Id: I20401d7afb69f1c3ae1a3b0d6e3ec9097f54ef96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17437 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-15mainboard/via/vt8454c: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/via/vt8454c. Change-Id: I94e22e1d814733c4049e78e5b3c23b9bb429f6fa Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17312 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15mainboard/via/epia-m700: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/via/epia-m700. Change-Id: I7a16a9f396d50279cf2bd13de72bd78e8f53f7d8 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17311 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15mainboard/via/epia-cn: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/via/epia-cn. Change-Id: I1b05abcedc427e4876e1fdab85298015308a3d17 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17310 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15mainboard/tyan/s8226: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/tyan/s8226. Change-Id: I41729fc03518a7804ae224c773967453a7ab60a7 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17309 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15google/link/i915.c: Fix build error when native gfx init enabledIru Cai
- Move members of struct edid to struct edid_mode - Change `u32 pmmio` to `u8 *pmmio` in i915_lightup_sandy Change-Id: Id64daf5eae1d4d8265105067b2e6ae55786a5638 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/17332 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-14google/chell : update DPTF policy settingsSumeet Pawnikar
Fine tuned DPTF policy values for chell device as below, 1. Increase Passive temperature value to 52 degree Celsius for TSR2. 2. Remove charger effect for TSR2. 3. Increase Minimum PowerLimit1 to 3W. 4. Reduce Maximum PowerLimit1 to 6W. BUG=chrome-os-partner:54718 BRANCH=None. TEST=Built for chell device. Change-Id: I46f69e3cd527ea3d28bdd7daa29d91f76770c277 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17376 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14intel/kblrvp: Enable TPMNaresh G Solanki
Add choice to build without TPM, TPM 1.2 support or TPM 2.0 support. Additionally configure lpc clock pad used with LPC TPM & update devicetree.cb. Change-Id: I1c24fdefa6e73637b3037ecf118559abe5fde300 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17367 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 20:13:08 +0000