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Enable PCIe port 5 for WLAN device
BUG=b:261514079
BRANCH=firmware-brya-14505.B
TEST=Build and boot on marasov.
Ensure that the WLAN module is enumerated in the output of lspci.
localhost ~ # lspci
01:00.0 Network controller: MEDIATEK Corp. MT7921 802.11ax PCI Express Wireless Network Adapter
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I007501bb00e2b7b83de1292f3066874d07646cb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70442
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on the SKU plan, add FW_CONFIG definition.
BUG=b:260473966
BRANCH=None
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I727f69e8fe340cfe624adb5a49bd080ba9544786
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70418
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based
on the state of the system while `SLP_S0_L` signal is `low` (while
the system is in S0ix).
Implemented runtime ASL method (MS0X) being called by PEPD device
_DSM to configure `SLP_S0_GATE (GPP_H14)` PIN at S0ix entry/exit.
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One))
{
\_SB.PCI0.CTXS (0x75)
}
Else
{
\_SB.PCI0.STXS (0x75)
}
}
BUG=b:256807255
TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70196
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<device/mmio.h>` chain-include `<arch/mmio.h>:
https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes
Also sort includes while on it.
Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Replace the amdblocks/gpio.h and soc/gpio.h includes with the common
gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h
in the AMD SoC case.
Since baseboard/ec.h and indirectly baseboard/gpio.h files will get
included in the DSDT, the soc/gpio.h includes in those aren't replaced
with a gpio.h include for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib982e338b5c6bc145ec1a8f6dd75175a42dfb426
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70436
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace the amdblocks/gpio.h and soc/gpio.h includes with the common
gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h
in the AMD SoC case.
Since baseboard/ec.h and indirectly baseboard/gpio.h files will get
included in the DSDT, the soc/gpio.h includes in those aren't replaced
with a gpio.h include for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa82c10d10e4438b0437b78ddd95b5e823805571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70435
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2e1978f20b085f609cbeb0907374383f2d11fbf0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70474
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds MTL-P board id definition. Change include,
1. Add board_id.c implementation
2. Add board_id.h implementation
3. Add board_id config in variants.h
4. Makefile changes
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I90b0543d5db208f696d2c2c2dc3d2581514a845b
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66102
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch adds the initial code for mtlrvp_p_ext_ec variant board
which includes
1. support for 2 mainboards (Chrome EC and Windows EC) by
adding overridetree.cb to corresponding directory
2. Move devicetree to baseboard/mtlrvp_p
3. Update mainboard name in Kconfig and Kconfig.name
4. Add config option to select corresponding overridetree.cb
Subsequent patches include patch train starting from (CB - 66102)
BUG=b:260654043
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
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Found using 'Wmissing-include-dirs' command option.
Change-Id: Ie0e31fcdbeb219d3ecbe14a492d3e7824f6a51cc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70397
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables V1p05 and Vnn external bypass VRs for Marasov.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id28305b02e86f5ac55382ac6d2bd5e0453aae9b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Adjust the bit fields in the FW_CONFIG for Proto Phase.
BUG=b:254404046
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=marasov emerge-brya coreboot
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ia71269918092655c11c2b37a26ec19123f759650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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This patch enables S0ix for Google/Rex platform.
BUG=b:256807255
TEST=Able to program FADT table Bit 21 (Low Power Idle S0)
Change-Id: I79546267d29622c65321f7dfa29d3aac2fa59438
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70430
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Drop the __weak qualifier as this function is not overridden.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ica25b2bc4325ff9d27be672926b4e3b550c86e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Found using 'Wmissing-include-dirs' command option.
Change-Id: Ie9ff43432215ebc89e6c1ea5f86b248e7fecd943
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70396
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace the amdblocks/gpio.h, amdblocks/gpio_defs.h and soc/gpio.h
includes with the common gpio.h which will include soc/gpio.h which will
include amdblocks/gpio.h which will include amdblocks/gpio_defs.h in the
AMD SoC case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I37a33dd8821a00b7edfd1e5b593f71bea0e77630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70434
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Replace the amdblocks/gpio.h, amdblocks/gpio_defs.h and soc/gpio.h
includes with the common gpio.h which will include soc/gpio.h which will
include amdblocks/gpio.h which will include amdblocks/gpio_defs.h in the
AMD SoC case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I13bc33b91f6e6d52867da9043bb386f3befac5fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70433
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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option STORAGE_EMMC 0
option STORAGE_NVME 1
BUG=b:239513596
TEST=FW_NAME=gladios emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I27baa2ca8c2b334fb81aa87b22c3b7c028c38cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Enable Dynamic DPTC support.
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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DTTS indicated Dynamic Thermal Table Switching.The proposal would like
to develop the schematic for switching 6 thermal table by lid status,
machine body mode and temperature. After entering the OS, the thermal
table would be table A. If the “Motion” or “Lid status change” is
detected. The thermal table would switch to laptop mode or lid close
mode.
Once the higher environment temperatures are detected,the thermal
table would switch to the corresponding power throttle table (B, D or
F). Based on these table switching mechanisms, no matter how the
end-user uses Chromebook,they could enjoy more humanized thermal
designs.
Release Over Over Release .
Temp. Temp. Temp. Temp. .
-------------------------------------------------------- .
Desktop mode Table A Table B 50C 45C .
Lid open (Default) .
-------------------------------------------------------- .
Desktop mode Table C Table D 55C 50C .
Lid close .
-------------------------------------------------------- .
Laptop mode Table E Table F 45C 40C .
-------------------------------------------------------- .
On the proposal, the transmission rules are list below:
1. Table A is the default table after booting.
2. A, C, E (Release Temp) can switch to each other.
3. B, D, F (Over Temp) can switch to each other.
4. A and B, C and D, E and F can switch to each other.
5. If Lid open/close or mode switch event trigger, temperature release
tables will translation to each other, temperature over tables will
translation to each other.After that event trigger, EC will check the
new temperature condition and decide if the temperature need to be
trigger.For example, if table A will switch to table D, table A will
switch to C with Lid close event, if temperature is over 55C, EC will
trigger temperature to switch form table C to D.
6. EC will trigger 3 times body-detection events during power on boot
without any body-mode and lid status change. For this case if the
previous table label is on same group, we will based on the temperature
to decide the table.
For example, assume table A is current table. When the temperature
reaches 50C, than the table is switched from A to B. The current table
is B. When the temperature is downgrade below 45C, the table is
switched form B to A. The same rule is for C and D, E and F.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Enable STT and set 6 thermal table profiles for Dynamic Thermal Table
Switching Proposal support.
BUG=b:232946420
BRANCH=none
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ie0740cb5bb16cd53c2ee6937e32a974346012823
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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This patch generates the following for the mainboard:
Scope (\_SB)
{
Method (MPTS, 1, Serialized)
{
Local0 = \_SB.PCI0.RP06.RTD3._STA ()
If ((Local0 == One))
{
\_SB.PCI0.RP06.PXSX.DPTS (Arg0)
}
}
}
Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70229
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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option STORAGE_EMMC 0
option STORAGE_NVME 1
BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Idd52112743ee0d64aca630e54511503607770d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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LARS has two variants, LARS and LILI, which are differentiated via
the customization_id field in the VPD. To make differentiation easier
outside of ChromeOS (ie, for Windows/Linux drivers), set the SKU ID
based on VPD so it can be easily read via SMBIOS.
Modeled after similar code in google/reef (snappy variant).
TEST=build/boot lili variant, verify sku1 populated in SMBIOS tables.
Change-Id: I148462b6f86b25fa8db26ea6e1537d1a5e47984b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I74f943e9b616458a16aa13c29706cf1551fcbbb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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There are four requirements for the SMI to hit a printk()
this commit now removes.
Build must have DEBUG_SMI=y, otherwise any printk() is a no-op
inside SMM.
ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value.
Platform needs to have IO Trap #3 enabled at IO 0x800.
The SMI monitor must call io_trap_handler for IO Trap #3.
At the moment, only getac/p470 would meet the above criteria
with TRAP(0x32) in its DSDT _INI method. The ASL ignores any
return value of TRAP() calls made.
A mainboard IO trap handler should have precedence over
a southbridge IO trap handler. At the moment we seem to have
no cases of the latter to support, so remove the latter.
Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I4819909cf9460ca550af38ca73a50220b77a385f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Avoid calling a function named mainboard_io_trap_handler() when
the dock (dis)connect is not triggered from IO trap.
Change-Id: Idc258a390f2de2c32d38a0e35fcce896d058d1b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Two GPIOs were set as SCI, but are not GEvent capable pins on morgana.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I00dc1b2595c047ce6898b394061d119ac8680755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Modify the configuration of GPIO_74 (PMIC Thermal Trip Point) as
in it's current configuration, it stops the laptop entering S5.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0e31f095ff42a03e3ea1496fe67d69b0f1763a3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Configure mayan GPIOs per schematic 105-D59700-00A Rev 1.00
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I283afc716487fd8fa6d455194c382d87a3e6860b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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DmaProperty must only be present on endpoint devices.
BUG=b:259716145
TEST=TBD
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic5be85c3d13250646867f8c8f5950796ec339551
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Function definitions without a type a deprecated in all versions of C.
Change-Id: I2efb42e653b0deb56ba6b0c9789764a9cabc552e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70138
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change the EC FW CBFS filename prefix to a more accurate "ec/"
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic789df11160e3ffe7b7294b11e1fa80e3c3961ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70206
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable SOC_AMD_COMMON_BLOCK_ACPI_DPTC for Morthal boards, to enable
support for the low/no battery boot feature.
BUG=b:217911928
TEST=build_packages --board=skyrim chromeos-bootimage --autosetgov
Change-Id: I3eb6bee6601e34420a90f33f8f2c45cf3fe37f9b
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70216
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I20c3298a920396718f0dc036e57faf8e46b82b2c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70253
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add RTD3 support for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec
BUG=none
BRANCH=firmware-brya-14505.B
TEST=Insert a SD card or NIC AIC on PCIe slot1 and run
'suspend_stress_test -c 1'. The RP8 should not cause suspend issue.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ieb7d207a7ec3763bad3e82522e86a825c1ed00b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70119
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
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Add the RPL CPU power limits to kano and zydron's power limit table.
BUG=b:261127266
BRANCH=brya
TEST="emerge-brya coreboot chromeos-bootimage", flash zydron with
image-zydron.serial.bin and verify zydron boots successfully to kernel.
Change-Id: I369c5d7a9a3db0c3e7184a23b0f159ed715b5a50
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70238
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For geralt project, we also support MIPI panel as our firmware display.
So add this patch to configure ddp to choose eDP display or MIPI panel
display.
BUG=b:244208960
TEST=test firmware display pass for both eDP and MIPI panel on MT8188
EVB.
Change-Id: I06f38b1889811274588c26e9284da4d502acf38b
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70181
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is added at runtime.
Change-Id: Ife2865f91e3d046bc66e423b2054f56176f57fc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69300
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is added at runtime.
Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69299
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is added at runtime.
Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69298
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.
This removes the need for a magic lapic in the devicetree.
Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Zork boards will not boot without PSP verstage/VBOOT, so select it
by default.
Change-Id: I2447bf69baefd5560a0153dcd3d9b87b0a91a3f9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69763
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds PCIe based SD controller at RP 7 (from RP 11) with
Proto 1 schematics dated 11/30.
Additionally, added the RTD3 entries for the SD controller.
Finally, ensured that EN_PP3300_SD (GPP_D03) is configured in
bootblock and SD_PERST_L (GPP_D02) is configured in romstage to
meet the power cycle requirement.
BUG=b:242917011
TEST=Able to build and boot Google/Rex. SD card detection is due
for the Proto 1 hardware.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23d53e4d61ec36d2145f9e5816d97d13eb5b219e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70064
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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This patch drops the usage of reading `board_id()` while performing
the GPIO configuration.
The reason to drop the board_id check is to ensure that GPIO
configuration for MLB (mainboard) would remain the same and the only
GPIO PIN configuration that differs would be due to usage of having
different DBs (daughter board) which will be taken care using
CBI (and fw_config.c file) in coreboot.
Additionally, drop unused early GPIO default configuration table.
BUG=b:260804656
TEST=Able to perform the GPIO configuration and able to boot
Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I96cafd1c904001cbf4199977e9e721afe5eab470
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Enable this feature, and it can use the probe statement in devicetree
to cache of fw_config field as oem string.
TEST=With CBI FW_CONFIG field set to 0x1561
localhost ~ # dmidecode -t 11
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
String 1: AUDIO-MAX98357_ALC5682I_I2S
String 2: CELLULAR-CELLULAR_PCIE
String 3: UFC-UFC_MIPI
String 4: WFC-WFC_MIPI
String 5: DB_SD-SD_GL9755S
Change-Id: I6cb35eb9c0fbe32764ca76bb7a929cc92fc38404
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70228
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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NVMe is determined by a logical bit 1, not the physical SKU pin.
Thus, (logical) sku_id & 0x2 == 0x2 would mean that the device has
NVMe enabled on it. Previously, I thought that it was tied to a
physical pin, but this is not correct.
BUG=b:254281839
BRANCH=None
TEST=flash and boot on villager and make sure that NVMe is not
initialized in coreboot.
Change-Id: Iaa75d2418d6a2351d874842e8678bd6ad3c92526
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70230
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ied55add6d7549f165d8b97032d7f21ede0ce2dde
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Fixes using USB-C devices in either orientation on left-side USB-C
port.
Test: Plug USB-C device in both orientations on left-side USB-C port,
check speed with lsusb -t.
Change-Id: I9fbc53bb51a5225e92b0b6bb9ced87a0ab90c9ce
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69702
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add WiFi SAR table for zydron.
BUG=b:260770999
TEST=build FW and checked SAR table can load by WiFi driver.
Change-Id: I8d5f966c7af3ac6d9923d4f6c851bfb340f31fab
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required
for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using
8254 timer counter 2 output. However when 8254 timer is used, S0ix
will not work as 8254 has to be gated instead. For further info on
s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified
Checklist).
This CL also disables s0ix because it is not required by the
platform.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67553
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update VBT configurations for DP++ and DP dongles support.
Tested working on customer's side.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I7aa34297a10bf16b9043140bff91fd3a8c4009d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70154
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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"use_crt" and "use_lvds" are boolean, so use "true/false".
Change-Id: I5b5b42c27351331ad40fbe92fb87390cb1284aa9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70148
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0# in
system76/ec@cc3effb6a451 ("board/system76/common: use SLP_S0# pin for
modern standby detection"), DevSlp blocks suspend entry. Disable it
until it is fixed.
Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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The Galago Pro 6 (galp6) is an Alder Lake-P board.
Tested with a custom edk2 UefiPayloadPkg.
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- M.2 NVMe SSD (with MZVL2500HCJQ)
- All USB ports
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Windows 10 and Linux 6.1
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- S0ix suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.0.6
- Internal flashing with flashrom v1.2-1087-gde016a17
Not working:
- Detection of devices in TBT slot on boot
Change-Id: I8940fb3777d7f18393ef50baec32f9445b375648
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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The Piglin & Hoglin boards were built with a couple of different sizes
of ROM chips. Despite this, the desire was to use just a single FMD
file. The different sizes are already accounted for in Kconfig, so
add the Kconfig size here to be used.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ia75725b0c4d61e832c94160fa4cd455e89c60274
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Adjust scl_lcnt, scl_hcnt, sda_hold value for I2C5 to meet
touchpad SPEC.
BUG=b:260540852
BRANCH=firmware-brya-14505.B
TEST=build, checked TP function work normally,
and measure the timing meet SPEC
tLOW ~1.72 us
tHIGH ~0.63 us
tHD ~0.69 us
fscl 383 kHz
Change-Id: I9036a604a90558911c4f8a492db9f1f0f28bf404
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Fine-tune eMMC DLL based on Xivu EVT system.
BUG=b:256538132
TEST=executed 3000 cycles of cold boot successfully
Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be
Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69892
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable DPTC support for frostflow.
BUG=b:257187831
TEST=emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iac7b8789a5189827fe98cb06328d666300841a5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69931
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refer to brask board to add audio settings for gaelin.
BUG=b:253177160
BRANCH=firmware-brya-14505.B
TEST=Able to verify audio playback on gaelin with kernel v5.10.
Change-Id: Ibc8cacce6cb4b3e55fc7332bb9eb9ac20848fc5b
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Modify USB2.0 port[4] settings to support camera.
BUG=b:238252678
BRANCH=firmware-brya-14505.B
TEST=with brask overlay changes, camera in camera app works
Change-Id: I42325b75e129429ee451ded6a2086fd3808e581a
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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GSPI2 interface is not used on this mainboard and can be disabled. It
will in addition remove the warning of a leftover static device in the
log.
Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Commit 2c102232e8f7 ("mb/amd/chausie,google/skyrim: increase
RW_MRC_CACHE size to 120 kByte") increased the MRC cache size, but with
the change the default AMD_FWM_POSITION_INDEX which is 5 for the 16MByte
flash size, the amdfw part won't be placed on the expected position,
since the cbfs header is in that exact location and cbfstool places the
amdfw part right after that. Change the AMD_FWM_POSITION_INDEX to 4 for
the non-chromeos builds to work around this.
TEST=Non-chromeos chausie build now boots and doesn't fail any more
before releasing the x86 cores from reset
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70133
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new audio sku configure for Pujjo board.
BUG=b:260538412
TEST=Boot to OS on pujjo and check that audio are configured
based on fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia9ddc683945002a0b19efd67006e1983b2eb9f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of using a fake lapic device hook up the cpu cluster to chip
cpu/intel/model_206ax.
The lapic device is also not needed as the mp init will allocate it for
the BSP at runtime.
Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Also remove the now unnecessary comments from the devicetree.
Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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When retrieving the SKU id value through the sku_id() function in
mainboard_needs_pcie_init(), we only want the values in the lower 5
bits as we can only represent SKU id up to 27. Everything in the
higher bits should be masked out because they are not needed.
BUG=b:254281839
BRANCH=None
TEST=Make sure that NVMe is not initialized
Tested on a herobrine board with SKU id 0
Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70164
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, we are getting the sku id from the EC every time we call
the sku_id() function. However, this will never change so we only
need to retrieve it once. Inserting exit condition if sku id is
already set, then don't get it from the EC again.
Also, removing the ram_code function, which does nothing right now.
There is already a weak stub_function for this in
src/lib/coreboot_table.c that already does the same thing.
BUG=b:260740438,b:182963902
BRANCH=None
TEST=make sure image still boots to login on herobrine device
Change-Id: Ia787968100baf58a41ccce0cf95ed3ec9ce1758a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
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Configure birman GPIOs per schematic 105-D67000-00B v0.7
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I5459efb38431e568e25405c440b5b9cf1354f02f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for
dynamic table switching support.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: Icbf9348447b9e7acc0caa8082cf5dd00853da37a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
FSP silicon discards the request if the Voltage Regulator or SoC does
not support the feature.
BUG:b:259057787
TEST:Verify that the feature is enabled by reading from pcode
No PnP regression observed
BRANCH=firmware-brya-14505.B
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7e318534f1429af8ec06048430966344ddd346a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69579
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jeremy Compostella <jeremy.compostella@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This only moves CPU configuration to a common place. Other PCI devices
can be done in follow-ups.
Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch supports multiple camera modules based on FW_CONFIG.
BUG=b:251235140
TEST=Test the changes with ov2740/hi556 camera.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib0a4f46d889e9f6c2898efee6825cf2d02252d87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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This patch enables crashlog for all brya projects.
BUG=b:190756531, b:259978562
BRANCH=None
TEST=emerge-brya coreboot chromeos-bootimage & ensure the crashlog
PCIe device 0xa.0 is enabled and intel-pmt kernel driver is
loaded.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ib632c8ac9ea7a4f0e0b08b96eb149f8ef1386be0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68526
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This change disables unused PCIE RP8 and CLKSRC4. Without this change
sasukette cannot enter into s0ix properly.
BUG=b:259891452
TEST=Build and verified in sasukette
Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I70fb470b63ddd06f1d1e34deaea296d81e24f75f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70058
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI DmaProperty for ethernet devices.
BUG=b:259716145
TEST=Verified SSDT on google/osiris.
Before:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
}
}
After:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
}
}
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I647593fd02644d30cd21b60d8305c0ec55dc64cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70017
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:259716145
TEST=TBD
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ifaa0912b38129ed2db01fb78ed39c0db89e746fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70018
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new ram_id:0100 for memory Samsung K3LKBKB0BM-MGCP.
Add new ram_id:0101 for memory Samsung K3LKCKC0BM-MGCP.
The RAM ID table has been assigned as:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNCP3MLYR-N6E 1 (0001)
MT62F2G32D8DR-031 WT:B 2 (0010)
H9JCNNNFA5MLYR-N6E 3 (0011)
K3LKBKB0BM-MGCP 4 (0100)
K3LKCKC0BM-MGCP 5 (0101)
BUG=b:254758998
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8ff879ff7185f5a0ca1b9632820aba3b0f5d02c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
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Set Package Power Parameters from AMD DevHub document #57316.
"stapm_time_constant_s" = "200"
BRANCH=none
BUG=b:257187831
TEST=emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I15a69df1436aba05bc19eaffd79394e5ca9bdb3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69565
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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The Skyrim devices share a common set of DPTC values to enable booting
with low/no battery. Rather than duplicating them in each variant's
overridetree.cb, move them into the baseboard/devicetree.cb.
BUG=b:217911928
TEST=tast run <IP> power.ShutdownWithCommandBatteryCutoff
Change-Id: I20f0a8259c2fc986da23026da88feadd69942046
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69904
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Name a variable based on its utility. `is_external` variable adds
`ExternalFacingPort` _DSD property to an ACPI device hence
rename it to `add_acpi_external_facing_port`.
BUG=b:259716145
TEST=Build google/rex with this flag and verify it in SSDT at
runtime.
SSDT snippet:
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
Package (0x01)
{
Package (0x02)
{
"HotPlugSupportInD3",
One
}
},
ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"),
Package (0x01)
{
Package (0x02)
{
"ExternalFacingPort",
One
}
}
})
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69970
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch will create the baseboard structure for mtlrvp. Changes
include,
1. Adding Baseboard config for mtlrvp in Kconfig
2. Move gpio.h to corresponding baseboard directory
3. Append header reference to CPPFLAGS_common in Makefile.inc
BUG=none
TEST=FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I82acb6879fecb242014258f2c358804d5abbbd48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69971
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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mayan is the reference board for the morgana SoC. It needs to be
updated to match the actual board design as well. amd/mayan is started
as a copy of amd/birman.
Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70010
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on latest schematic to update the gpio table.
BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=marasov emerge-brya coreboot
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I03b443826d39182eaf23ad3e4e0ba8d6b8a93022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69180
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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SATA is not supported on google/rex hence disable it.
BUG=none
TEST=Build and boot to google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I35a742ab9782feed86c3af514505d870d181b34b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Enable NVMe GPIOs based on fw_config and add NVMe to devicetree.
Note, eMMC and NVMe are not probed in devicetree. On first boot in
factory, the device needs to boot with unprovisioned fw_config, so all
storage devices should be enabled when unprovisioned. Currently,
devicetree disables all probed devices when unprovisioned. If we want
eMMC and NVMe to be probed, support needs to be added for enabling
probed devices when unprovisioned.
BUG=b:259211172
TEST=Verified by ODM. On craask, LTE and WCAM still work. On craaskneto,
eMMC and NVMe SKUs can both boot.
Change-Id: I76a056cddff2246cfb5bb26ddbdfc333b49d9aaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69958
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Follow thermal table from thermal team.
1. Modify TS1 passive policy to 68.
BUG=b:249446156
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69960
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As for mainboard mc_ehl1, a hard real-time dependency is also required
for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive
which in the end leads to an increased number of cache misses. Disabling
the L1 prefetcher boosts up the performance (in some cases by more than
10 %) in this specific use case.
Change-Id: I07b27dd672533e693a6c2987d16f54333850760e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Move the chip configuration to the cpu cluster device.
It looks like none of the devicetree were featuring a lapic 0xacac,
nor was tcc_offset ever set, so this remains a NOP.
Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59315
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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|
These boards do no fill MADT with useful information.
Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.
Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
