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Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.
I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.
Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.
Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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sustained_power_limit = 12w
fast_ppt_limit = 24w
slow_ppt_limit = 20w
BUG=b:162377903
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage
Change-Id: I9baf9990e26edbbadfba85bc16b380c46684033d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change updates TGLRVP configuration to have USB Type-C connector
device properties filled into ACPI SSDT.
TEST=Built and booted to kernel on tglrvp boards. Verified the USBC
scope under LPCB.EC0.CREC with required connector device properties.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory part being added is:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR
BUG=None
TEST=Build the magalor board.
Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add interrupts for all enabled superio devices to quiet the warning
about missing interrupts in devicetree.
Vendor uses interrupt 0x00 for all devices except SUART* and KBC, so
let's do that, too. This also changes SWC from 0x0b to 0x00.
Verified with superiotool on X11SSM-F.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I7a6dc7345f020e53415a7d0d104ce93ab4b194fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonas Löffelholz
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add VPD variables for enabling/disabling FRB2 watchdog timer and setting
the timer countdown value in romstage. By default it would start the timer
and trigger hard reset when it's expired. The timer is expected to be
stopped later by payload or OS.
Add RO_VPD and RW_VPD sections.
Tested on OCP Tioga Pass.
Change-Id: I53b69c3c5d22c022130fd812ef26097898d913d0
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add bluetooth reset gpio 143 to dalboz baseboard devicetree
Add bluetooth reset gpio 14 to trembyle baseboard devicetree
Remove bluetooth reset_gpio when not supported on a specific board
variant.
BUG=b:157580724
TEST=Boot Ezkinil with Realtek 8822CE, observe log
[ 12.240720] Bluetooth: af_bluetooth.c:bt_init() HCI device and connection manager initialized
[ 12.249272] Bluetooth: hci_sock.c:hci_sock_init() HCI socket layer initialized
[ 12.256520] Bluetooth: l2cap_sock.c:l2cap_init_sockets() L2CAP socket layer initialized
[ 12.264575] Bluetooth: sco.c:sco_init() SCO socket layer initialized
[ 12.273700] usb 3-2: GPIO lookup for consumer reset
[ 12.273702] usb 3-2: using ACPI for GPIO lookup
[ 12.273705] acpi device:18: GPIO: looking up reset-gpios
[ 12.273707] acpi device:18: GPIO: looking up reset-gpio
[ 12.273711] acpi device:18: GPIO: _DSD returned device:18 0 0 0
[ 12.273737] gpio gpiochip0: Persistence not supported for GPIO 14
[ 12.273960] usbcore: registered new interface driver btusb
Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Two usb Type-C ports under the actual mux device. Each port has its own
ACPI device entry. These nodes are the ones that the USB Type-C
port/connector device will refer to in order to configure the mux.
TEST=Built image-tglrvp-up4.bin successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I8423ddbb5bc189899a9e19e7da6e2ee7b7fecc18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Rearrange code to unify with the rest of xx20/xx30 boards. No functional
changes - just smaller diff output.
Change-Id: I5867b2a90b2e53a3a9dd919701f1e185cb39cf78
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Replace functionally identical files with t440p/acpi/superio.asl which
is licensed under more flexible terms (GPL-2.0-only or no licensing
terms vs. GPL-2.0-or-later). Apart from licensing terms these files are
identical.
This makes diff between boards smaller.
Change-Id: I1cd4a85b65ceaa0a383416e7276ad41a41783cb7
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43685
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
BUG=b:161215903
BRANCH=NONE
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib61af2399541c4caf4a310a34e778e0ba1cbd3ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43802
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select the drivers for ALC5682 codec and MX98360A spk amp
BUG=b:161407664
BRANCH=NONE
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibe3d878b1058bfae4143d96be854884e61394ad5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Follow schematic to modify USB port setting and clean up I2C clock tuning.
USB2 [0]: USB Type C Port 0
USB2 [1]: USB Type C Port 1
USB2 [2]: None
USB2 [3]: USB Type A Port 1
USB2 [4]: None
USB2 [5]: Camera
USB2 [6]: None
USB2 [7]: WLAN module - BlueTooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: USB Type C Port 1 (Sub/B side)
USB3 [2]: None
USB3 [3]: USB Type A Port 1
USB3 [4]: None
USB3 [5]: None
BUG=b:161407664
BRANCH=NONE
TEST=Build the coreboot image on madoo board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ia73593f52adee3806e725127891f084a08bf1360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43750
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow schematic to modify some GPIO pins.
GPP_D12 - NC Pin
GPP_D13 - NC Pin
GPP_D14 - NC Pin
GPP_D15 - NC Pin
GPP_E0 - NC Pin
GPP_E2 - NC Pin
GPP_H6 - NC Pin
GPP_H7 - NC Pin
GPP_S02 - NC Pin
GPP_S03 - NC Pin
BUG=b:161407664
BRANCH=NONE
TEST=Build the coreboot image on madoo board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I85aadfb0d020055eec921c7646c16ae6c95a606f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43745
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update dq/dqs mappings based on voxel schematics.
BUG=b:155062561
BRANCH=none
TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ida248094a1477fe457026e18f313385082ee71f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.
BUG=b:153588771
TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If59502aec7c3ab55864a518d626cde52aee18373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43746
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This copies over the USB daughterboard device tree config from volteer
to volteer2. These two boards are basically identical in this area so
the config should also be identical.
BUG=b:158673460
TEST=none
Change-Id: If8a82bc18b36d92a1c851b49612edfbefa18ec54
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:161734657
TEST=Ensure that the discrete WiFi information is built into ACPI table.
Scope (\_SB.PCI0.RP01)
{
Device (WF00)
{
Name (_UID, 0x923ACF1C) // _UID: Unique ID
Name (_DDN, "WIFI Device") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x43,
0x03
})
}
}
Change-Id: I9a9259e167fc213291b89e151729553ec4649eaf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43769
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This applies what commit 79572e4f32f844f60338d1aafdba6b94f4111a5c does
to the devicetree settings of amd/mandolin.
Change-Id: I6cc0a2b60b13a809016225caf3c89f730deb4ce0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Since there aren't any other variants, we can move things between the
devicetree and the overridetree.
Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change.
Change-Id: I54aac67237a3850dbf11f58bd41aba87505214f3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43927
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ief8d53b79918d4d68bf10650ff796a27b67d862b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change.
Change-Id: I655bc7576e8ff48258a2a19387e01372f4bbea3d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
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Todor is created to take the place of terrador therefore
copying terrador content into todor's setup.
BUG=b:162110806
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TODOR
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I63151728a04f2252ca8a77158a2656ad8b1e1b51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Create the todor variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
In addition,
* sort the variant names in alphabetical order.
* todor uses the same config options as terrador.
BUG=b:162110806
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TODOR
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I7aa7acf1f3c3cc14b92ded05d5868818a627a432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Use the common driver to configure the GPIOs on the Delta Lake
platform as done for Tioga Pass in commit 89d2aa0. The GPIO
settings are dumped by inteltool with original UEFI firmware,
then use intelp2m to generate header file.
TEST=Dump GPIO settings by Intel ITP and check if match gpio.h.
Change-Id: I8005d4caa2d87b6831099bfec3a40246224f3cb5
Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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All boards disable PIRQs, except purism/librem_bdw. Since IRQ0 is
invalid and modern OSes don't use PIRQ routing, disable the PIRQs.
Change-Id: I93b074474c3c6d4329903cab928dc41e1d3a3fb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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All boards disable PIRQs. They aren't used on modern OSes anyway.
Change-Id: I1351fd4a3910e8cf2e9afe51dc2e82c7464de403
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Create the eldrid variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:162115131
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_ELDRID
Signed-off-by: MiceLin <mice_lin@wistron.corp-partner.google.com>
Change-Id: I1cd07ee7a87335e1e0b51d65c26bffc3bc46037c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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The over-current pin mapping matches the board schematics.
Change-Id: I23fd208680dcb52f5adaa144f00cb46bc7a21b91
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Some smart battery patches have been backported to the ChromeOS 4.19 kernel,
and userspace can now access smart battery data from sysfs instead of using
the hacky ectool instead.
Also change all space indents into tab indents while we're here.
BUG=chromium:1047277
TEST=confirmed a /sys/class/power_supply/sbs-i2c device shows up
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I43687e63e4c1a7756c117129ced20749afc1b9e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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LPDDR4x DRAM table for burnet/esche:
[1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB"
[2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB"
[3] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB"
[4] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB"
BUG=b:161768221,b:159301679
BRANCH=master
TEST=emerge-jacuzzi coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ida7ab877c3f7e10a67680b69a1d724ec734d2928
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Use gpio_keys driver to add ACPI node for pen eject event. Also
setting gpio wake pin for wake events.
Removal and insertion (both edges) triggers IRQ and only removal is a
wake event (rising edge).
Adding for both Volteer and Volteer2 variants.
BUG=b:146083964
BRANCH=None
TEST=tested on a Volteer
Change-Id: Ida3217a5b156320856ce3302c2623eba2230f28d
Signed-off-by: Alex Levin <levinale@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43764
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update delbin configuration include GPIO, memory SPD table, I2C devices
and USB type C.
BUG=b:158797761
BRANCH=None
TEST=emerge-volteer coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I59ce4720e0ffeeeb2c9440bb300686def80211ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42301
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MRC automatically detects the DDR type and sets Rcomp resistor
and target values for JSL and does not require explicit programming.
Change-Id: Ia130765e2cb91d6a39ad00ebbab20e7e87fa42d1
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Create the magolor variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:58540772
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_MAGOLOR
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I3e39e650b82a0aa629a48a00227700b058effb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Fixes a bug in Makefile.inc, which did not allow building ROM image
with ramstage.c from motherboard configuration.
Change-Id: I70d8a2e1f53e2fa56d514361116a55f175407753
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43457
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use
PIRQ routing, so we might as well zero the other bits for consistency.
Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots.
Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, the message below is printed, suggesting it’s decimal
notation:
coreboot-4.12-1530-g7acbd5fc45 Sun Jul 19 07:47:58 UTC 2020 smm starting (log level: 7)...
EC event 48
GPI (mask 1000)
Prepend 0x, so it’s clear it’s hexadecimal notation.
EC event 0x48
Use the command below change all places:
git grep -l 'EC event %02x' | xargs sed -i 's/EC event %02x/EC event %#02x/'
Change-Id: I8d1e6434a0e550c5a19576f9f7fea05e7a812e49
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set this fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: I6a6b745bdaacb1c4fbf032e4ce54cb25a72d790a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43561
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set these fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43454
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update ELAN i2c-hid touchpad configuration
BUG=b:160741785
BRANCH=None
TEST=Verify touchpad is working fine.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I098d8a305c6e04af1562a545ff4af6383665798b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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This effectively reverts commit 5086ccef
(mb/purism/librem_skl: Fix CLKREQ for 15v3 NVMe).
Some Librem 15v3/v4 boards are showing issues with NVMe detection or
booting via SeaBIOS, so revert this until a proper fix can be found.
Test: build / successfully boot Librem 15v4 with problematic NVMe drive.
Change-Id: I0659f77bbe693f3d3b192a28ff3ef013658930cc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43490
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For devices sharing same firmware, there may be few customization based
on SKU ID - for example being clamshell or form factor. On Kukui and
Jacuzzi platforms the SKU ID is defined on AP SOC, so we have to send
the information to EC.
BUG=b:161767717
TEST=make -j # builds and boots on Juniper
BRANCH=kukui
Change-Id: I8ffdd9fd1e609c1dd4b0e22dc7aab560ccdc842e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43788
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust GPIO setting to match boten design
BUG=b:160741777
BRANCH=NONE
TEST=Add gpio.c for boten
Signed-off-by: Yan Liu <yan.liu@bitland.corp-partner.google.com>
Change-Id: I4eafee608f657f8ec5a06caf6e99b08b3330512b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43277
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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HDMI DDC GPIOs were configured as NC till now in waddledoo.
This may cause HDMI i2c transfer to break and EDID read will
fail due to wrong configuration
Configuring these GPIOs as NF in coreboot to fix the issue.
BUG=b:160324327
BRANCH=None
TEST=HDMI works on DDI2 onn Type-C port
Change-Id: If02f062132d7c3b01b07ea9401e81f451df35c3c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43294
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tune I2C bus3 frequency and insure it meets I2C spec.
BUG=b:161650117
TEST=flash coreboot to the DUT and actual measured I2C bus3
make sure it meet Spec.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ifa9f0bce723f55a12fd2313788c995f8326e3e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I0297c8c4008d9e448793c38a3758dced9ede0d7e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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- Update MAINBOARD_PART_NUMBER for TGL variants
- MAINBOARD_PART_NUMBER is reported as FRID on acpi
- This is required for cros_config to differentiate
across TGL variants.
- Mosys uses cros_config to identify TGL variants using
data read from FRID
Bug=none
Test=build and boot coreboot on TGLRVP UP3 hardware
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I11d4ab2a5b6ade6c50988a9fec4d9866fe79d7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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Set up a 8-byte I/O range at 0x290-0x297 as PIIX4's generic device 9,
which activates a chip select when this range is accessed.
On the P2B family it connects to the W83781D hardware monitor,
allowing access to it over the ISA bus, just like vendor firmware.
Apparently this does not work on p3b-f, but no ill effects observed
either.
TEST=On p2b-ls lm-sensors can detect chip and get readings over ISA.
Change-Id: Iaed1df7230359e94c580c305f4769c8bb4f5fce0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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|
Change-Id: Iac0f0c3d102a9a900ac168f8be907349d9a3dd42
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43565
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:155002684
TEST=build drawcia, and check touchscreen can work
Change-Id: I29a891e07bb3c1d8ebe17666c18bfcf3bc1c361d
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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The only reason to use a named choice statement is if you plan on
having the choice statement in multiple places. Since none of these
are used in multiple places, we can get rid of the names.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie5f84e9dc38050234976bd193ac5fbf649e564f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Variants that select BASE_ASUS_P2B_D will also get
MAX_CPUS==2 below, so this was redundant.
Change-Id: I9048a4821f19d90e1489b09e294d2551941abf10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43809
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib41341b42904dc3050a97b70966dde7e46057d6b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I7a6ddf95d085490d52e00ade7bac23e8c8849427
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42865
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9730680a8359407a2a03dbb7243a6547420e1f39
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43856
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's a `GPL-2.0-or-later` version of this file in volteer2, so use it
in place of these weirdly-licensed files.
Change-Id: Icde2f6539d9c726d6967350f74e7bc015e01e7b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Put them in common code just in case something depends on the values.
Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I6375f97bc2a30beba5882792328f26e0675621cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43867
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This applies what commit 79572e4f32f844f60338d1aafdba6b94f4111a5c does
to the devicetree settings of the zork devices.
Change-Id: Ife94818d771f137e56c51ad1598148f60fcf5345
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43820
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4ea2fb83522d8810fe84e0a3f42bf44f2f911461
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43819
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:161923068
Change-Id: I67f23c0602e345fbd806e661a4462cf07f93ef64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since FSP pre-populates the UPD struct with the non-zero default values,
coreboot shouldn't set them to zero in the case that they aren't
configured in the board's devicetree. Since all parameters being zero is
a valid case, this patch adds another devicetree option that applying
the devicetree settings for the USB2 PHY tuning depends on being set.
BUG=b:161923068
Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set this fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Ie3ee2eadc08826d49e8517c83ab6831398e3aa93
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43455
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Change-Id: I85c20d282949b51efd7cdd6f6e79b0b84ff62e2b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set power limits in devicetree for Tiger Lake Y-SKU based volteer
variant boards.
BUG=b:152639350
BRANCH=None
TEST=Built and tested power limits on volteer variant board.
Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- remove comments (except the GPIO group), because it does not contain
useful information that helps to understand the circuit, which we do
not have;
- remove empty lines between macros;
- use a shorter PAD_CFG_GPI_INT() macro instead of
PAD_CFG_GPI_TRIG_OWN() to set DRIVER mode.
Change-Id: Ia7111341aab6f400da70d936849e4d4c9406905b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Converts bit field macros to target PAD_CFG_*() macros, which were
hidden in the comments. To do this, the following command was used:
./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F,
remains identical.
Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35679
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fixes some bit fields to convert to target macros PAD_CFG_*() macros.
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Change-Id: I291f5f0f34505c466b610aa4049c8cc35937d140
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42918
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch excludes bit fields that should be ignored [1] in order
to convert current macros to target PAD_CFG_*() macros. The following
commands were used for this:
./intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
/intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer
Disable (bit 9:8) for the native function, because it does not
affect the pad in this mode.
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Change-Id: Icdf366a8d416598cec5afcb9a0fae6bf7ecd7ba0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42917
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In the middle of the Great DPTF Refactor of 2020, new volteer variants
were added, but their dptf.asl files are no longer used, so delete them.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I52f2042aa870a29026eb9fe122340ad07654e706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Use the intelp2m utility [1,2] with -fld=cb options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to
generate the target macro in the comments, so that it is easier to
understand what result we should get:
./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser
[2] https://review.coreboot.org/c/coreboot/+/35643
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F,
remains identical.
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42916
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use macros to configure each of the IIO ports instead of an array
of some unknown parameters. This will clean up the code and make
it easier to read.
Tested with BUILD_TIMELESS=1, Tioga Pass, remains identical.
Change-Id: I2911992435a6c93624525426d56212f821abb866
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43502
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When RTC failure is detected, send IPMI OEM command to issue CMOS clear.
This is to let the payload (LinuxBoot) handle the IPMI OEM CMOS
clear command by resetting RTC data, erasing RW_VPD (TODO) and add a
SEL, then reboot the system.
Tested=on OCP Delta Lake, after removing RTC battery we can see the above
flow can be executed correctly.
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43005
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Populate SMBIOS data from OCP_DMI driver read from FRU
2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting
PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SKUID
51 - Garfour EVT (non-touch, TypeA DB)
52 - Garfour DVT (touch, HDMI DB)
BUG=b:161554087
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: I3cb17c2b665c303da210817a531c869c6324b249
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Henry Sun <henrysun@google.com>
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The Raydium ACPI entry currently provides a reset GPIO and an _ON/_OFF
method to the kernel. These are contradictory. The ownership of the GPIO
should be mutually exclusive between either the OS or the FW. Since we
have two methods exposed this causes the OS to reset the TS twice. Once
using the _ON method, and once using the GPIO. Additionally the _ON
method is waiting for 20ms after reset while the OS driver uses a 50ms
delay. The Raydium TS datasheet specifies 20ms for FW ready time, so the
OS driver is adding additional padding.
The reference design has a 32ms rise time on the reset line. So without
this patch, the OS tries to reset the TS using the _ON method and it
waits for 20ms. This is not enough time for the reset line to reach
high, let alone account for the FW ready time. The OS driver then tries
to reset the device by toggling the GPIO. It waits 50ms which is still
2ms less than required.
This CL removes the GPIO from being exported in the _CRS so the OS
driver won't try and reset the device. It also increases the reset delay
by 32ms to account for the rise time.
This isn't a complete fix. I think that the slow rise time is causing
some kind of metastability in the TS reset hardware. Using a script to
bind and unbind the TS driver, the TS device becomes unresponsive after
~200 iterations. The only way to reset the device is to power cycle.
The TS power is also not currently controlled by the power resource.
This means that we have no guarantee over when the reset line is
toggled. This will lead to issues while spending and resuming.
BUG=b:160854397
TEST=Boot trembyle and make sure TS works. Suspend/Resume trembyle 300+
times.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I23131be5d7109eed660a8bd6e2c156c015aa3c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Earlier versions of Dalboz did not correctly handle HS400. One fix was
to add stitching vias, but these boards did not have them. b/156539551
Another possible fix is to add tuning parameters including drive
strength, but that is still a WIP. b/158959725
This should correct OS load failures in the meantime by running the bus
slower.
BUG=b:158845662
TEST=build, flash, boot sku 0x5a80000c to OS
BRANCH=None
Signed-off-by: Eric Peers <epeers@google.com>
Change-Id: Ia3e7a641bde04c5a7be29bf91c38dd8c110ed17a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43572
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the dirinboz variant of the dalboz reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:161579679
BRANCH=master
TEST=util/abuild/abuild -p none -t google/zork -x -a
make sure the build includes GOOGLE_DIRINBOZ
Change-Id: I33c03080ffbe0bca61acf4144417b9f5fff6389f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree.
BUG=b:157971972
BRANCH=sarien
TEST=local build and boot from SATA/PCIe-eMMC storage successfully
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43669
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add PCIe-eMMC bridge bayhub 720 on Sarien.
BUG=b:157971972
BRANCH=sarien
TEST=local build and boot from storage successfully
Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Reset the Touchscreen (TS) and disable the stop GPIO (report switch) at
the same time. Add a delay of 100 ms after disabling the stop GPIO. This
will ensure the required delay is inserted for both reset and stop
disable GPIOs simultaneously.
BUG=b:152936541
TEST=Build and boot the waddledoo mainboard. Ensure that the SiS
Touchscreen is functional.
Change-Id: Icbfb5e07a28ab72b1ff696ad1183a6c2173dcaac
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
BUG=None
TEST=Build the drawcia board.
Change-Id: Id05c0b2a87b64bfedc761949cbc8ad6cf7dd73a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change does the following:
a. USI_REPORT_EN is no longer set to high in coreboot. Instead
GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this
pad as required.
b. Appropriate delays are added for power-down sequencing:
- Delay after REPORT_EN is disabled - 1ms
- Delay after RESET is asserted - 1ms
BUG=b:159501288
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If4d12fa0d4f4e5123d8fdccdabda996dcafa4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Morphius uses Goodix touchscreen and not G2 touchscreen. This change
updates hid and desc properties in devicetree accordingly.
BUG=b:159501288
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I2527fa5409bb127ac225c6fb2a5f1bc24895f6cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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GPIO_91 is added to ACPI using the device tree entry for codec. So,
this change drops the TODO from GPIO table.
Change-Id: I9c2e91465ab554126531f8512028360ae5fb316d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change configures all missing pads in ramstage for dalboz
reference. This ensures that the state of all pads is set correctly
for the payload/OS. Also, all the pads for the platform are configured
in baseboard gpio table in ramstage to ensure that variants can
override any pads if required.
BUG=b:154351731
Change-Id: Ia30da908d3827177a7b3594ffba38bff81018ab9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change configures all missing pads in ramstage for trembyle
reference. This ensures that the state of all pads is set correctly
for the payload/OS. Also, all the pads for the platform are configured
in baseboard gpio table in ramstage to ensure that variants can
override any pads if required.
BUG=b:154351731
Change-Id: Idd827b6a4f995546493596f22249f8699bdf526b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change drops PULL_UP configured on pads in early_gpio table since
these pads have external pulls.
BUG=b:154351731
Change-Id: Id270e7b4f83dfa942655f513776a3b1c15c9678d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Most of the DXIO descriptors are used to configure PCIe engines and
lanes, but on Picasso system some of the DXIO lanes can also be
configured as SATA or XGBE ports.
Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The lane numbers in the PCIe/DXIO descriptor are the logical and not the
physical ones, so add logical to the corresponding field names of the
fsp_pcie_descriptor struct.
Change-Id: I7037fed225119218e87593932815aff815e83ff8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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new boards introduced to Kukui family.
esche: clamshell
burnet: 360 convertible
BUG=b:161768221
BRANCH=master
TEST=emerge-jacuzzi coreboot
Change-Id: I2245c34533549bb94c58938fee5778b8a03e2767
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
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Update .vbt file to support two DP outputs.
Change-Id: Ifd4163aafe4ef3070d04a72a4699303af72c5102
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This adds ACPI code for System76 EC and converts system76/lemp9
to use EC_SYSTEM76_EC.
Tested on system76/lemp9.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I1f693268d94b693b6764e4a3baf4c3180689f3be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Michael Niewöhner
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Add function to send POST start command to BMC. This function is
used in romstage and the POST end command will be sent in u-root.
TEST=Read POST command log in OpenBMC,
if command received successfully, message may show as below,
root@bmc-oob:~# cat /var/log/messages |grep -i "POST"
2020 Jul 15 16:36:11 bmc-oob. user.info fby3-v2020.23.1:
ipmid: POST Start Event for Payload#2
root@bmc-oob:~#
Signed-off-by: TimChu <Tim.Chu@quantatw.com>
Change-Id: Ide0e2a52876db555ed8b5e919215e85731fd80ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Create SMBIOS type 9 by getting PCIe config from BMC.
TEST=Check SMBIOS type 9 is created correctly on different SKUs
Change-Id: Ifd2031b91c960ff2add8807247271eb7c38a0bf2
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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